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GET /api/patches/1585799/?format=api
{ "id": 1585799, "url": "http://patchwork.ozlabs.org/api/patches/1585799/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-10-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220128153009.2467560-10-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2022-01-28T15:29:46", "name": "[PULL,09/32] hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6930ea49cffd0970c497b540b7c79952431f8c51", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-10-peter.maydell@linaro.org/mbox/", "series": [ { "id": 283405, "url": "http://patchwork.ozlabs.org/api/series/283405/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=283405", "date": "2022-01-28T15:29:53", "name": "[PULL,01/32] Update copyright dates to 2022", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/283405/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1585799/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1585799/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=v7YTJihv;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4JljsX0rgpz9t3b\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 29 Jan 2022 03:41:52 +1100 (AEDT)", "from localhost ([::1]:42962 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1nDUJp-0002c6-Ps\n\tfor incoming@patchwork.ozlabs.org; Fri, 28 Jan 2022 11:41:49 -0500", "from eggs.gnu.org ([209.51.188.92]:58130)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1nDTDQ-0002Is-4s\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:31:08 -0500", "from [2a00:1450:4864:20::32e] (port=46977\n helo=mail-wm1-x32e.google.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1nDTDK-0006Oj-T0\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:31:07 -0500", "by mail-wm1-x32e.google.com with SMTP id\n c190-20020a1c9ac7000000b0035081bc722dso4289773wme.5\n for <qemu-devel@nongnu.org>; Fri, 28 Jan 2022 07:30:25 -0800 (PST)", "from orth.archaic.org.uk (orth.archaic.org.uk. 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Software drivers in this scenario\nconfigure and trigger DMA operations through the controlling peripheral's\nregister API (for example, writing a specific bit in a register could\npropagate down to a transfer start signal on the DMA control interface).\nAt the same time the status, results and interrupts for the transfer might\nstill be intended to be read and caught through the DMA engine's register\nAPI (and signals).\n\nThis patch adds a class 'read' method for allowing to start read transfers\nfrom peripherals embedding and controlling the Xilinx CSU DMA engine as in\nabove scenario.\n\nSigned-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>\nReviewed-by: Luc Michel <luc@lmichel.fr>\nMessage-id: 20220121161141.14389-6-francisco.iglesias@xilinx.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n include/hw/dma/xlnx_csu_dma.h | 19 +++++++++++++++++--\n hw/dma/xlnx_csu_dma.c | 17 +++++++++++++++++\n 2 files changed, 34 insertions(+), 2 deletions(-)", "diff": "diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw/dma/xlnx_csu_dma.h\nindex 28806628b10..922ab80eb61 100644\n--- a/include/hw/dma/xlnx_csu_dma.h\n+++ b/include/hw/dma/xlnx_csu_dma.h\n@@ -51,7 +51,22 @@ typedef struct XlnxCSUDMA {\n RegisterInfo regs_info[XLNX_CSU_DMA_R_MAX];\n } XlnxCSUDMA;\n \n-#define XLNX_CSU_DMA(obj) \\\n- OBJECT_CHECK(XlnxCSUDMA, (obj), TYPE_XLNX_CSU_DMA)\n+OBJECT_DECLARE_TYPE(XlnxCSUDMA, XlnxCSUDMAClass, XLNX_CSU_DMA)\n+\n+struct XlnxCSUDMAClass {\n+ SysBusDeviceClass parent_class;\n+\n+ /*\n+ * read: Start a read transfer on a Xilinx CSU DMA engine\n+ *\n+ * @s: the Xilinx CSU DMA engine to start the transfer on\n+ * @addr: the address to read\n+ * @len: the number of bytes to read at 'addr'\n+ *\n+ * @return a MemTxResult indicating whether the operation succeeded ('len'\n+ * bytes were read) or failed.\n+ */\n+ MemTxResult (*read)(XlnxCSUDMA *s, hwaddr addr, uint32_t len);\n+};\n \n #endif\ndiff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c\nindex 896bb3574dd..095f9544767 100644\n--- a/hw/dma/xlnx_csu_dma.c\n+++ b/hw/dma/xlnx_csu_dma.c\n@@ -472,6 +472,20 @@ static uint64_t addr_msb_pre_write(RegisterInfo *reg, uint64_t val)\n return val & R_ADDR_MSB_ADDR_MSB_MASK;\n }\n \n+static MemTxResult xlnx_csu_dma_class_read(XlnxCSUDMA *s, hwaddr addr,\n+ uint32_t len)\n+{\n+ RegisterInfo *reg = &s->regs_info[R_SIZE];\n+ uint64_t we = MAKE_64BIT_MASK(0, 4 * 8);\n+\n+ s->regs[R_ADDR] = addr;\n+ s->regs[R_ADDR_MSB] = (uint64_t)addr >> 32;\n+\n+ register_write(reg, len, we, object_get_typename(OBJECT(s)), false);\n+\n+ return (s->regs[R_SIZE] == 0) ? MEMTX_OK : MEMTX_ERROR;\n+}\n+\n static const RegisterAccessInfo *xlnx_csu_dma_regs_info[] = {\n #define DMACH_REGINFO(NAME, snd) \\\n (const RegisterAccessInfo []) { \\\n@@ -696,6 +710,7 @@ static void xlnx_csu_dma_class_init(ObjectClass *klass, void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(klass);\n StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);\n+ XlnxCSUDMAClass *xcdc = XLNX_CSU_DMA_CLASS(klass);\n \n dc->reset = xlnx_csu_dma_reset;\n dc->realize = xlnx_csu_dma_realize;\n@@ -704,6 +719,8 @@ static void xlnx_csu_dma_class_init(ObjectClass *klass, void *data)\n \n ssc->push = xlnx_csu_dma_stream_push;\n ssc->can_push = xlnx_csu_dma_stream_can_push;\n+\n+ xcdc->read = xlnx_csu_dma_class_read;\n }\n \n static void xlnx_csu_dma_init(Object *obj)\n", "prefixes": [ "PULL", "09/32" ] }