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GET /api/patches/1585750/?format=api
{ "id": 1585750, "url": "http://patchwork.ozlabs.org/api/patches/1585750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-7-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220128153009.2467560-7-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2022-01-28T15:29:43", "name": "[PULL,06/32] hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1a6543a66d83cf39b2d6735ed79c739cc8b9af6c", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-7-peter.maydell@linaro.org/mbox/", "series": [ { "id": 283405, "url": "http://patchwork.ozlabs.org/api/series/283405/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=283405", "date": "2022-01-28T15:29:53", "name": "[PULL,01/32] Update copyright dates to 2022", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/283405/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1585750/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1585750/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=TQLtQ/8y;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jlj2R5nGzz9t3b\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 29 Jan 2022 03:04:31 +1100 (AEDT)", "from localhost ([::1]:47432 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1nDTjh-0007cv-E4\n\tfor incoming@patchwork.ozlabs.org; Fri, 28 Jan 2022 11:04:29 -0500", "from eggs.gnu.org ([209.51.188.92]:57738)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1nDTDB-0002Ay-IS\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:30:58 -0500", "from [2a00:1450:4864:20::32a] (port=44986\n helo=mail-wm1-x32a.google.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1nDTD1-0006Ns-2P\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:30:47 -0500", "by mail-wm1-x32a.google.com with SMTP id\n l35-20020a05600c1d2300b0034d477271c1so4287411wms.3\n for <qemu-devel@nongnu.org>; Fri, 28 Jan 2022 07:30:23 -0800 (PST)", "from orth.archaic.org.uk (orth.archaic.org.uk. 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:references:mime-version:content-transfer-encoding;\n bh=FXZTXesqZyKuKDZawiHNQrJkdeY3IP9KlA8IiCeAN5M=;\n b=zawNRtAo6jTc2tVHzvs5C3SBrKTClSkm0iyNqvzHktoe4H311gqDnuvHLPQ4/ULaOc\n wEacHoB8yO3kpkVbLxx+y58cU+OqJFWnaLJKoL1hMguvS/A50zzzHtn75nJPO+SYuQ6c\n HLqzWLJiCXIbcOHWhNHX0io1yFCYxgwX+n7zDt5fGt7gVrzBSfLodRKkf9Hy8FsWKqS5\n xMyzoEj2A3cKDnKDFZpNMkClzyEwQsNUJ7nxqZr/sBl2frjARtVDfi7W9KKKKhspYK1i\n erW6eNQbdY92dqRpIDsIRtXibGTizQcuS8juQIQbFGF5lZPlp6Mb2TryTVS8T2UvBbPh\n virg==", "X-Gm-Message-State": "AOAM533ipMLpMDe73fuU5n409zkMPfiQVk5B3mXOMCYArOQcsMZp3qUH\n 9Kt3OhGnv0z4UR4crFEc11tmN81uGtap+Q==", "X-Google-Smtp-Source": "\n ABdhPJyw4SASwy62lwKo3gBMp/0NHGSvP+gVqgHgnmHi4tY+uJ/gfLTHVvpumfNgW+igsfimmYR+aA==", "X-Received": "by 2002:a7b:c40a:: with SMTP id k10mr7816692wmi.179.1643383822626;\n Fri, 28 Jan 2022 07:30:22 -0800 (PST)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PULL 06/32] hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM\n and RTC models", "Date": "Fri, 28 Jan 2022 15:29:43 +0000", "Message-Id": "<20220128153009.2467560-7-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220128153009.2467560-1-peter.maydell@linaro.org>", "References": "<20220128153009.2467560-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Host-Lookup-Failed": "Reverse DNS lookup failed for 2a00:1450:4864:20::32a\n (failed)", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32a;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com", "X-Spam_score_int": "-12", "X-Spam_score": "-1.3", "X-Spam_bar": "-", "X-Spam_report": "(-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Francisco Iglesias <francisco.iglesias@xilinx.com>\n\nAdd an orgate and 'or' the interrupts from the BBRAM and RTC models.\n\nSigned-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Luc Michel <luc@lmichel.fr>\nMessage-id: 20220121161141.14389-3-francisco.iglesias@xilinx.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n include/hw/arm/xlnx-versal.h | 5 +++--\n hw/arm/xlnx-versal-virt.c | 2 +-\n hw/arm/xlnx-versal.c | 28 ++++++++++++++++++++++++++--\n 3 files changed, 30 insertions(+), 5 deletions(-)", "diff": "diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h\nindex 895ba12c61e..62fb6f0a688 100644\n--- a/include/hw/arm/xlnx-versal.h\n+++ b/include/hw/arm/xlnx-versal.h\n@@ -85,6 +85,8 @@ struct Versal {\n XlnxEFuse efuse;\n XlnxVersalEFuseCtrl efuse_ctrl;\n XlnxVersalEFuseCache efuse_cache;\n+\n+ qemu_or_irq apb_irq_orgate;\n } pmc;\n \n struct {\n@@ -111,8 +113,7 @@ struct Versal {\n #define VERSAL_GEM1_WAKE_IRQ_0 59\n #define VERSAL_ADMA_IRQ_0 60\n #define VERSAL_XRAM_IRQ_0 79\n-#define VERSAL_BBRAM_APB_IRQ_0 121\n-#define VERSAL_RTC_APB_ERR_IRQ 121\n+#define VERSAL_PMC_APB_IRQ 121\n #define VERSAL_SD0_IRQ_0 126\n #define VERSAL_EFUSE_IRQ 139\n #define VERSAL_RTC_ALARM_IRQ 142\ndiff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c\nindex 0c5edc898e1..8ea9979710f 100644\n--- a/hw/arm/xlnx-versal-virt.c\n+++ b/hw/arm/xlnx-versal-virt.c\n@@ -365,7 +365,7 @@ static void fdt_add_bbram_node(VersalVirt *s)\n qemu_fdt_add_subnode(s->fdt, name);\n \n qemu_fdt_setprop_cells(s->fdt, name, \"interrupts\",\n- GIC_FDT_IRQ_TYPE_SPI, VERSAL_BBRAM_APB_IRQ_0,\n+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_PMC_APB_IRQ,\n GIC_FDT_IRQ_FLAGS_LEVEL_HI);\n qemu_fdt_setprop(s->fdt, name, \"interrupt-names\",\n interrupt_names, sizeof(interrupt_names));\ndiff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c\nindex b2705b6925e..fefd00b57c5 100644\n--- a/hw/arm/xlnx-versal.c\n+++ b/hw/arm/xlnx-versal.c\n@@ -25,6 +25,8 @@\n #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME(\"cortex-a72\")\n #define GEM_REVISION 0x40070106\n \n+#define VERSAL_NUM_PMC_APB_IRQS 2\n+\n static void versal_create_apu_cpus(Versal *s)\n {\n int i;\n@@ -260,6 +262,25 @@ static void versal_create_sds(Versal *s, qemu_irq *pic)\n }\n }\n \n+static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic)\n+{\n+ DeviceState *orgate;\n+\n+ /*\n+ * The VERSAL_PMC_APB_IRQ is an 'or' of the interrupts from the following\n+ * models:\n+ * - RTC\n+ * - BBRAM\n+ */\n+ object_initialize_child(OBJECT(s), \"pmc-apb-irq-orgate\",\n+ &s->pmc.apb_irq_orgate, TYPE_OR_IRQ);\n+ orgate = DEVICE(&s->pmc.apb_irq_orgate);\n+ object_property_set_int(OBJECT(orgate),\n+ \"num-lines\", VERSAL_NUM_PMC_APB_IRQS, &error_fatal);\n+ qdev_realize(orgate, NULL, &error_fatal);\n+ qdev_connect_gpio_out(orgate, 0, pic[VERSAL_PMC_APB_IRQ]);\n+}\n+\n static void versal_create_rtc(Versal *s, qemu_irq *pic)\n {\n SysBusDevice *sbd;\n@@ -277,7 +298,8 @@ static void versal_create_rtc(Versal *s, qemu_irq *pic)\n * TODO: Connect the ALARM and SECONDS interrupts once our RTC model\n * supports them.\n */\n- sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);\n+ sysbus_connect_irq(sbd, 1,\n+ qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0));\n }\n \n static void versal_create_xrams(Versal *s, qemu_irq *pic)\n@@ -328,7 +350,8 @@ static void versal_create_bbram(Versal *s, qemu_irq *pic)\n sysbus_realize(sbd, &error_fatal);\n memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL,\n sysbus_mmio_get_region(sbd, 0));\n- sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);\n+ sysbus_connect_irq(sbd, 0,\n+ qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 1));\n }\n \n static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base)\n@@ -455,6 +478,7 @@ static void versal_realize(DeviceState *dev, Error **errp)\n versal_create_gems(s, pic);\n versal_create_admas(s, pic);\n versal_create_sds(s, pic);\n+ versal_create_pmc_apb_irq_orgate(s, pic);\n versal_create_rtc(s, pic);\n versal_create_xrams(s, pic);\n versal_create_bbram(s, pic);\n", "prefixes": [ "PULL", "06/32" ] }