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GET /api/patches/1585734/?format=api
{ "id": 1585734, "url": "http://patchwork.ozlabs.org/api/patches/1585734/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-26-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220128153009.2467560-26-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2022-01-28T15:30:02", "name": "[PULL,25/32] hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8b79f4adaa5447fca928905b78d480174aa41782", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-26-peter.maydell@linaro.org/mbox/", "series": [ { "id": 283405, "url": "http://patchwork.ozlabs.org/api/series/283405/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=283405", "date": "2022-01-28T15:29:53", "name": "[PULL,01/32] Update copyright dates to 2022", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/283405/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1585734/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1585734/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=UKwb3Ljm;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4JlhT92pj1z9t56\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 29 Jan 2022 02:39:09 +1100 (AEDT)", "from localhost ([::1]:41066 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1nDTL7-00006O-3S\n\tfor incoming@patchwork.ozlabs.org; Fri, 28 Jan 2022 10:39:06 -0500", "from eggs.gnu.org ([209.51.188.92]:57642)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1nDTD5-0002Ab-OP\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:30:52 -0500", "from [2a00:1450:4864:20::42e] (port=33707\n helo=mail-wr1-x42e.google.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1nDTCz-0006Qb-Kf\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:30:44 -0500", "by mail-wr1-x42e.google.com with SMTP id e8so11670425wrc.0\n for <qemu-devel@nongnu.org>; Fri, 28 Jan 2022 07:30:39 -0800 (PST)", "from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2])\n by smtp.gmail.com with ESMTPSA id j3sm4749485wrb.57.2022.01.28.07.30.37\n for <qemu-devel@nongnu.org>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 28 Jan 2022 07:30:37 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n h=from:to:subject:date:message-id:in-reply-to:references:mime-version\n :content-transfer-encoding;\n bh=O5lPl9HHeRUVqRwf9Wefbbxm14diARdL3uA5T3Sfq8w=;\n b=UKwb3Ljm+gTCUJ9tSQRgOLY83/6Xb+gsMsU5adLszouQnfejMytpJEl4nc0vYLO1no\n q7dBiHgCpoMxmyhjWMAXiahDQeW6wm1k4uH8E2OY0C16RDi6EJOjQqfyKWSTTHeRessN\n 5nBpxaEOfAge239gNn6ZIff61G72uQ7sWrSaT46Yeu0AVR41QJUi+uwmRB3ma9N5Ognm\n tSCRhESR929gVFj4I05LdPG1FLGVEDfQRxdU+SWBwgYT4g4djE6ZdzP1LrwtedvTgMTM\n GiX4hfvZ/q9doZvpzBRPCanQ8GMEEQ2GoYROuxJFtlWPoHZNkldkikskLwEtoa87+azT\n Zc/A==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20210112;\n h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=O5lPl9HHeRUVqRwf9Wefbbxm14diARdL3uA5T3Sfq8w=;\n b=ZIqH/ewQXdXWhQx6BnZBrhyEyDKhWfQdpIs90VMIHV83cxrtT5UFZPOuvevmTQqBf8\n kNzbYEuhPc8pivTaiODAvMl3Mxrf+VmyO/2v15FeC/vR0lwjr1uFdut49A8dDi6LZ6A1\n Bu9gmHpZuk0xq0zx9tAlbTK7E7eXU8X+KhO2uD+ehpIwDxDjpo1Id1ygbSsTLp4ueq7q\n 7Eg7VUM8MnvKznJ+PD+6Ebid0jDAg5olRXnqzEhi0C1pMzPbTeE7LMy/X7uVBsfDS93j\n SwRCa+zbIRg9gZZ5neJdPDYoTAXdUuPI/A1yUIZKdYrUKVGK9+JZQRbHLpG9bfLVRoqR\n +6sQ==", "X-Gm-Message-State": "AOAM532P3vTOpu+G/ZQfk2TryYJv3LhYWxfIWWgqCB/xAk0sutHeopUE\n x4+clZuoA4lnLDmHicr/PQgEsq+m9NC8Pg==", "X-Google-Smtp-Source": "\n ABdhPJx+ftAxw2Y3Yw0yQ8BLQSTRsgGjfKsNwHghyuVVcmEiwNvLk99A5SBoGWDkLiqbMYqbmpdP8w==", "X-Received": "by 2002:a5d:4709:: with SMTP id y9mr7534164wrq.613.1643383838113;\n Fri, 28 Jan 2022 07:30:38 -0800 (PST)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PULL 25/32] hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are\n supported", "Date": "Fri, 28 Jan 2022 15:30:02 +0000", "Message-Id": "<20220128153009.2467560-26-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220128153009.2467560-1-peter.maydell@linaro.org>", "References": "<20220128153009.2467560-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Host-Lookup-Failed": "Reverse DNS lookup failed for 2a00:1450:4864:20::42e\n (failed)", "Received-SPF": "pass client-ip=2a00:1450:4864:20::42e;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com", "X-Spam_score_int": "-12", "X-Spam_score": "-1.3", "X-Spam_bar": "-", "X-Spam_report": "(-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "The GICR_CTLR.CES bit is a read-only bit which is set to 1 to indicate\nthat the GICR_CTLR.EnableLPIs bit can be written to 0 to disable\nLPIs (as opposed to allowing LPIs to be enabled but not subsequently\ndisabled). Our implementation permits this, so advertise it\nby setting CES to 1.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-id: 20220122182444.724087-10-peter.maydell@linaro.org\n---\n hw/intc/gicv3_internal.h | 1 +\n hw/intc/arm_gicv3_common.c | 4 ++++\n 2 files changed, 5 insertions(+)", "diff": "diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h\nindex 5394266aaf4..a316f6c58a5 100644\n--- a/hw/intc/gicv3_internal.h\n+++ b/hw/intc/gicv3_internal.h\n@@ -110,6 +110,7 @@\n #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)\n \n #define GICR_CTLR_ENABLE_LPIS (1U << 0)\n+#define GICR_CTLR_CES (1U << 1)\n #define GICR_CTLR_RWP (1U << 3)\n #define GICR_CTLR_DPG0 (1U << 24)\n #define GICR_CTLR_DPG1NS (1U << 25)\ndiff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c\nindex 579aa0cb9ed..4ca5ae9bc56 100644\n--- a/hw/intc/arm_gicv3_common.c\n+++ b/hw/intc/arm_gicv3_common.c\n@@ -429,6 +429,10 @@ static void arm_gicv3_common_reset(DeviceState *dev)\n \n cs->level = 0;\n cs->gicr_ctlr = 0;\n+ if (s->lpi_enable) {\n+ /* Our implementation supports clearing GICR_CTLR.EnableLPIs */\n+ cs->gicr_ctlr |= GICR_CTLR_CES;\n+ }\n cs->gicr_statusr[GICV3_S] = 0;\n cs->gicr_statusr[GICV3_NS] = 0;\n cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;\n", "prefixes": [ "PULL", "25/32" ] }