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GET /api/patches/1561977/?format=api
{ "id": 1561977, "url": "http://patchwork.ozlabs.org/api/patches/1561977/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20211130180110.2217042-1-aaelhaj@google.com/", "project": { "id": 57, "url": "http://patchwork.ozlabs.org/api/projects/57/?format=api", "name": "Linux ASPEED SoC development", "link_name": "linux-aspeed", "list_id": "linux-aspeed.lists.ozlabs.org", "list_email": "linux-aspeed@lists.ozlabs.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20211130180110.2217042-1-aaelhaj@google.com>", "list_archive_url": null, "date": "2021-11-30T18:01:10", "name": "ARM: dts: aspeed: Add TYAN S8036 BMC machine", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2fcad9f5679400f0f90f003795ffa63dbbebb734", "submitter": { "id": 82990, "url": "http://patchwork.ozlabs.org/api/people/82990/?format=api", "name": "Ali El-Haj-Mahmoud", "email": "aaelhaj@google.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20211130180110.2217042-1-aaelhaj@google.com/mbox/", "series": [ { "id": 274536, "url": "http://patchwork.ozlabs.org/api/series/274536/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=274536", "date": "2021-11-30T18:01:10", "name": "ARM: dts: aspeed: Add TYAN S8036 BMC machine", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/274536/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1561977/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1561977/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256\n header.s=20210112 header.b=U2yNKGWE;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; 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charset=\"UTF-8\"", "X-Mailman-Approved-At": "Wed, 01 Dec 2021 11:13:59 +1100", "X-BeenThere": "linux-aspeed@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux ASPEED SoC development <linux-aspeed.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linux-aspeed>,\n <mailto:linux-aspeed-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linux-aspeed/>", "List-Post": "<mailto:linux-aspeed@lists.ozlabs.org>", "List-Help": "<mailto:linux-aspeed-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linux-aspeed>,\n <mailto:linux-aspeed-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Rob Herring <robh+dt@kernel.org>, Ali El-Haj-Mahmoud <aaelhaj@google.com>,\n Oskar Sneft <osk@google.com>", "Errors-To": "linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Linux-aspeed\"\n <linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "The TYAN S8036 is a server platform with an ASPEED AST2500 BMC.\n\nSigned-off-by: Ali El-Haj-Mahmoud <aaelhaj@google.com>\n---\n arch/arm/boot/dts/Makefile | 3 +-\n arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts | 466 ++++++++++++++++++++\n 2 files changed, 468 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts", "diff": "diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile\nindex 8b7f150be39e..b0ca5e88942b 100644\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -1499,4 +1499,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \\\n \taspeed-bmc-quanta-q71l.dtb \\\n \taspeed-bmc-supermicro-x11spi.dtb \\\n \taspeed-bmc-inventec-transformers.dtb \\\n-\taspeed-bmc-tyan-s7106.dtb\n+\taspeed-bmc-tyan-s7106.dtb \\\n+\taspeed-bmc-tyan-s8036.dtb\ndiff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts\nnew file mode 100644\nindex 000000000000..873e7bf2361e\n--- /dev/null\n+++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts\n@@ -0,0 +1,466 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/dts-v1/;\n+\n+#include \"aspeed-g5.dtsi\"\n+#include <dt-bindings/gpio/aspeed-gpio.h>\n+#include <dt-bindings/interrupt-controller/irq.h>\n+\n+/ {\n+\tmodel = \"Tyan S8036 BMC\";\n+\tcompatible = \"tyan,s8036-bmc\", \"aspeed,ast2500\";\n+\n+\tchosen {\n+\t\tstdout-path = &uart5;\n+\t\tbootargs = \"console=ttyS4,115200 earlycon\";\n+\t};\n+\n+\tmemory@80000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x80000000 0x20000000>;\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges;\n+\n+\t\tp2a_memory: region@987f0000 {\n+\t\t\tno-map;\n+\t\t\treg = <0x987f0000 0x00010000>; /* 64KB */\n+\t\t};\n+\n+\t\tvga_memory: framebuffer@9f000000 {\n+\t\t\tno-map;\n+\t\t\treg = <0x9f000000 0x01000000>; /* 16M */\n+\t\t};\n+\n+\t\tgfx_memory: framebuffer {\n+\t\t\tsize = <0x01000000>; /* 16M */\n+\t\t\talignment = <0x01000000>;\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\treusable;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tidentify {\n+\t\t\tgpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\theartbeat {\n+\t\t\tgpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tiio-hwmon {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,\n+\t\t\t<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,\n+\t\t\t<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,\n+\t\t\t<&adc 12>, <&adc 13>, <&adc 14>;\n+\t};\n+\n+\tiio-hwmon-battery {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 15>;\n+\t};\n+};\n+\n+&fmc {\n+\tstatus = \"okay\";\n+\tflash@0 {\n+\t\tlabel = \"bmc\";\n+\t\tstatus = \"okay\";\n+\t\tm25p,fast-read;\n+#include \"openbmc-flash-layout.dtsi\"\n+\t};\n+};\n+\n+&spi1 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_spi1_default>;\n+\n+\tflash@0 {\n+\t\tstatus = \"okay\";\n+\t\tlabel = \"pnor\";\n+\t\tm25p,fast-read;\n+\t};\n+};\n+\n+&uart1 {\n+\t/* Rear RS-232 connector */\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_txd1_default\n+\t\t\t&pinctrl_rxd1_default>;\n+};\n+\n+&uart2 {\n+\t/* RS-232 connector on header */\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_txd2_default\n+\t\t\t&pinctrl_rxd2_default>;\n+};\n+\n+&uart3 {\n+\t/* Alternative to vuart to internally connect (route) to uart1\n+\t * when vuart cannot be used due to BIOS limitations.\n+\t */\n+\tstatus = \"okay\";\n+};\n+\n+&uart4 {\n+\t/* Alternative to vuart to internally connect (route) to the\n+\t * external port usually used by uart1 when vuart cannot be\n+\t * used due to BIOS limitations.\n+\t */\n+\tstatus = \"okay\";\n+};\n+\n+&uart5 {\n+\t/* BMC \"debug\" (console) UART; connected to RS-232 connector\n+\t * on header; selectable via jumpers as alternative to uart2\n+\t */\n+\tstatus = \"okay\";\n+};\n+\n+&uart_routing {\n+\tstatus = \"okay\";\n+};\n+\n+&vuart {\n+\tstatus = \"okay\";\n+\n+\t/* We enable the VUART here, but leave it in a state that does\n+\t * not interfere with the SuperIO. The goal is to have both the\n+\t * VUART and the SuperIO available and decide at runtime whether\n+\t * the VUART should actually be used. For that reason, configure\n+\t * an \"invalid\" IO address and an IRQ that is not used by the\n+\t * BMC.\n+\t */\n+\taspeed,lpc-io-reg = <0xffff>;\n+\taspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;\n+};\n+\n+&lpc_ctrl {\n+\tstatus = \"okay\";\n+};\n+\n+&p2a {\n+\tstatus = \"okay\";\n+\tmemory-region = <&p2a_memory>;\n+};\n+\n+&lpc_snoop {\n+\tstatus = \"okay\";\n+\tsnoop-ports = <0x80>;\n+};\n+\n+&adc {\n+\tstatus = \"okay\";\n+};\n+\n+&vhub {\n+\tstatus = \"okay\";\n+};\n+\n+&pwm_tacho {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_pwm0_default\n+\t\t\t&pinctrl_pwm1_default\n+\t\t\t&pinctrl_pwm3_default\n+\t\t\t&pinctrl_pwm4_default>;\n+\n+\t/* CPU fan */\n+\tfan@0 {\n+\t\treg = <0x00>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x00>;\n+\t};\n+\n+\t/* PWM group for chassis fans #1, #2, #3 and #4 */\n+\tfan@2 {\n+\t\treg = <0x03>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x02>;\n+\t};\n+\n+\tfan@3 {\n+\t\treg = <0x03>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x03>;\n+\t};\n+\n+\tfan@4 {\n+\t\treg = <0x03>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x04>;\n+\t};\n+\n+\tfan@5 {\n+\t\treg = <0x03>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x05>;\n+\t};\n+\n+\t/* PWM group for chassis fans #5 and #6 */\n+\tfan@6 {\n+\t\treg = <0x04>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x06>;\n+\t};\n+\n+\tfan@7 {\n+\t\treg = <0x04>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x07>;\n+\t};\n+};\n+\n+&i2c0 {\n+\t/* Directly connected to Sideband-Temperature Sensor Interface (APML) */\n+\tstatus = \"okay\";\n+};\n+\n+&i2c1 {\n+\t/* Directly connected to IPMB HDR. */\n+\tstatus = \"okay\";\n+};\n+\n+&i2c2 {\n+\tstatus = \"okay\";\n+\n+\t/* BMC EEPROM, incl. mainboard FRU */\n+\teeprom@50 {\n+\t\tcompatible = \"atmel,24c256\";\n+\t\treg = <0x50>;\n+\t};\n+\t/* Also connected to:\n+\t * - BCM5720\n+\t * - FPGA\n+\t * - FAN HDR\n+\t * - FPIO HDR\n+\t */\n+};\n+\n+&i2c3 {\n+\tstatus = \"okay\";\n+\n+\t/* PSU1 FRU @ 0xA0 */\n+\teeprom@50 {\n+\t\tcompatible = \"atmel,24c02\";\n+\t\treg = <0x50>;\n+\t};\n+\n+\t/* PSU2 FRU @ 0xA2 */\n+\teeprom@51 {\n+\t\tcompatible = \"atmel,24c02\";\n+\t\treg = <0x51>;\n+\t};\n+\n+\t/* PSU1 @ 0xB0 */\n+\tpower-supply@58 {\n+\t\tcompatible = \"pmbus\";\n+\t\treg = <0x58>;\n+\t};\n+\n+\t/* PSU2 @ 0xB2 */\n+\tpower-supply@59 {\n+\t\tcompatible = \"pmbus\";\n+\t\treg = <0x59>;\n+\t};\n+\n+};\n+\n+&i2c4 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c5 {\n+\tstatus = \"okay\";\n+\t/* Hardware monitor with temperature sensors */\n+\tnct7802@28 {\n+\t\tcompatible = \"nuvoton,nct7802\";\n+\t\treg = <0x28>;\n+\t\tchannel@0 { /* LTD */\n+\t\t\treg = <0>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t\tchannel@1 { /* RTD1 */\n+\t\t\treg = <1>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tsensor-type = \"temperature\";\n+\t\t\ttemperature-mode = \"thermistor\";\n+\t\t};\n+\n+\t\tchannel@2 { /* RTD2 */\n+\t\t\treg = <2>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tsensor-type = \"temperature\";\n+\t\t\ttemperature-mode = \"thermistor\";\n+\t\t};\n+\n+\t\tchannel@3 { /* RTD3 */\n+\t\t\treg = <3>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tsensor-type = \"temperature\";\n+\t\t};\n+\t};\n+\n+\t/* Also connected to:\n+\t * - PCA9544\n+\t * - CLK BUFF\n+\t * - OCP FRU\n+\t */\n+};\n+\n+&i2c6 {\n+\tstatus = \"okay\";\n+\t/* Connected to:\n+\t * - PCA9548 @0xE0\n+\t * - PCA9548 @0xE2\n+\t * - PCA9544 @0xE4\n+\t */\n+};\n+\n+&i2c7 {\n+\tstatus = \"okay\";\n+\n+\t/* Connected to:\n+\t * - PCH SMBUS #4\n+\t */\n+};\n+\n+&i2c8 {\n+\tstatus = \"okay\";\n+\n+\t/* Not connected */\n+};\n+\n+&mac0 {\n+\tstatus = \"okay\";\n+\tuse-ncsi;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_rmii1_default>;\n+};\n+\n+&mac1 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;\n+};\n+\n+&ibt {\n+\tstatus = \"okay\";\n+};\n+\n+&kcs1 {\n+\tstatus = \"okay\";\n+\taspeed,lpc-io-reg = <0xca8>;\n+};\n+\n+&kcs3 {\n+\tstatus = \"okay\";\n+\taspeed,lpc-io-reg = <0xca2>;\n+};\n+\n+/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */\n+&gfx {\n+\tstatus = \"okay\";\n+\tmemory-region = <&gfx_memory>;\n+};\n+\n+/* We're following the GPIO naming as defined at\n+ * https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md.\n+ *\n+ * Notes on led-identify and id-button:\n+ * - A physical button is connected to id-button which\n+ * triggers the clock on a D flip-flop. The /Q output of the\n+ * flip-flop drives its D input.\n+ * - The flip-flop's Q output drives led-identify which is\n+ * connected to LEDs.\n+ * - With that, every button press toggles the LED between on and off.\n+ *\n+ * Notes on power-, reset- and nmi- button and control:\n+ * - The -button signals can be used to monitor physical buttons.\n+ * - The -control signals can be used to actuate the specific\n+ * operation.\n+ * - In hardware, the -button signals are connected to the -control\n+ * signals through drivers with the -control signals being\n+ * protected through diodes.\n+ */\n+&gpio {\n+\tstatus = \"okay\";\n+\tgpio-line-names =\n+\t/*A0*/\t\t\"\",\n+\t/*A1*/\t\t\"\",\n+\t/*A2*/\t\t\"led-identify\", /* in/out: BMC_CHASSIS_ID_LED_L */\n+\t/*A3*/\t\t\"\",\n+\t/*A4*/\t\t\"\",\n+\t/*A5*/\t\t\"\",\n+\t/*A6*/\t\t\"\",\n+\t/*A7*/\t\t\"\",\n+\t/*B0-B7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*C0-C7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*D0*/\t\t\"\",\n+\t/*D1*/\t\t\"\",\n+\t/*D2*/\t\t\"power-chassis-good\", /* in: PWR_GOOD_LED -- Check if this is Z3?*/\n+\t/*D3*/\t\t\"platform-reset\", /* in: RESET_LED_L */\n+\t/*D4*/\t\t\"\",\n+\t/*D5*/\t\t\"\",\n+\t/*D6*/\t\t\"\",\n+\t/*D7*/\t\t\"\",\n+\t/*E0*/\t\t\"power-button\", /* in: BMC_SYS_MON_PWR_BTN_L */\n+\t/*E1*/\t\t\"power-chassis-control\", /* out: BMC_ASSERT_PWR_BTN */\n+\t/*E2*/\t\t\"reset-button\", /* in: BMC_SYS_MOS_RST_BTN_L*/\n+\t/*E3*/\t\t\"reset-control\", /* out: BMC_ASSERT_RST_BTN */\n+\t/*E4*/\t\t\"nmi-button\", /* in: BMC_SYS_MON_NMI_BTN_L */\n+\t/*E5*/\t\t\"nmi-control\", /* out: BMC_ASSERT_NMI_BTN */\n+\t/*E6*/\t\t\"TSI_RESERT\",\n+\t/*E7*/\t\t\"led-heartbeat\", /* out: BMC_GPIOE7 */\n+\t/*F0*/\t\t\"\",\n+\t/*F1*/\t\t\"clear-cmos-control\", /* out: BMC_ASSERT_CLR_CMOS_L */\n+\t/*F2*/\t\t\"\",\n+\t/*F3*/\t\t\"\",\n+\t/*F4*/\t\t\"led-fault\", /* out: BMC_HWM_FAULT_LED_L */\n+\t/*F5*/\t\t\"BMC_SYS_FAULT_LED_L\",\n+\t/*F6*/\t\t\"BMC_ASSERT_BIOS_WP_L\",\n+\t/*F7*/\t\t\"\",\n+\t/*G0-G7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*H0-H7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*I0-I7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*J0-J7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*K0-K7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*L0-L7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*M0-M7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*N0-N7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*O0-O7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*P0-P7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*Q0*/\t\t\"\",\n+\t/*Q1*/\t\t\"\",\n+\t/*Q2*/\t\t\"\",\n+\t/*Q3*/\t\t\"\",\n+\t/*Q4*/\t\t\"\",\n+\t/*Q5*/\t\t\"\",\n+\t/*Q6*/\t\t\"id-button\", /* in: BMC_CHASSIS_ID_BTN_L */\n+\t/*Q7*/\t\t\"\",\n+\t/*R0-R7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*S0-S7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*T0-T7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*U0-U7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*V0-V7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*W0-W7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*X0-X7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*Y0-Y7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\",\"\",\n+\t/*Z0-Z2*/\t\"\",\"\",\"\",\n+\t/*Z3*/\t\t\"post-complete\", /* BMC_SYS_MON_PWROK */\n+\t/*Z4-Z7*/\t\"\",\"\",\"\",\"\",\n+\t/*AA0*/\t\t\"\",\n+\t/*AA1*/\t\t\"\",\n+\t/*AA2*/\t\t\"\",\n+\t/*AA3*/\t\t\"\",\n+\t/*AA4*/\t\t\"\",\n+\t/*AA5*/\t\t\"\",\n+\t/*AA6*/\t\t\"\",\n+\t/*AA7*/\t\t\"BMC_ASSERT_BMC_READY\",\n+\t/*AB0*/\t\t\"BMC_SPD_SEL\",\n+\t/*AB1-AB7*/\t\"\",\"\",\"\",\"\",\"\",\"\",\"\";\n+};\n", "prefixes": [] }