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GET /api/patches/1523775/?format=api
{ "id": 1523775, "url": "http://patchwork.ozlabs.org/api/patches/1523775/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-15-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210902130928.528803-15-clg@kaod.org>", "list_archive_url": null, "date": "2021-09-02T13:09:22", "name": "[v2,14/20] ppc/pnv: Add support for PHB5 \"Address-based trigger\" mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fe1da64a48122802b2d52ba30ce8123fe7f96c71", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-15-clg@kaod.org/mbox/", "series": [ { "id": 260743, "url": "http://patchwork.ozlabs.org/api/series/260743/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=260743", "date": "2021-09-02T13:09:11", "name": "ppc/pnv: Extend the powernv10 machine", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/260743/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1523775/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1523775/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "garm.ovh; auth=pass\n (GARM-101G00496daaba9-c6ab-4a9f-9831-8c0b8bf64dd7,\n 0F69C8711EE098B745CC44F7BEC1CAFBB1DDDEDC) smtp.auth=clg@kaod.org" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4H0hqx6kFGz9t6g\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 2 Sep 2021 23:39:57 +1000 (AEST)", "from localhost ([::1]:51934 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1mLmwd-0004Ud-Ou\n\tfor incoming@patchwork.ozlabs.org; Thu, 02 Sep 2021 09:39:55 -0400", "from eggs.gnu.org ([2001:470:142:3::10]:42950)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTh-0006uV-Lg\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:10:01 -0400", "from 8.mo52.mail-out.ovh.net ([46.105.37.156]:40363)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTW-00029m-F0\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:10:01 -0400", "from mxplan5.mail.ovh.net (unknown [10.109.156.48])\n by mo52.mail-out.ovh.net (Postfix) with ESMTPS id 96323295EB4;\n Thu, 2 Sep 2021 15:09:38 +0200 (CEST)", "from kaod.org (37.59.142.101) by DAG4EX1.mxp5.local (172.16.2.31)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Thu, 2 Sep\n 2021 15:09:36 +0200" ], "X-OVh-ClientIp": "82.64.250.170", "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>", "Subject": "[PATCH v2 14/20] ppc/pnv: Add support for PHB5 \"Address-based\n trigger\" mode", "Date": "Thu, 2 Sep 2021 15:09:22 +0200", "Message-ID": "<20210902130928.528803-15-clg@kaod.org>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20210902130928.528803-1-clg@kaod.org>", "References": "<20210902130928.528803-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[37.59.142.101]", "X-ClientProxiedBy": "DAG5EX1.mxp5.local (172.16.2.41) To DAG4EX1.mxp5.local\n (172.16.2.31)", "X-Ovh-Tracer-GUID": "b841be7a-9120-4833-86eb-d0090c21b93e", "X-Ovh-Tracer-Id": "14776310380422532003", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "\n gggruggvucftvghtrhhoucdtuddrgedvtddruddvhedgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrddutddunecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopegtlhhgsehkrghougdrohhrgh", "Received-SPF": "pass client-ip=46.105.37.156; envelope-from=clg@kaod.org;\n helo=8.mo52.mail-out.ovh.net", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?=\n\t=?utf-8?q?ter?= <clg@kaod.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "When the Address-Based Interrupt Trigger mode is activated, the PHB\nmaps the interrupt source number into the interrupt command address.\nThe PHB directly triggers the IC ESB page of the interrupt number and\nnot the notify page of the IC anymore.\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n include/hw/pci-host/pnv_phb4_regs.h | 2 +\n hw/pci-host/pnv_phb4.c | 73 ++++++++++++++++++++++++++---\n hw/pci-host/trace-events | 2 +\n 3 files changed, 71 insertions(+), 6 deletions(-)", "diff": "diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h\nindex 64f326b7158e..4a0d3b28efb3 100644\n--- a/include/hw/pci-host/pnv_phb4_regs.h\n+++ b/include/hw/pci-host/pnv_phb4_regs.h\n@@ -220,12 +220,14 @@\n #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16, 63)\n #define PHB_ETU_ERR_SUMMARY 0x2c8\n #define PHB_INT_NOTIFY_ADDR 0x300\n+#define PHB_INT_NOTIFY_ADDR_64K PPC_BIT(1) /* P10 */\n #define PHB_INT_NOTIFY_INDEX 0x308\n \n /* Fundamental register set B */\n #define PHB_VERSION 0x800\n #define PHB_CTRLR 0x810\n #define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* P10 */\n+#define PHB_CTRLR_IRQ_ABT_MODE PPC_BIT(10) /* P10 */\n #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11)\n #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12)\n #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13)\ndiff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c\nindex cf506d1623c3..353ce6617743 100644\n--- a/hw/pci-host/pnv_phb4.c\n+++ b/hw/pci-host/pnv_phb4.c\n@@ -1259,10 +1259,54 @@ static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge,\n return phb->bus_path;\n }\n \n-static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,\n- bool pq_checked)\n+/*\n+ * Address base trigger mode (POWER10)\n+ *\n+ * Trigger directly the IC ESB page\n+ */\n+static void pnv_phb4_xive_notify_abt(PnvPHB4 *phb, uint32_t srcno,\n+ bool pq_checked)\n+{\n+ uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3];\n+ uint64_t data = 0; /* trigger data : don't care */\n+ hwaddr addr;\n+ MemTxResult result;\n+ int esb_shift;\n+\n+ if (notif_port & PHB_INT_NOTIFY_ADDR_64K) {\n+ esb_shift = 16;\n+ } else {\n+ esb_shift = 12;\n+ }\n+\n+ /* Compute the address of the IC ESB management page */\n+ addr = (notif_port & ~PHB_INT_NOTIFY_ADDR_64K);\n+ addr |= (1ull << (esb_shift + 1)) * srcno;\n+ addr |= (1ull << esb_shift);\n+\n+ /*\n+ * When the PQ state bits are checked on the PHB, the associated\n+ * PQ state bits on the IC should be ignored. Use the unconditional\n+ * trigger offset to inject a trigger on the IC. This is always\n+ * the case for LSIs\n+ */\n+ if (pq_checked) {\n+ addr |= XIVE_ESB_INJECT;\n+ }\n+\n+ trace_pnv_phb4_xive_notify_ic(addr, data);\n+\n+ address_space_stq_be(&address_space_memory, addr, data,\n+ MEMTXATTRS_UNSPECIFIED, &result);\n+ if (result != MEMTX_OK) {\n+ phb_error(phb, \"trigger failed @%\"HWADDR_PRIx \"\\n\", addr);\n+ return;\n+ }\n+}\n+\n+static void pnv_phb4_xive_notify_ic(PnvPHB4 *phb, uint32_t srcno,\n+ bool pq_checked)\n {\n- PnvPHB4 *phb = PNV_PHB4(xf);\n uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3];\n uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3];\n uint64_t data = offset | srcno;\n@@ -1272,7 +1316,7 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,\n data |= XIVE_TRIGGER_PQ;\n }\n \n- trace_pnv_phb4_xive_notify(notif_port, data);\n+ trace_pnv_phb4_xive_notify_ic(notif_port, data);\n \n address_space_stq_be(&address_space_memory, notif_port, data,\n MEMTXATTRS_UNSPECIFIED, &result);\n@@ -1282,6 +1326,18 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,\n }\n }\n \n+static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,\n+ bool pq_checked)\n+{\n+ PnvPHB4 *phb = PNV_PHB4(xf);\n+\n+ if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE) {\n+ pnv_phb4_xive_notify_abt(phb, srcno, pq_checked);\n+ } else {\n+ pnv_phb4_xive_notify_ic(phb, srcno, pq_checked);\n+ }\n+}\n+\n static Property pnv_phb4_properties[] = {\n DEFINE_PROP_UINT32(\"index\", PnvPHB4, phb_id, 0),\n DEFINE_PROP_UINT32(\"chip-id\", PnvPHB4, chip_id, 0),\n@@ -1442,10 +1498,15 @@ void pnv_phb4_update_regions(PnvPhb4PecStack *stack)\n \n void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon)\n {\n+ uint64_t notif_port =\n+ phb->regs[PHB_INT_NOTIFY_ADDR >> 3] & ~PHB_INT_NOTIFY_ADDR_64K;\n uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3];\n+ bool abt = !!(phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE);\n \n- monitor_printf(mon, \"PHB4[%x:%x] Source %08x .. %08x\\n\",\n+ monitor_printf(mon, \"PHB4[%x:%x] Source %08x .. %08x %s @%\"HWADDR_PRIx\"\\n\",\n phb->chip_id, phb->phb_id,\n- offset, offset + phb->xsrc.nr_irqs - 1);\n+ offset, offset + phb->xsrc.nr_irqs - 1,\n+ abt ? \"ABT\" : \"\",\n+ notif_port);\n xive_source_pic_print_info(&phb->xsrc, 0, mon);\n }\ndiff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events\nindex 630e9fcc5e77..6e5d8d335525 100644\n--- a/hw/pci-host/trace-events\n+++ b/hw/pci-host/trace-events\n@@ -32,3 +32,5 @@ unin_read(uint64_t addr, uint64_t value) \"addr=0x%\" PRIx64 \" val=0x%\"PRIx64\n \n # pnv_phb4.c\n pnv_phb4_xive_notify(uint64_t notif_port, uint64_t data) \"notif=@0x%\"PRIx64\" data=0x%\"PRIx64\n+pnv_phb4_xive_notify_ic(uint64_t addr, uint64_t data) \"addr=@0x%\"PRIx64\" data=0x%\"PRIx64\n+pnv_phb4_xive_notify_abt(uint64_t notif_port, uint64_t data) \"notif=@0x%\"PRIx64\" data=0x%\"PRIx64\n", "prefixes": [ "v2", "14/20" ] }