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GET /api/patches/1523773/?format=api
{ "id": 1523773, "url": "http://patchwork.ozlabs.org/api/patches/1523773/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-17-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210902130928.528803-17-clg@kaod.org>", "list_archive_url": null, "date": "2021-09-02T13:09:24", "name": "[v2,16/20] ppc/pnv: add XIVE Gen2 TIMA support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "30a5f8a1a1f152c5136771fcc03844d5663d5159", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-17-clg@kaod.org/mbox/", "series": [ { "id": 260743, "url": "http://patchwork.ozlabs.org/api/series/260743/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=260743", "date": "2021-09-02T13:09:11", "name": "ppc/pnv: Extend the powernv10 machine", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/260743/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1523773/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1523773/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "garm.ovh; auth=pass\n (GARM-101G004560219b9-078c-4ea5-989f-cffbf355e179,\n 0F69C8711EE098B745CC44F7BEC1CAFBB1DDDEDC) smtp.auth=clg@kaod.org" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4H0hp336m3z9sPf\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 2 Sep 2021 23:38:19 +1000 (AEST)", "from localhost ([::1]:47472 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1mLmv3-0001ON-8C\n\tfor incoming@patchwork.ozlabs.org; Thu, 02 Sep 2021 09:38:17 -0400", "from eggs.gnu.org ([2001:470:142:3::10]:42936)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTh-0006sE-4V\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:10:01 -0400", "from 8.mo52.mail-out.ovh.net ([46.105.37.156]:53446)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTW-00029o-EF\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:10:00 -0400", "from mxplan5.mail.ovh.net (unknown [10.109.156.48])\n by mo52.mail-out.ovh.net (Postfix) with ESMTPS id 05CD3295F0A;\n Thu, 2 Sep 2021 15:09:39 +0200 (CEST)", "from kaod.org (37.59.142.101) by DAG4EX1.mxp5.local (172.16.2.31)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Thu, 2 Sep\n 2021 15:09:37 +0200" ], "X-OVh-ClientIp": "82.64.250.170", "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>", "Subject": "[PATCH v2 16/20] ppc/pnv: add XIVE Gen2 TIMA support", "Date": "Thu, 2 Sep 2021 15:09:24 +0200", "Message-ID": "<20210902130928.528803-17-clg@kaod.org>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20210902130928.528803-1-clg@kaod.org>", "References": "<20210902130928.528803-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[37.59.142.101]", "X-ClientProxiedBy": "DAG5EX1.mxp5.local (172.16.2.41) To DAG4EX1.mxp5.local\n (172.16.2.31)", "X-Ovh-Tracer-GUID": "2683649d-1c95-4417-9303-79439adf58df", "X-Ovh-Tracer-Id": "14776591852960058275", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "\n gggruggvucftvghtrhhoucdtuddrgedvtddruddvhedgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrddutddunecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopegtlhhgsehkrghougdrohhrgh", "Received-SPF": "pass client-ip=46.105.37.156; envelope-from=clg@kaod.org;\n helo=8.mo52.mail-out.ovh.net", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?=\n\t=?utf-8?q?ter?= <clg@kaod.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Only the CAM line updates done by the hypervisor are specific to\nPOWER10. Instead of duplicating the TM ops table, we handle these\ncommands locally under the PowerNV XIVE2 model.\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n include/hw/ppc/xive2.h | 8 ++++\n hw/intc/pnv_xive2.c | 27 +++++++++++-\n hw/intc/xive2.c | 95 ++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 128 insertions(+), 2 deletions(-)", "diff": "diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h\nindex 9222b5b36979..cf6211a0ecb9 100644\n--- a/include/hw/ppc/xive2.h\n+++ b/include/hw/ppc/xive2.h\n@@ -87,5 +87,13 @@ typedef struct Xive2EndSource {\n Xive2Router *xrtr;\n } Xive2EndSource;\n \n+/*\n+ * XIVE2 Thread Interrupt Management Area (POWER10)\n+ */\n+\n+void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,\n+ uint64_t value, unsigned size);\n+uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,\n+ hwaddr offset, unsigned size);\n \n #endif /* PPC_XIVE2_H */\ndiff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c\nindex cb12cea14fc6..4a2649893232 100644\n--- a/hw/intc/pnv_xive2.c\n+++ b/hw/intc/pnv_xive2.c\n@@ -1610,15 +1610,32 @@ static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops = {\n * TIMA ops\n */\n \n+/*\n+ * Special TIMA offsets to handle accesses in a POWER10 way.\n+ *\n+ * Only the CAM line updates done by the hypervisor should be handled\n+ * specifically.\n+ */\n+#define HV_PAGE_OFFSET (XIVE_TM_HV_PAGE << TM_SHIFT)\n+#define HV_PUSH_OS_CTX_OFFSET (HV_PAGE_OFFSET | (TM_QW1_OS + TM_WORD2))\n+#define HV_PULL_OS_CTX_OFFSET (HV_PAGE_OFFSET | TM_SPC_PULL_OS_CTX)\n+\n static void pnv_xive2_tm_write(void *opaque, hwaddr offset,\n uint64_t value, unsigned size)\n {\n PowerPCCPU *cpu = POWERPC_CPU(current_cpu);\n PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);\n XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);\n+ XivePresenter *xptr = XIVE_PRESENTER(xive);\n+\n+ /* TODO: should we switch the TM ops table instead ? */\n+ if (offset == HV_PUSH_OS_CTX_OFFSET) {\n+ xive2_tm_push_os_ctx(xptr, tctx, offset, value, size);\n+ return;\n+ }\n \n /* Other TM ops are the same as XIVE1 */\n- xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size);\n+ xive_tctx_tm_write(xptr, tctx, offset, value, size);\n }\n \n static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size)\n@@ -1626,9 +1643,15 @@ static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size)\n PowerPCCPU *cpu = POWERPC_CPU(current_cpu);\n PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);\n XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);\n+ XivePresenter *xptr = XIVE_PRESENTER(xive);\n+\n+ /* TODO: should we switch the TM ops table instead ? */\n+ if (offset == HV_PULL_OS_CTX_OFFSET) {\n+ return xive2_tm_pull_os_ctx(xptr, tctx, offset, size);\n+ }\n \n /* Other TM ops are the same as XIVE1 */\n- return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size);\n+ return xive_tctx_tm_read(xptr, tctx, offset, size);\n }\n \n static const MemoryRegionOps pnv_xive2_tm_ops = {\ndiff --git a/hw/intc/xive2.c b/hw/intc/xive2.c\nindex 26af08a5de07..e31037e1f030 100644\n--- a/hw/intc/xive2.c\n+++ b/hw/intc/xive2.c\n@@ -158,6 +158,101 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t data)\n }\n end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex);\n }\n+\n+/*\n+ * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode\n+ */\n+\n+static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk,\n+ uint32_t *nvp_idx, bool *vo)\n+{\n+ *nvp_blk = xive2_nvp_blk(cam);\n+ *nvp_idx = xive2_nvp_idx(cam);\n+ *vo = !!(cam & TM2_QW1W2_VO);\n+}\n+\n+uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,\n+ hwaddr offset, unsigned size)\n+{\n+ uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);\n+ uint32_t qw1w2_new;\n+ uint32_t cam = be32_to_cpu(qw1w2);\n+ uint8_t nvp_blk;\n+ uint32_t nvp_idx;\n+ bool vo;\n+\n+ xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo);\n+\n+ if (!vo) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: pulling invalid NVP %x/%x !?\\n\",\n+ nvp_blk, nvp_idx);\n+ }\n+\n+ /* Invalidate CAM line */\n+ qw1w2_new = xive_set_field32(TM2_QW1W2_VO, qw1w2, 0);\n+ memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4);\n+\n+ return qw1w2;\n+}\n+\n+static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,\n+ uint8_t nvp_blk, uint32_t nvp_idx)\n+{\n+ Xive2Nvp nvp;\n+ uint8_t ipb;\n+ uint8_t cppr = 0;\n+\n+ /*\n+ * Grab the associated thread interrupt context registers in the\n+ * associated NVP\n+ */\n+ if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: No NVP %x/%x\\n\",\n+ nvp_blk, nvp_idx);\n+ return;\n+ }\n+\n+ if (!xive2_nvp_is_valid(&nvp)) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: invalid NVP %x/%x\\n\",\n+ nvp_blk, nvp_idx);\n+ return;\n+ }\n+\n+ ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2);\n+ if (ipb) {\n+ nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0);\n+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);\n+ }\n+\n+ /* An IPB or CPPR change can trigger a resend */\n+ if (ipb || cppr) {\n+ xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);\n+ }\n+}\n+\n+/*\n+ * Updating the OS CAM line can trigger a resend of interrupt\n+ */\n+void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,\n+ hwaddr offset, uint64_t value, unsigned size)\n+{\n+ uint32_t cam = value;\n+ uint32_t qw1w2 = cpu_to_be32(cam);\n+ uint8_t nvp_blk;\n+ uint32_t nvp_idx;\n+ bool vo;\n+\n+ xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo);\n+\n+ /* First update the thead context */\n+ memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);\n+\n+ /* Check the interrupt pending bits */\n+ if (vo) {\n+ xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx);\n+ }\n+}\n+\n /*\n * XIVE Router (aka. Virtualization Controller or IVRE)\n */\n", "prefixes": [ "v2", "16/20" ] }