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GET /api/patches/1523772/?format=api
{ "id": 1523772, "url": "http://patchwork.ozlabs.org/api/patches/1523772/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-5-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210902130928.528803-5-clg@kaod.org>", "list_archive_url": null, "date": "2021-09-02T13:09:12", "name": "[v2,04/20] ppc/xive2: Introduce a presenter matching routine", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a846ac8d490587c87bf4fa1529d7938ced86e02f", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-5-clg@kaod.org/mbox/", "series": [ { "id": 260743, "url": "http://patchwork.ozlabs.org/api/series/260743/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=260743", "date": "2021-09-02T13:09:11", "name": "ppc/pnv: Extend the powernv10 machine", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/260743/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1523772/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1523772/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "garm.ovh; auth=pass\n (GARM-101G00440870221-4fd5-48d0-aea0-001163a166b7,\n 0F69C8711EE098B745CC44F7BEC1CAFBB1DDDEDC) smtp.auth=clg@kaod.org" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4H0hmG56p7z9sPf\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 2 Sep 2021 23:36:46 +1000 (AEST)", "from localhost ([::1]:41652 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1mLmtY-0005lt-Gu\n\tfor incoming@patchwork.ozlabs.org; Thu, 02 Sep 2021 09:36:44 -0400", "from eggs.gnu.org ([2001:470:142:3::10]:42746)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTY-0006Rx-R3\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:09:52 -0400", "from 1.mo52.mail-out.ovh.net ([178.32.96.117]:57483)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTP-0001ts-Ev\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:09:52 -0400", "from mxplan5.mail.ovh.net (unknown [10.109.156.48])\n by mo52.mail-out.ovh.net (Postfix) with ESMTPS id 5A334295F3C;\n Thu, 2 Sep 2021 15:09:34 +0200 (CEST)", "from kaod.org (37.59.142.101) by DAG4EX1.mxp5.local (172.16.2.31)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Thu, 2 Sep\n 2021 15:09:32 +0200" ], "X-OVh-ClientIp": "82.64.250.170", "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>", "Subject": "[PATCH v2 04/20] ppc/xive2: Introduce a presenter matching routine", "Date": "Thu, 2 Sep 2021 15:09:12 +0200", "Message-ID": "<20210902130928.528803-5-clg@kaod.org>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20210902130928.528803-1-clg@kaod.org>", "References": "<20210902130928.528803-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[37.59.142.101]", "X-ClientProxiedBy": "DAG5EX1.mxp5.local (172.16.2.41) To DAG4EX1.mxp5.local\n (172.16.2.31)", "X-Ovh-Tracer-GUID": "11eabdd9-f3d2-4eba-aae1-e1146acb85eb", "X-Ovh-Tracer-Id": "14775184480637914019", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "\n gggruggvucftvghtrhhoucdtuddrgedvtddruddvhedgiedtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrddutddunecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopegtlhhgsehkrghougdrohhrgh", "Received-SPF": "pass client-ip=178.32.96.117; envelope-from=clg@kaod.org;\n helo=1.mo52.mail-out.ovh.net", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?=\n\t=?utf-8?q?ter?= <clg@kaod.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "The VP space is larger in XIVE2 (P10), 24 bits instead of 19bits on\nXIVE (P9), and the CAM line can use a 7bits or 8bits thread id.\n\nFor now, we only use 7bits thread ids, same as P9, but because of the\nchange of the size of the VP space, the CAM matching routine is\ndifferent between P9 and P10. It is easier to duplicate the whole\nroutine than to add extra handlers in xive_presenter_tctx_match() used\nfor P9.\n\nWe might come with a better solution later on, after we have added\nsome more support for the XIVE2 controller.\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n\n v2: fixed alignment\n \n include/hw/ppc/xive2.h | 9 +++++\n hw/intc/xive2.c | 82 ++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 91 insertions(+)", "diff": "diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h\nindex a3cd02520475..e881c039d9c0 100644\n--- a/include/hw/ppc/xive2.h\n+++ b/include/hw/ppc/xive2.h\n@@ -55,6 +55,15 @@ int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,\n \n void xive2_router_notify(XiveNotifier *xn, uint32_t lisn);\n \n+/*\n+ * XIVE2 Presenter (POWER10)\n+ */\n+\n+int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,\n+ uint8_t format,\n+ uint8_t nvt_blk, uint32_t nvt_idx,\n+ bool cam_ignore, uint32_t logic_serv);\n+\n /*\n * XIVE2 END ESBs (POWER10)\n */\ndiff --git a/hw/intc/xive2.c b/hw/intc/xive2.c\nindex e4aa614f3cc8..9e186bbb6cd9 100644\n--- a/hw/intc/xive2.c\n+++ b/hw/intc/xive2.c\n@@ -209,6 +209,88 @@ static int xive2_router_get_block_id(Xive2Router *xrtr)\n return xrc->get_block_id(xrtr);\n }\n \n+/*\n+ * Encode the HW CAM line with 7bit or 8bit thread id. The thread id\n+ * width and block id width is configurable at the IC level.\n+ *\n+ * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit)\n+ * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit)\n+ */\n+static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)\n+{\n+ Xive2Router *xrtr = XIVE2_ROUTER(xptr);\n+ CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;\n+ uint32_t pir = env->spr_cb[SPR_PIR].default_value;\n+ uint8_t blk = xive2_router_get_block_id(xrtr);\n+ uint8_t tid_shift = 7;\n+ uint8_t tid_mask = (1 << tid_shift) - 1;\n+\n+ return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask));\n+}\n+\n+/*\n+ * The thread context register words are in big-endian format.\n+ */\n+int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,\n+ uint8_t format,\n+ uint8_t nvt_blk, uint32_t nvt_idx,\n+ bool cam_ignore, uint32_t logic_serv)\n+{\n+ uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx);\n+ uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);\n+ uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);\n+ uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);\n+ uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]);\n+\n+ /*\n+ * TODO (PowerNV): ignore mode. The low order bits of the NVT\n+ * identifier are ignored in the \"CAM\" match.\n+ */\n+\n+ if (format == 0) {\n+ if (cam_ignore == true) {\n+ /*\n+ * F=0 & i=1: Logical server notification (bits ignored at\n+ * the end of the NVT identifier)\n+ */\n+ qemu_log_mask(LOG_UNIMP, \"XIVE: no support for LS NVT %x/%x\\n\",\n+ nvt_blk, nvt_idx);\n+ return -1;\n+ }\n+\n+ /* F=0 & i=0: Specific NVT notification */\n+\n+ /* PHYS ring */\n+ if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) &&\n+ cam == xive2_tctx_hw_cam_line(xptr, tctx)) {\n+ return TM_QW3_HV_PHYS;\n+ }\n+\n+ /* HV POOL ring */\n+ if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) &&\n+ cam == xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) {\n+ return TM_QW2_HV_POOL;\n+ }\n+\n+ /* OS ring */\n+ if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&\n+ cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) {\n+ return TM_QW1_OS;\n+ }\n+ } else {\n+ /* F=1 : User level Event-Based Branch (EBB) notification */\n+\n+ /* USER ring */\n+ if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&\n+ (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) &&\n+ (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) &&\n+ (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) {\n+ return TM_QW0_USER;\n+ }\n+ }\n+ return -1;\n+}\n+\n static void xive2_router_realize(DeviceState *dev, Error **errp)\n {\n Xive2Router *xrtr = XIVE2_ROUTER(dev);\n", "prefixes": [ "v2", "04/20" ] }