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GET /api/patches/1523771/?format=api
{ "id": 1523771, "url": "http://patchwork.ozlabs.org/api/patches/1523771/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-10-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210902130928.528803-10-clg@kaod.org>", "list_archive_url": null, "date": "2021-09-02T13:09:17", "name": "[v2,09/20] ppc/pnv: Add a HOMER model to POWER10", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6f2dc546a8c7b893cb0d2fbf2a67db2ebe3fcb4f", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-10-clg@kaod.org/mbox/", "series": [ { "id": 260743, "url": "http://patchwork.ozlabs.org/api/series/260743/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=260743", "date": "2021-09-02T13:09:11", "name": "ppc/pnv: Extend the powernv10 machine", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/260743/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1523771/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1523771/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "garm.ovh; auth=pass\n (GARM-101G0045a2634fa-b711-461f-8bd3-00574141f9bc,\n 0F69C8711EE098B745CC44F7BEC1CAFBB1DDDEDC) smtp.auth=clg@kaod.org" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4H0hm83X4mz9sPf\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 2 Sep 2021 23:36:40 +1000 (AEST)", "from localhost ([::1]:41126 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1mLmtS-0005Q3-8m\n\tfor incoming@patchwork.ozlabs.org; Thu, 02 Sep 2021 09:36:38 -0400", "from eggs.gnu.org ([2001:470:142:3::10]:42884)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTe-0006lq-9i\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:09:58 -0400", "from 5.mo52.mail-out.ovh.net ([188.165.45.220]:58421)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTR-0001wD-Fp\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:09:57 -0400", "from mxplan5.mail.ovh.net (unknown [10.109.156.48])\n by mo52.mail-out.ovh.net (Postfix) with ESMTPS id 54D4C295F31;\n Thu, 2 Sep 2021 15:09:36 +0200 (CEST)", "from kaod.org (37.59.142.101) by DAG4EX1.mxp5.local (172.16.2.31)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Thu, 2 Sep\n 2021 15:09:34 +0200" ], "X-OVh-ClientIp": "82.64.250.170", "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>", "Subject": "[PATCH v2 09/20] ppc/pnv: Add a HOMER model to POWER10", "Date": "Thu, 2 Sep 2021 15:09:17 +0200", "Message-ID": "<20210902130928.528803-10-clg@kaod.org>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20210902130928.528803-1-clg@kaod.org>", "References": "<20210902130928.528803-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[37.59.142.101]", "X-ClientProxiedBy": "DAG5EX1.mxp5.local (172.16.2.41) To DAG4EX1.mxp5.local\n (172.16.2.31)", "X-Ovh-Tracer-GUID": "9c08529a-1be9-4d9e-995e-94e9057fd6d6", "X-Ovh-Tracer-Id": "14775747428900572067", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "\n gggruggvucftvghtrhhoucdtuddrgedvtddruddvhedgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrddutddunecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopegtlhhgsehkrghougdrohhrgh", "Received-SPF": "pass client-ip=188.165.45.220; envelope-from=clg@kaod.org;\n helo=5.mo52.mail-out.ovh.net", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?=\n\t=?utf-8?q?ter?= <clg@kaod.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Reviewed-by: David Gibson <david@gibson.dropbear.id.au>\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n include/hw/ppc/pnv.h | 10 ++++++\n include/hw/ppc/pnv_homer.h | 3 ++\n include/hw/ppc/pnv_xscom.h | 3 ++\n hw/ppc/pnv.c | 20 ++++++++++++\n hw/ppc/pnv_homer.c | 64 ++++++++++++++++++++++++++++++++++++++\n 5 files changed, 100 insertions(+)", "diff": "diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h\nindex f44b9947d00e..3ea2d798eed1 100644\n--- a/include/hw/ppc/pnv.h\n+++ b/include/hw/ppc/pnv.h\n@@ -128,6 +128,7 @@ struct Pnv10Chip {\n Pnv9Psi psi;\n PnvLpcController lpc;\n PnvOCC occ;\n+ PnvHomer homer;\n \n uint32_t nr_quads;\n PnvQuad *quads;\n@@ -358,4 +359,13 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);\n #define PNV10_XIVE2_END_SIZE 0x0000020000000000ull\n #define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull)\n \n+#define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull\n+#define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull\n+#define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \\\n+ PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))\n+\n+#define PNV10_HOMER_SIZE 0x0000000000400000ull\n+#define PNV10_HOMER_BASE(chip) \\\n+ (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE)\n+\n #endif /* PPC_PNV_H */\ndiff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h\nindex 1889e3083c57..07e8b193116e 100644\n--- a/include/hw/ppc/pnv_homer.h\n+++ b/include/hw/ppc/pnv_homer.h\n@@ -32,6 +32,9 @@ DECLARE_INSTANCE_CHECKER(PnvHomer, PNV8_HOMER,\n #define TYPE_PNV9_HOMER TYPE_PNV_HOMER \"-POWER9\"\n DECLARE_INSTANCE_CHECKER(PnvHomer, PNV9_HOMER,\n TYPE_PNV9_HOMER)\n+#define TYPE_PNV10_HOMER TYPE_PNV_HOMER \"-POWER10\"\n+DECLARE_INSTANCE_CHECKER(PnvHomer, PNV10_HOMER,\n+ TYPE_PNV10_HOMER)\n \n struct PnvHomer {\n DeviceState parent;\ndiff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h\nindex 75db33d46af6..7c7440de0c40 100644\n--- a/include/hw/ppc/pnv_xscom.h\n+++ b/include/hw/ppc/pnv_xscom.h\n@@ -134,6 +134,9 @@ struct PnvXScomInterfaceClass {\n #define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE\n #define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE\n \n+#define PNV10_XSCOM_PBA_BASE 0x01010CDA\n+#define PNV10_XSCOM_PBA_SIZE 0x40\n+\n #define PNV10_XSCOM_XIVE2_BASE 0x2010800\n #define PNV10_XSCOM_XIVE2_SIZE 0x400\n \ndiff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c\nindex 0de3027b7122..d510d2e1d917 100644\n--- a/hw/ppc/pnv.c\n+++ b/hw/ppc/pnv.c\n@@ -1621,6 +1621,7 @@ static void pnv_chip_power10_instance_init(Object *obj)\n object_initialize_child(obj, \"psi\", &chip10->psi, TYPE_PNV10_PSI);\n object_initialize_child(obj, \"lpc\", &chip10->lpc, TYPE_PNV10_LPC);\n object_initialize_child(obj, \"occ\", &chip10->occ, TYPE_PNV10_OCC);\n+ object_initialize_child(obj, \"homer\", &chip10->homer, TYPE_PNV10_HOMER);\n \n for (i = 0; i < PNV10_CHIP_MAX_PEC; i++) {\n object_initialize_child(obj, \"pec[*]\", &chip10->pecs[i],\n@@ -1795,6 +1796,25 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)\n pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,\n &chip10->occ.xscom_regs);\n \n+ /* OCC SRAM model */\n+ memory_region_add_subregion(get_system_memory(),\n+ PNV10_OCC_SENSOR_BASE(chip),\n+ &chip10->occ.sram_regs);\n+\n+ /* HOMER */\n+ object_property_set_link(OBJECT(&chip10->homer), \"chip\", OBJECT(chip),\n+ &error_abort);\n+ if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {\n+ return;\n+ }\n+ /* Homer Xscom region */\n+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,\n+ &chip10->homer.pba_regs);\n+\n+ /* Homer mmio region */\n+ memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),\n+ &chip10->homer.regs);\n+\n /* PHBs */\n pnv_chip_power10_phb_realize(chip, &local_err);\n if (local_err) {\ndiff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c\nindex 9a262629b73a..ea73919e54ca 100644\n--- a/hw/ppc/pnv_homer.c\n+++ b/hw/ppc/pnv_homer.c\n@@ -332,6 +332,69 @@ static const TypeInfo pnv_homer_power9_type_info = {\n .class_init = pnv_homer_power9_class_init,\n };\n \n+static uint64_t pnv_homer_power10_pba_read(void *opaque, hwaddr addr,\n+ unsigned size)\n+{\n+ PnvHomer *homer = PNV_HOMER(opaque);\n+ PnvChip *chip = homer->chip;\n+ uint32_t reg = addr >> 3;\n+ uint64_t val = 0;\n+\n+ switch (reg) {\n+ case PBA_BAR0:\n+ val = PNV10_HOMER_BASE(chip);\n+ break;\n+ case PBA_BARMASK0: /* P10 homer region mask */\n+ val = (PNV10_HOMER_SIZE - 1) & 0x300000;\n+ break;\n+ case PBA_BAR2: /* P10 occ common area */\n+ val = PNV10_OCC_COMMON_AREA_BASE;\n+ break;\n+ case PBA_BARMASK2: /* P10 occ common area size */\n+ val = (PNV10_OCC_COMMON_AREA_SIZE - 1) & 0x700000;\n+ break;\n+ default:\n+ qemu_log_mask(LOG_UNIMP, \"PBA: read to unimplemented register: Ox%\"\n+ HWADDR_PRIx \"\\n\", addr >> 3);\n+ }\n+ return val;\n+}\n+\n+static void pnv_homer_power10_pba_write(void *opaque, hwaddr addr,\n+ uint64_t val, unsigned size)\n+{\n+ qemu_log_mask(LOG_UNIMP, \"PBA: write to unimplemented register: Ox%\"\n+ HWADDR_PRIx \"\\n\", addr >> 3);\n+}\n+\n+static const MemoryRegionOps pnv_homer_power10_pba_ops = {\n+ .read = pnv_homer_power10_pba_read,\n+ .write = pnv_homer_power10_pba_write,\n+ .valid.min_access_size = 8,\n+ .valid.max_access_size = 8,\n+ .impl.min_access_size = 8,\n+ .impl.max_access_size = 8,\n+ .endianness = DEVICE_BIG_ENDIAN,\n+};\n+\n+static void pnv_homer_power10_class_init(ObjectClass *klass, void *data)\n+{\n+ PnvHomerClass *homer = PNV_HOMER_CLASS(klass);\n+\n+ homer->pba_size = PNV10_XSCOM_PBA_SIZE;\n+ homer->pba_ops = &pnv_homer_power10_pba_ops;\n+ homer->homer_size = PNV10_HOMER_SIZE;\n+ homer->homer_ops = &pnv_power9_homer_ops; /* TODO */\n+ homer->core_max_base = PNV9_CORE_MAX_BASE;\n+}\n+\n+static const TypeInfo pnv_homer_power10_type_info = {\n+ .name = TYPE_PNV10_HOMER,\n+ .parent = TYPE_PNV_HOMER,\n+ .instance_size = sizeof(PnvHomer),\n+ .class_init = pnv_homer_power10_class_init,\n+};\n+\n static void pnv_homer_realize(DeviceState *dev, Error **errp)\n {\n PnvHomer *homer = PNV_HOMER(dev);\n@@ -377,6 +440,7 @@ static void pnv_homer_register_types(void)\n type_register_static(&pnv_homer_type_info);\n type_register_static(&pnv_homer_power8_type_info);\n type_register_static(&pnv_homer_power9_type_info);\n+ type_register_static(&pnv_homer_power10_type_info);\n }\n \n type_init(pnv_homer_register_types);\n", "prefixes": [ "v2", "09/20" ] }