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GET /api/patches/1523766/?format=api
{ "id": 1523766, "url": "http://patchwork.ozlabs.org/api/patches/1523766/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-18-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210902130928.528803-18-clg@kaod.org>", "list_archive_url": null, "date": "2021-09-02T13:09:25", "name": "[v2,17/20] pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1)", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "11c5570e67f14871a6e95c58ecc2b35ab9d6c5da", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-18-clg@kaod.org/mbox/", "series": [ { "id": 260743, "url": "http://patchwork.ozlabs.org/api/series/260743/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=260743", "date": "2021-09-02T13:09:11", "name": "ppc/pnv: Extend the powernv10 machine", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/260743/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1523766/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1523766/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "garm.ovh; auth=pass\n (GARM-101G004ffd7f8bf-d307-4b2d-84a6-979533aae3dc,\n 0F69C8711EE098B745CC44F7BEC1CAFBB1DDDEDC) smtp.auth=clg@kaod.org" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4H0hbT40Qdz9sPf\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 2 Sep 2021 23:29:09 +1000 (AEST)", "from localhost ([::1]:52552 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1mLmmA-0001eA-8E\n\tfor incoming@patchwork.ozlabs.org; Thu, 02 Sep 2021 09:29:06 -0400", "from eggs.gnu.org ([2001:470:142:3::10]:42606)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>)\n id 1mLmTT-00068f-Gx; Thu, 02 Sep 2021 09:09:47 -0400", "from smtpout1.mo529.mail-out.ovh.net ([178.32.125.2]:51859)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>)\n id 1mLmTO-0001z4-Mi; Thu, 02 Sep 2021 09:09:47 -0400", "from mxplan5.mail.ovh.net (unknown [10.108.4.92])\n by mo529.mail-out.ovh.net (Postfix) with ESMTPS id AB07CBC1123A;\n Thu, 2 Sep 2021 15:09:39 +0200 (CEST)", "from kaod.org (37.59.142.101) by DAG4EX1.mxp5.local (172.16.2.31)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Thu, 2 Sep\n 2021 15:09:37 +0200" ], "X-OVh-ClientIp": "82.64.250.170", "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>", "Subject": "[PATCH v2 17/20] pnv/xive2: Add support XIVE2 P9-compat mode (or\n Gen1)", "Date": "Thu, 2 Sep 2021 15:09:25 +0200", "Message-ID": "<20210902130928.528803-18-clg@kaod.org>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20210902130928.528803-1-clg@kaod.org>", "References": "<20210902130928.528803-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[37.59.142.101]", "X-ClientProxiedBy": "DAG5EX1.mxp5.local (172.16.2.41) To DAG4EX1.mxp5.local\n (172.16.2.31)", "X-Ovh-Tracer-GUID": "11ce4bc0-07c9-4bd3-a0f7-c1dd86c16e6b", "X-Ovh-Tracer-Id": "14776873331081907107", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "\n gggruggvucftvghtrhhoucdtuddrgedvtddruddvhedgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrddutddunecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopegtlhhgsehkrghougdrohhrgh", "Received-SPF": "pass client-ip=178.32.125.2; envelope-from=clg@kaod.org;\n helo=smtpout1.mo529.mail-out.ovh.net", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?=\n\t=?utf-8?q?ter?= <clg@kaod.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "The thread interrupt management area (TIMA) is a set of pages mapped\nin the Hypervisor and in the guest OS address space giving access to\nthe interrupt thread context registers for interrupt management, ACK,\nEOI, CPPR, etc.\n\nXIVE2 changes slightly the TIMA layout with extra bits for the new\nfeatures, larger CAM lines and the controller provides configuration\nswitches for backward compatibility. This is called the XIVE2\nP9-compat mode, of Gen1 TIMA. It impacts the layout of the TIMA and\nthe availability of the internal features associated with it,\nAutomatic Save & Restore for instance. Using a P9 layout also means\nsetting the controller in such a mode at init time.\n\nAs the OPAL driver initializes the XIVE2 controller with a XIVE2/P10\nTIMA directly, the XIVE2 model only has a simple support for the\ncompat mode in the OS TIMA.\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n hw/intc/pnv_xive2_regs.h | 6 ++++++\n hw/intc/pnv_xive2.c | 22 +++++++++++++++++-----\n 2 files changed, 23 insertions(+), 5 deletions(-)", "diff": "diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h\nindex 46d4fb378135..902220e6be69 100644\n--- a/hw/intc/pnv_xive2_regs.h\n+++ b/hw/intc/pnv_xive2_regs.h\n@@ -60,6 +60,12 @@\n #define CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE PPC_BIT(16)\n #define CQ_XIVE_CFG_HYP_HARD_BLOCK_ID PPC_BITMASK(17, 23)\n \n+#define CQ_XIVE_CFG_GEN1_TIMA_OS PPC_BIT(24)\n+#define CQ_XIVE_CFG_GEN1_TIMA_HYP PPC_BIT(25)\n+#define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26) /* 0 if bit[25]=0 */\n+#define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25]=0 */\n+#define CQ_XIVE_CFG_GEN1_END_ESX PPC_BIT(28)\n+\n /* Interrupt Controller Base Address Register - 512 pages (32M) */\n #define X_CQ_IC_BAR 0x08\n #define CQ_IC_BAR 0x040\ndiff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c\nindex 4a2649893232..b364ee3b306b 100644\n--- a/hw/intc/pnv_xive2.c\n+++ b/hw/intc/pnv_xive2.c\n@@ -444,6 +444,8 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format,\n PnvChip *chip = xive->chip;\n int count = 0;\n int i, j;\n+ bool gen1_tima_os =\n+ xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS;\n \n for (i = 0; i < chip->nr_cores; i++) {\n PnvCore *pc = chip->cores[i];\n@@ -460,9 +462,15 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format,\n \n tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);\n \n- ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk,\n- nvt_idx, cam_ignore,\n- logic_serv);\n+ if (gen1_tima_os) {\n+ ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk,\n+ nvt_idx, cam_ignore,\n+ logic_serv);\n+ } else {\n+ ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk,\n+ nvt_idx, cam_ignore,\n+ logic_serv);\n+ }\n \n /*\n * Save the context and follow on to catch duplicates,\n@@ -1627,9 +1635,11 @@ static void pnv_xive2_tm_write(void *opaque, hwaddr offset,\n PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);\n XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);\n XivePresenter *xptr = XIVE_PRESENTER(xive);\n+ bool gen1_tima_os =\n+ xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS;\n \n /* TODO: should we switch the TM ops table instead ? */\n- if (offset == HV_PUSH_OS_CTX_OFFSET) {\n+ if (!gen1_tima_os && offset == HV_PUSH_OS_CTX_OFFSET) {\n xive2_tm_push_os_ctx(xptr, tctx, offset, value, size);\n return;\n }\n@@ -1644,9 +1654,11 @@ static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size)\n PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);\n XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);\n XivePresenter *xptr = XIVE_PRESENTER(xive);\n+ bool gen1_tima_os =\n+ xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS;\n \n /* TODO: should we switch the TM ops table instead ? */\n- if (offset == HV_PULL_OS_CTX_OFFSET) {\n+ if (!gen1_tima_os && offset == HV_PULL_OS_CTX_OFFSET) {\n return xive2_tm_pull_os_ctx(xptr, tctx, offset, size);\n }\n \n", "prefixes": [ "v2", "17/20" ] }