Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1523756/?format=api
{ "id": 1523756, "url": "http://patchwork.ozlabs.org/api/patches/1523756/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-20-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210902130928.528803-20-clg@kaod.org>", "list_archive_url": null, "date": "2021-09-02T13:09:27", "name": "[v2,19/20] pnv/xive2: Add support for automatic save&restore", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9b163f709e80bf97190f73b9d9b90bff559b1e4f", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-20-clg@kaod.org/mbox/", "series": [ { "id": 260743, "url": "http://patchwork.ozlabs.org/api/series/260743/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=260743", "date": "2021-09-02T13:09:11", "name": "ppc/pnv: Extend the powernv10 machine", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/260743/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1523756/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1523756/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "garm.ovh; auth=pass\n (GARM-101G0049adc2f3c-4028-4e82-b828-c80216c3692a,\n 0F69C8711EE098B745CC44F7BEC1CAFBB1DDDEDC) smtp.auth=clg@kaod.org" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4H0hWX6lbYz9sVw\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 2 Sep 2021 23:25:44 +1000 (AEST)", "from localhost ([::1]:42342 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1mLmis-0003Cg-Mc\n\tfor incoming@patchwork.ozlabs.org; Thu, 02 Sep 2021 09:25:42 -0400", "from eggs.gnu.org ([2001:470:142:3::10]:42668)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>)\n id 1mLmTV-0006GP-V0; Thu, 02 Sep 2021 09:09:50 -0400", "from smtpout1.mo529.mail-out.ovh.net ([178.32.125.2]:36743)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>)\n id 1mLmTO-0001zQ-OT; Thu, 02 Sep 2021 09:09:49 -0400", "from mxplan5.mail.ovh.net (unknown [10.108.4.92])\n by mo529.mail-out.ovh.net (Postfix) with ESMTPS id 317E4BC1123F;\n Thu, 2 Sep 2021 15:09:40 +0200 (CEST)", "from kaod.org (37.59.142.101) by DAG4EX1.mxp5.local (172.16.2.31)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Thu, 2 Sep\n 2021 15:09:38 +0200" ], "X-OVh-ClientIp": "82.64.250.170", "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>", "Subject": "[PATCH v2 19/20] pnv/xive2: Add support for automatic save&restore", "Date": "Thu, 2 Sep 2021 15:09:27 +0200", "Message-ID": "<20210902130928.528803-20-clg@kaod.org>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20210902130928.528803-1-clg@kaod.org>", "References": "<20210902130928.528803-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[37.59.142.101]", "X-ClientProxiedBy": "DAG5EX1.mxp5.local (172.16.2.41) To DAG4EX1.mxp5.local\n (172.16.2.31)", "X-Ovh-Tracer-GUID": "9739be4d-2f21-49fd-aa48-bc9c55dc27a7", "X-Ovh-Tracer-Id": "14776873329100098467", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "\n gggruggvucftvghtrhhoucdtuddrgedvtddruddvhedgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrddutddunecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopegtlhhgsehkrghougdrohhrgh", "Received-SPF": "pass client-ip=178.32.125.2; envelope-from=clg@kaod.org;\n helo=smtpout1.mo529.mail-out.ovh.net", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?=\n\t=?utf-8?q?ter?= <clg@kaod.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "The XIVE interrupt controller on P10 can automatically save and\nrestore the state of the interrupt registers under the internal NVP\nstructure representing the VCPU. This saves a costly store/load in\nguest entries and exits.\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n hw/intc/pnv_xive2_regs.h | 3 +\n include/hw/ppc/xive2.h | 1 +\n include/hw/ppc/xive2_regs.h | 12 ++++\n hw/intc/pnv_xive2.c | 18 +++++-\n hw/intc/xive2.c | 126 ++++++++++++++++++++++++++++++++++--\n 5 files changed, 154 insertions(+), 6 deletions(-)", "diff": "diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h\nindex 902220e6be69..3488ae188938 100644\n--- a/hw/intc/pnv_xive2_regs.h\n+++ b/hw/intc/pnv_xive2_regs.h\n@@ -30,6 +30,7 @@\n #define CQ_XIVE_CAP_VP_INT_PRIO_4_8 2\n #define CQ_XIVE_CAP_VP_INT_PRIO_8 3\n #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)\n+#define CQ_XIVE_CAP_VP_SAVE_RESTORE PPC_BIT(38)\n \n #define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56)\n #define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57)\n@@ -65,6 +66,8 @@\n #define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26) /* 0 if bit[25]=0 */\n #define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25]=0 */\n #define CQ_XIVE_CFG_GEN1_END_ESX PPC_BIT(28)\n+#define CQ_XIVE_CFG_EN_VP_SAVE_RESTORE PPC_BIT(38) /* 0 if bit[25]=1 */\n+#define CQ_XIVE_CFG_EN_VP_SAVE_REST_STRICT PPC_BIT(39) /* 0 if bit[25]=1 */\n \n /* Interrupt Controller Base Address Register - 512 pages (32M) */\n #define X_CQ_IC_BAR 0x08\ndiff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h\nindex b08600cbd5ee..88c3e393162d 100644\n--- a/include/hw/ppc/xive2.h\n+++ b/include/hw/ppc/xive2.h\n@@ -30,6 +30,7 @@ OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER);\n */\n \n #define XIVE2_GEN1_TIMA_OS 0x00000001\n+#define XIVE2_VP_SAVE_RESTORE 0x00000002\n \n typedef struct Xive2RouterClass {\n SysBusDeviceClass parent;\ndiff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h\nindex f4827f4c6d54..d214b49bef75 100644\n--- a/include/hw/ppc/xive2_regs.h\n+++ b/include/hw/ppc/xive2_regs.h\n@@ -20,10 +20,13 @@\n #define TM2_QW0W2_VU PPC_BIT32(0)\n #define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31)\n #define TM2_QW1W2_VO PPC_BIT32(0)\n+#define TM2_QW1W2_HO PPC_BIT32(1)\n #define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31)\n #define TM2_QW2W2_VP PPC_BIT32(0)\n+#define TM2_QW2W2_HP PPC_BIT32(1)\n #define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31)\n #define TM2_QW3W2_VT PPC_BIT32(0)\n+#define TM2_QW3W2_HT PPC_BIT32(1)\n #define TM2_QW3W2_LP PPC_BIT32(6)\n #define TM2_QW3W2_LE PPC_BIT32(7)\n \n@@ -137,10 +140,17 @@ void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,\n typedef struct Xive2Nvp {\n uint32_t w0;\n #define NVP2_W0_VALID PPC_BIT32(0)\n+#define NVP2_W0_HW PPC_BIT32(7)\n #define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */\n uint32_t w1;\n+#define NVP2_W1_CO PPC_BIT32(13)\n+#define NVP2_W1_CO_PRIV PPC_BITMASK32(14, 15)\n+#define NVP2_W1_CO_THRID_VALID PPC_BIT32(16)\n+#define NVP2_W1_CO_THRID PPC_BITMASK32(17, 31)\n uint32_t w2;\n+#define NVP2_W2_CPPR PPC_BITMASK32(0, 7)\n #define NVP2_W2_IPB PPC_BITMASK32(8, 15)\n+#define NVP2_W2_LSMFB PPC_BITMASK32(16, 23)\n uint32_t w3;\n uint32_t w4;\n #define NVP2_W4_ESC_ESB_BLOCK PPC_BITMASK32(0, 3) /* N:0 */\n@@ -156,6 +166,8 @@ typedef struct Xive2Nvp {\n } Xive2Nvp;\n \n #define xive2_nvp_is_valid(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_VALID)\n+#define xive2_nvp_is_hw(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_HW)\n+#define xive2_nvp_is_co(nvp) (be32_to_cpu((nvp)->w1) & NVP2_W1_CO)\n \n /*\n * The VP number space in a block is defined by the END2_W6_VP_OFFSET\ndiff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c\nindex 2b7d6ccbd097..6f0a63cd3d2f 100644\n--- a/hw/intc/pnv_xive2.c\n+++ b/hw/intc/pnv_xive2.c\n@@ -434,6 +434,10 @@ static uint32_t pnv_xive2_get_config(Xive2Router *xrtr)\n cfg |= XIVE2_GEN1_TIMA_OS;\n }\n \n+ if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) {\n+ cfg |= XIVE2_VP_SAVE_RESTORE;\n+ }\n+\n return cfg;\n }\n \n@@ -1999,9 +2003,21 @@ static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx,\n return;\n }\n \n- monitor_printf(mon, \" %08x end:%02x/%04x IPB:%02x\\n\",\n+ monitor_printf(mon, \" %08x end:%02x/%04x IPB:%02x\",\n nvp_idx, eq_blk, eq_idx,\n xive_get_field32(NVP2_W2_IPB, nvp->w2));\n+ /*\n+ * When the NVP is HW controlled, more fields are updated\n+ */\n+ if (xive2_nvp_is_hw(nvp)) {\n+ monitor_printf(mon, \" CPPR:%02x\",\n+ xive_get_field32(NVP2_W2_CPPR, nvp->w2));\n+ if (xive2_nvp_is_co(nvp)) {\n+ monitor_printf(mon, \" CO:%04x\",\n+ xive_get_field32(NVP2_W1_CO_THRID, nvp->w1));\n+ }\n+ }\n+ monitor_printf(mon, \"\\n\");\n }\n \n /*\ndiff --git a/hw/intc/xive2.c b/hw/intc/xive2.c\nindex 71086c7fbd01..978a0e3972e1 100644\n--- a/hw/intc/xive2.c\n+++ b/hw/intc/xive2.c\n@@ -168,27 +168,92 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t data)\n \n /*\n * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode\n+ *\n+ * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit\n+ *\n+ * - if a context is enabled with the H bit set, the VP context\n+ * information is retrieved from the NVP structure (“check out”)\n+ * and stored back on a context pull (“check in”), the SW receives\n+ * the same context pull information as on P9\n+ *\n+ * - the H bit cannot be changed while the V bit is set, i.e. a\n+ * context cannot be set up in the TIMA and then be “pushed” into\n+ * the NVP by changing the H bit while the context is enabled\n */\n \n+static void xive2_tctx_save_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx,\n+ uint8_t nvp_blk, uint32_t nvp_idx)\n+{\n+ CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;\n+ uint32_t pir = env->spr_cb[SPR_PIR].default_value;\n+ Xive2Nvp nvp;\n+ uint8_t *regs = &tctx->regs[TM_QW1_OS];\n+\n+ if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: No NVP %x/%x\\n\",\n+ nvp_blk, nvp_idx);\n+ return;\n+ }\n+\n+ if (!xive2_nvp_is_valid(&nvp)) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: invalid NVP %x/%x\\n\",\n+ nvp_blk, nvp_idx);\n+ return;\n+ }\n+\n+ if (!xive2_nvp_is_hw(&nvp)) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: NVP %x/%x is not HW owned\\n\",\n+ nvp_blk, nvp_idx);\n+ return;\n+ }\n+\n+ if (!xive2_nvp_is_co(&nvp)) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: NVP %x/%x is not checkout\\n\",\n+ nvp_blk, nvp_idx);\n+ return;\n+ }\n+\n+ if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) &&\n+ xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"XIVE: NVP %x/%x invalid checkout Thread %x\\n\",\n+ nvp_blk, nvp_idx, pir);\n+ return;\n+ }\n+\n+ nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]);\n+ nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]);\n+ nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]);\n+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);\n+\n+ nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0);\n+ /* NVP2_W1_CO_THRID_VALID only set once */\n+ nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF);\n+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1);\n+}\n+\n static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk,\n- uint32_t *nvp_idx, bool *vo)\n+ uint32_t *nvp_idx, bool *vo, bool *ho)\n {\n *nvp_blk = xive2_nvp_blk(cam);\n *nvp_idx = xive2_nvp_idx(cam);\n *vo = !!(cam & TM2_QW1W2_VO);\n+ *ho = !!(cam & TM2_QW1W2_HO);\n }\n \n uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,\n hwaddr offset, unsigned size)\n {\n+ Xive2Router *xrtr = XIVE2_ROUTER(xptr);\n uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);\n uint32_t qw1w2_new;\n uint32_t cam = be32_to_cpu(qw1w2);\n uint8_t nvp_blk;\n uint32_t nvp_idx;\n bool vo;\n+ bool do_save;\n \n- xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo);\n+ xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save);\n \n if (!vo) {\n qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: pulling invalid NVP %x/%x !?\\n\",\n@@ -199,11 +264,54 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,\n qw1w2_new = xive_set_field32(TM2_QW1W2_VO, qw1w2, 0);\n memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4);\n \n+ if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) {\n+ xive2_tctx_save_os_ctx(xrtr, tctx, nvp_blk, nvp_idx);\n+ }\n+\n return qw1w2;\n }\n \n+static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx,\n+ uint8_t nvp_blk, uint32_t nvp_idx,\n+ Xive2Nvp *nvp)\n+{\n+ CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;\n+ uint32_t pir = env->spr_cb[SPR_PIR].default_value;\n+ uint8_t cppr;\n+\n+ if (!xive2_nvp_is_hw(nvp)) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: NVP %x/%x is not HW owned\\n\",\n+ nvp_blk, nvp_idx);\n+ return 0;\n+ }\n+\n+ cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2);\n+ nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0);\n+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2);\n+\n+ tctx->regs[TM_QW1_OS + TM_CPPR] = cppr;\n+ /* we don't model LSMFB */\n+\n+ nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1);\n+ nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1);\n+ nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir);\n+\n+ /*\n+ * Checkout privilege: 0:OS, 1:Pool, 2:Hard\n+ *\n+ * TODO: we only support OS push/pull\n+ */\n+ nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0);\n+\n+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1);\n+\n+ /* return restored CPPR to generate a CPU exception if needed */\n+ return cppr;\n+}\n+\n static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,\n- uint8_t nvp_blk, uint32_t nvp_idx)\n+ uint8_t nvp_blk, uint32_t nvp_idx,\n+ bool do_restore)\n {\n Xive2Nvp nvp;\n uint8_t ipb;\n@@ -225,6 +333,12 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,\n return;\n }\n \n+ /* Automatically restore thread context registers */\n+ if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE &&\n+ do_restore) {\n+ cppr = xive2_tctx_restore_os_ctx(xrtr, tctx, nvp_blk, nvp_idx, &nvp);\n+ }\n+\n ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2);\n if (ipb) {\n nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0);\n@@ -248,15 +362,17 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,\n uint8_t nvp_blk;\n uint32_t nvp_idx;\n bool vo;\n+ bool do_restore;\n \n- xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo);\n+ xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore);\n \n /* First update the thead context */\n memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);\n \n /* Check the interrupt pending bits */\n if (vo) {\n- xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx);\n+ xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx,\n+ do_restore);\n }\n }\n \n", "prefixes": [ "v2", "19/20" ] }