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GET /api/patches/1523755/?format=api
{ "id": 1523755, "url": "http://patchwork.ozlabs.org/api/patches/1523755/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-14-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210902130928.528803-14-clg@kaod.org>", "list_archive_url": null, "date": "2021-09-02T13:09:21", "name": "[v2,13/20] ppc/pnv: Add support for PQ offload on PHB5", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7b57ea1684da2ac47b7b27428c4eb98efd78cee1", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-14-clg@kaod.org/mbox/", "series": [ { "id": 260743, "url": "http://patchwork.ozlabs.org/api/series/260743/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=260743", "date": "2021-09-02T13:09:11", "name": "ppc/pnv: Extend the powernv10 machine", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/260743/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1523755/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1523755/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "garm.ovh; auth=pass\n (GARM-101G00495fe6b5e-d002-4dac-b4db-7b7e8ed82878,\n 0F69C8711EE098B745CC44F7BEC1CAFBB1DDDEDC) smtp.auth=clg@kaod.org" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4H0hTd2QPvz9t0T\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 2 Sep 2021 23:24:05 +1000 (AEST)", "from localhost ([::1]:34866 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1mLmhH-0006h7-3f\n\tfor incoming@patchwork.ozlabs.org; Thu, 02 Sep 2021 09:24:03 -0400", "from eggs.gnu.org ([2001:470:142:3::10]:42446)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTP-0005ud-TM\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:09:43 -0400", "from 2.mo52.mail-out.ovh.net ([178.33.105.233]:42076)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTL-0001xm-RR\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:09:43 -0400", "from mxplan5.mail.ovh.net (unknown [10.109.156.48])\n by mo52.mail-out.ovh.net (Postfix) with ESMTPS id 71C15295ECF;\n Thu, 2 Sep 2021 15:09:38 +0200 (CEST)", "from kaod.org (37.59.142.101) by DAG4EX1.mxp5.local (172.16.2.31)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Thu, 2 Sep\n 2021 15:09:36 +0200" ], "X-OVh-ClientIp": "82.64.250.170", "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>", "Subject": "[PATCH v2 13/20] ppc/pnv: Add support for PQ offload on PHB5", "Date": "Thu, 2 Sep 2021 15:09:21 +0200", "Message-ID": "<20210902130928.528803-14-clg@kaod.org>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20210902130928.528803-1-clg@kaod.org>", "References": "<20210902130928.528803-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[37.59.142.101]", "X-ClientProxiedBy": "DAG5EX1.mxp5.local (172.16.2.41) To DAG4EX1.mxp5.local\n (172.16.2.31)", "X-Ovh-Tracer-GUID": "37cd8b45-cb29-46b9-a303-476feb875f7c", "X-Ovh-Tracer-Id": "14776310380851399587", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "\n gggruggvucftvghtrhhoucdtuddrgedvtddruddvhedgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrddutddunecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopegtlhhgsehkrghougdrohhrgh", "Received-SPF": "pass client-ip=178.33.105.233; envelope-from=clg@kaod.org;\n helo=2.mo52.mail-out.ovh.net", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?=\n\t=?utf-8?q?ter?= <clg@kaod.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "The PQ_disable configuration bit disables the check done on the PQ\nstate bits when processing new MSI interrupts. When bit 9 is enabled,\nthe PHB forwards any MSI trigger to the XIVE interrupt controller\nwithout checking the PQ state bits. The XIVE IC knows from the trigger\nmessage that the PQ bits have not been checked and performs the check\nlocally.\n\nThis configuration bit only applies to MSIs and LSIs are still checked\non the PHB to handle the assertion level.\n\nPQ_disable enablement is a requirement for StoreEOI.\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n include/hw/pci-host/pnv_phb4_regs.h | 1 +\n include/hw/ppc/xive.h | 1 +\n hw/intc/xive.c | 22 +++++++++++++++++++++-\n hw/pci-host/pnv_phb4.c | 9 +++++++++\n 4 files changed, 32 insertions(+), 1 deletion(-)", "diff": "diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h\nindex 55df2c3e5ece..64f326b7158e 100644\n--- a/include/hw/pci-host/pnv_phb4_regs.h\n+++ b/include/hw/pci-host/pnv_phb4_regs.h\n@@ -225,6 +225,7 @@\n /* Fundamental register set B */\n #define PHB_VERSION 0x800\n #define PHB_CTRLR 0x810\n+#define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* P10 */\n #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11)\n #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12)\n #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13)\ndiff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h\nindex fa77de7c0e6b..f5294001d3f7 100644\n--- a/include/hw/ppc/xive.h\n+++ b/include/hw/ppc/xive.h\n@@ -176,6 +176,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XiveSource, XIVE_SOURCE)\n */\n #define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */\n #define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */\n+#define XIVE_SRC_PQ_DISABLE 0x4 /* Disable check on the PQ state bits */\n \n struct XiveSource {\n DeviceState parent;\ndiff --git a/hw/intc/xive.c b/hw/intc/xive.c\nindex 6771f6b1d2ae..3a04dc803176 100644\n--- a/hw/intc/xive.c\n+++ b/hw/intc/xive.c\n@@ -886,6 +886,16 @@ static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno)\n }\n }\n \n+/*\n+ * Sources can be configured with PQ offloading in which case the check\n+ * on the PQ state bits of MSIs is disabled\n+ */\n+static bool xive_source_esb_disabled(XiveSource *xsrc, uint32_t srcno)\n+{\n+ return (xsrc->esb_flags & XIVE_SRC_PQ_DISABLE) &&\n+ !xive_source_irq_is_lsi(xsrc, srcno);\n+}\n+\n /*\n * Returns whether the event notification should be forwarded.\n */\n@@ -895,6 +905,10 @@ static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno)\n \n assert(srcno < xsrc->nr_irqs);\n \n+ if (xive_source_esb_disabled(xsrc, srcno)) {\n+ return true;\n+ }\n+\n ret = xive_esb_trigger(&xsrc->status[srcno]);\n \n if (xive_source_irq_is_lsi(xsrc, srcno) &&\n@@ -915,6 +929,11 @@ static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno)\n \n assert(srcno < xsrc->nr_irqs);\n \n+ if (xive_source_esb_disabled(xsrc, srcno)) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: invalid EOI for IRQ %d\\n\", srcno);\n+ return false;\n+ }\n+\n ret = xive_esb_eoi(&xsrc->status[srcno]);\n \n /*\n@@ -936,9 +955,10 @@ static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno)\n static void xive_source_notify(XiveSource *xsrc, int srcno)\n {\n XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive);\n+ bool pq_checked = !xive_source_esb_disabled(xsrc, srcno);\n \n if (xnc->notify) {\n- xnc->notify(xsrc->xive, srcno, true);\n+ xnc->notify(xsrc->xive, srcno, pq_checked);\n }\n }\n \ndiff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c\nindex 3edd5845ebde..cf506d1623c3 100644\n--- a/hw/pci-host/pnv_phb4.c\n+++ b/hw/pci-host/pnv_phb4.c\n@@ -475,6 +475,15 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)\n flags = 0;\n }\n \n+ /*\n+ * When the PQ disable configuration bit is set, the check on the\n+ * PQ state bits is disabled on the PHB side (for MSI only) and it\n+ * is performed on the IC side instead.\n+ */\n+ if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_PQ_DISABLE) {\n+ flags |= XIVE_SRC_PQ_DISABLE;\n+ }\n+\n phb->xsrc.esb_shift = shift;\n phb->xsrc.esb_flags = flags;\n \n", "prefixes": [ "v2", "13/20" ] }