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GET /api/patches/1523753/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 1523753,
    "url": "http://patchwork.ozlabs.org/api/patches/1523753/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-8-clg@kaod.org/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20210902130928.528803-8-clg@kaod.org>",
    "list_archive_url": null,
    "date": "2021-09-02T13:09:15",
    "name": "[v2,07/20] ppc/pnv: Add POWER10 quads",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "9a7ccddb68846ef456b2eacd1ad015ce2a66db7a",
    "submitter": {
        "id": 68548,
        "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api",
        "name": "Cédric Le Goater",
        "email": "clg@kaod.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-8-clg@kaod.org/mbox/",
    "series": [
        {
            "id": 260743,
            "url": "http://patchwork.ozlabs.org/api/series/260743/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=260743",
            "date": "2021-09-02T13:09:11",
            "name": "ppc/pnv: Extend the powernv10 machine",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/260743/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1523753/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1523753/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>",
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            "from kaod.org (37.59.142.101) by DAG4EX1.mxp5.local (172.16.2.31)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Thu, 2 Sep\n 2021 15:09:33 +0200"
        ],
        "X-OVh-ClientIp": "82.64.250.170",
        "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>",
        "To": "David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>",
        "Subject": "[PATCH v2 07/20] ppc/pnv: Add POWER10 quads",
        "Date": "Thu, 2 Sep 2021 15:09:15 +0200",
        "Message-ID": "<20210902130928.528803-8-clg@kaod.org>",
        "X-Mailer": "git-send-email 2.31.1",
        "In-Reply-To": "<20210902130928.528803-1-clg@kaod.org>",
        "References": "<20210902130928.528803-1-clg@kaod.org>",
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        "Cc": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?=\n\t=?utf-8?q?ter?= <clg@kaod.org>",
        "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org",
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    },
    "content": "and use a pnv_chip_power10_quad_realize() helper to avoid code\nduplication with P9. This still needs some refinements on the XSCOM\nregisters handling in PnvQuad.\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n\n v2: rebased on previous changes adding 'quad-id'\n \n include/hw/ppc/pnv.h |  3 +++\n hw/ppc/pnv.c         | 50 +++++++++++++++++++++++++++++++++++---------\n 2 files changed, 43 insertions(+), 10 deletions(-)",
    "diff": "diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h\nindex a299fbc7f25c..13495423283a 100644\n--- a/include/hw/ppc/pnv.h\n+++ b/include/hw/ppc/pnv.h\n@@ -128,6 +128,9 @@ struct Pnv10Chip {\n     Pnv9Psi      psi;\n     PnvLpcController lpc;\n     PnvOCC       occ;\n+\n+    uint32_t     nr_quads;\n+    PnvQuad      *quads;\n };\n \n #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)\ndiff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c\nindex a186df3fee41..5c342e313329 100644\n--- a/hw/ppc/pnv.c\n+++ b/hw/ppc/pnv.c\n@@ -1370,6 +1370,21 @@ static void pnv_chip_power9_instance_init(Object *obj)\n     chip->num_phbs = pcc->num_phbs;\n }\n \n+static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,\n+                                      PnvCore *pnv_core)\n+{\n+    char eq_name[32];\n+    int core_id = CPU_CORE(pnv_core)->core_id;\n+\n+    snprintf(eq_name, sizeof(eq_name), \"eq[%d]\", core_id);\n+    object_initialize_child_with_props(OBJECT(chip), eq_name, eq,\n+                                       sizeof(*eq), TYPE_PNV_QUAD,\n+                                       &error_fatal, NULL);\n+\n+    object_property_set_int(OBJECT(eq), \"quad-id\", core_id, &error_fatal);\n+    qdev_realize(DEVICE(eq), NULL, &error_fatal);\n+}\n+\n static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)\n {\n     PnvChip *chip = PNV_CHIP(chip9);\n@@ -1379,18 +1394,9 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)\n     chip9->quads = g_new0(PnvQuad, chip9->nr_quads);\n \n     for (i = 0; i < chip9->nr_quads; i++) {\n-        char eq_name[32];\n         PnvQuad *eq = &chip9->quads[i];\n-        PnvCore *pnv_core = chip->cores[i * 4];\n-        int core_id = CPU_CORE(pnv_core)->core_id;\n-\n-        snprintf(eq_name, sizeof(eq_name), \"eq[%d]\", core_id);\n-        object_initialize_child_with_props(OBJECT(chip), eq_name, eq,\n-                                           sizeof(*eq), TYPE_PNV_QUAD,\n-                                           &error_fatal, NULL);\n \n-        object_property_set_int(OBJECT(eq), \"quad-id\", core_id, &error_fatal);\n-        qdev_realize(DEVICE(eq), NULL, &error_fatal);\n+        pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);\n \n         pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),\n                                 &eq->xscom_regs);\n@@ -1606,6 +1612,24 @@ static void pnv_chip_power10_instance_init(Object *obj)\n     object_initialize_child(obj, \"occ\",  &chip10->occ, TYPE_PNV10_OCC);\n }\n \n+static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)\n+{\n+    PnvChip *chip = PNV_CHIP(chip10);\n+    int i;\n+\n+    chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);\n+    chip10->quads = g_new0(PnvQuad, chip10->nr_quads);\n+\n+    for (i = 0; i < chip10->nr_quads; i++) {\n+        PnvQuad *eq = &chip10->quads[i];\n+\n+        pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);\n+\n+        pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),\n+                                &eq->xscom_regs);\n+    }\n+}\n+\n static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)\n {\n     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);\n@@ -1627,6 +1651,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)\n         return;\n     }\n \n+    pnv_chip_power10_quad_realize(chip10, &local_err);\n+    if (local_err) {\n+        error_propagate(errp, local_err);\n+        return;\n+    }\n+\n     /* XIVE2 interrupt controller (POWER10) */\n     object_property_set_int(OBJECT(&chip10->xive), \"ic-bar\",\n                             PNV10_XIVE2_IC_BASE(chip), &error_fatal);\n",
    "prefixes": [
        "v2",
        "07/20"
    ]
}