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GET /api/patches/1523752/?format=api
{ "id": 1523752, "url": "http://patchwork.ozlabs.org/api/patches/1523752/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-9-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210902130928.528803-9-clg@kaod.org>", "list_archive_url": null, "date": "2021-09-02T13:09:16", "name": "[v2,08/20] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5b3b5ce866eeb95e081b7300403cd7ae67da9898", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-9-clg@kaod.org/mbox/", "series": [ { "id": 260743, "url": "http://patchwork.ozlabs.org/api/series/260743/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=260743", "date": "2021-09-02T13:09:11", "name": "ppc/pnv: Extend the powernv10 machine", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/260743/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1523752/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1523752/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "garm.ovh; auth=pass\n (GARM-101G0045b3f654d-51ea-4890-9672-0d5bbd5ae2ca,\n 0F69C8711EE098B745CC44F7BEC1CAFBB1DDDEDC) smtp.auth=clg@kaod.org" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4H0hTF3p5Kz9tD5\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 2 Sep 2021 23:23:45 +1000 (AEST)", "from localhost ([::1]:32800 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1mLmgw-0005Kl-B5\n\tfor incoming@patchwork.ozlabs.org; Thu, 02 Sep 2021 09:23:43 -0400", "from eggs.gnu.org ([2001:470:142:3::10]:42868)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTd-0006k0-QN\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:09:57 -0400", "from 3.mo52.mail-out.ovh.net ([178.33.254.192]:51955)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTR-0001w2-C3\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:09:57 -0400", "from mxplan5.mail.ovh.net (unknown [10.109.156.48])\n by mo52.mail-out.ovh.net (Postfix) with ESMTPS id 20C7C295EFC;\n Thu, 2 Sep 2021 15:09:36 +0200 (CEST)", "from kaod.org (37.59.142.101) by DAG4EX1.mxp5.local (172.16.2.31)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Thu, 2 Sep\n 2021 15:09:34 +0200" ], "X-OVh-ClientIp": "82.64.250.170", "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>", "Subject": "[PATCH v2 08/20] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge", "Date": "Thu, 2 Sep 2021 15:09:16 +0200", "Message-ID": "<20210902130928.528803-9-clg@kaod.org>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20210902130928.528803-1-clg@kaod.org>", "References": "<20210902130928.528803-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[37.59.142.101]", "X-ClientProxiedBy": "DAG5EX1.mxp5.local (172.16.2.41) To DAG4EX1.mxp5.local\n (172.16.2.31)", "X-Ovh-Tracer-GUID": "531ebff2-a99d-46ac-b0d4-3fba5d9b3302", "X-Ovh-Tracer-Id": "14775747428397845411", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "\n gggruggvucftvghtrhhoucdtuddrgedvtddruddvhedgiedtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrddutddunecuvehluhhsthgvrhfuihiivgepieenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopegtlhhgsehkrghougdrohhrgh", "Received-SPF": "pass client-ip=178.33.254.192; envelope-from=clg@kaod.org;\n helo=3.mo52.mail-out.ovh.net", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?=\n\t=?utf-8?q?ter?= <clg@kaod.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "PHB4 and PHB5 are very similar. Use the PHB4 models with some minor\nadjustements in a subclass for P10.\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n include/hw/pci-host/pnv_phb4.h | 11 ++++\n include/hw/ppc/pnv.h | 3 ++\n include/hw/ppc/pnv_xscom.h | 6 +++\n hw/pci-host/pnv_phb4_pec.c | 44 ++++++++++++++++\n hw/ppc/pnv.c | 94 ++++++++++++++++++++++++++++++++++\n 5 files changed, 158 insertions(+)", "diff": "diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h\nindex 27556ae53425..78ae74349299 100644\n--- a/include/hw/pci-host/pnv_phb4.h\n+++ b/include/hw/pci-host/pnv_phb4.h\n@@ -221,4 +221,15 @@ struct PnvPhb4PecClass {\n int stk_compat_size;\n };\n \n+/*\n+ * POWER10 definitions\n+ */\n+\n+#define PNV_PHB5_VERSION 0x000000a500000001ull\n+#define PNV_PHB5_DEVICE_ID 0x0652\n+\n+#define TYPE_PNV_PHB5_PEC \"pnv-phb5-pec\"\n+#define PNV_PHB5_PEC(obj) \\\n+ OBJECT_CHECK(PnvPhb4PecState, (obj), TYPE_PNV_PHB5_PEC)\n+\n #endif /* PCI_HOST_PNV_PHB4_H */\ndiff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h\nindex 13495423283a..f44b9947d00e 100644\n--- a/include/hw/ppc/pnv.h\n+++ b/include/hw/ppc/pnv.h\n@@ -131,6 +131,9 @@ struct Pnv10Chip {\n \n uint32_t nr_quads;\n PnvQuad *quads;\n+\n+#define PNV10_CHIP_MAX_PEC 2\n+ PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];\n };\n \n #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)\ndiff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h\nindex 151df15378d1..75db33d46af6 100644\n--- a/include/hw/ppc/pnv_xscom.h\n+++ b/include/hw/ppc/pnv_xscom.h\n@@ -137,6 +137,12 @@ struct PnvXScomInterfaceClass {\n #define PNV10_XSCOM_XIVE2_BASE 0x2010800\n #define PNV10_XSCOM_XIVE2_SIZE 0x400\n \n+#define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */\n+#define PNV10_XSCOM_PEC_NEST_SIZE 0x100\n+\n+#define PNV10_XSCOM_PEC_PCI_BASE 0x8010800 /* index goes upwards ... */\n+#define PNV10_XSCOM_PEC_PCI_SIZE 0x200\n+\n void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);\n int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,\n uint64_t xscom_base, uint64_t xscom_size,\ndiff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c\nindex 741ddc90ed8d..ab13311ef4c7 100644\n--- a/hw/pci-host/pnv_phb4_pec.c\n+++ b/hw/pci-host/pnv_phb4_pec.c\n@@ -584,9 +584,53 @@ static const TypeInfo pnv_pec_stk_type_info = {\n }\n };\n \n+/*\n+ * POWER10 definitions\n+ */\n+\n+static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)\n+{\n+ return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;\n+}\n+\n+static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)\n+{\n+ /* index goes down ... */\n+ return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index;\n+}\n+\n+static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)\n+{\n+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);\n+ static const char compat[] = \"ibm,power10-pbcq\";\n+ static const char stk_compat[] = \"ibm,power10-phb-stack\";\n+\n+ pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;\n+ pecc->xscom_pci_base = pnv_phb5_pec_xscom_pci_base;\n+ pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;\n+ pecc->xscom_pci_size = PNV10_XSCOM_PEC_PCI_SIZE;\n+ pecc->compat = compat;\n+ pecc->compat_size = sizeof(compat);\n+ pecc->stk_compat = stk_compat;\n+ pecc->stk_compat_size = sizeof(stk_compat);\n+}\n+\n+static const TypeInfo pnv_phb5_pec_type_info = {\n+ .name = TYPE_PNV_PHB5_PEC,\n+ .parent = TYPE_PNV_PHB4_PEC,\n+ .instance_size = sizeof(PnvPhb4PecState),\n+ .class_init = pnv_phb5_pec_class_init,\n+ .class_size = sizeof(PnvPhb4PecClass),\n+ .interfaces = (InterfaceInfo[]) {\n+ { TYPE_PNV_XSCOM_INTERFACE },\n+ { }\n+ }\n+};\n+\n static void pnv_pec_register_types(void)\n {\n type_register_static(&pnv_pec_type_info);\n+ type_register_static(&pnv_phb5_pec_type_info);\n type_register_static(&pnv_pec_stk_type_info);\n }\n \ndiff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c\nindex 5c342e313329..0de3027b7122 100644\n--- a/hw/ppc/pnv.c\n+++ b/hw/ppc/pnv.c\n@@ -706,9 +706,17 @@ static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)\n static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)\n {\n Pnv10Chip *chip10 = PNV10_CHIP(chip);\n+ int i, j;\n \n pnv_xive2_pic_print_info(&chip10->xive, mon);\n pnv_psi_pic_print_info(&chip10->psi, mon);\n+\n+ for (i = 0; i < PNV10_CHIP_MAX_PEC; i++) {\n+ PnvPhb4PecState *pec = &chip10->pecs[i];\n+ for (j = 0; j < pec->num_stacks; j++) {\n+ pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon);\n+ }\n+ }\n }\n \n /* Always give the first 1GB to chip 0 else we won't boot */\n@@ -1602,7 +1610,10 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)\n \n static void pnv_chip_power10_instance_init(Object *obj)\n {\n+ PnvChip *chip = PNV_CHIP(obj);\n Pnv10Chip *chip10 = PNV10_CHIP(obj);\n+ PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);\n+ int i;\n \n object_initialize_child(obj, \"xive\", &chip10->xive, TYPE_PNV_XIVE2);\n object_property_add_alias(obj, \"xive-fabric\", OBJECT(&chip10->xive),\n@@ -1610,6 +1621,16 @@ static void pnv_chip_power10_instance_init(Object *obj)\n object_initialize_child(obj, \"psi\", &chip10->psi, TYPE_PNV10_PSI);\n object_initialize_child(obj, \"lpc\", &chip10->lpc, TYPE_PNV10_LPC);\n object_initialize_child(obj, \"occ\", &chip10->occ, TYPE_PNV10_OCC);\n+\n+ for (i = 0; i < PNV10_CHIP_MAX_PEC; i++) {\n+ object_initialize_child(obj, \"pec[*]\", &chip10->pecs[i],\n+ TYPE_PNV_PHB5_PEC);\n+ }\n+\n+ /*\n+ * Number of PHBs is the chip default\n+ */\n+ chip->num_phbs = pcc->num_phbs;\n }\n \n static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)\n@@ -1630,6 +1651,71 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)\n }\n }\n \n+static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp)\n+{\n+ Pnv10Chip *chip10 = PNV10_CHIP(chip);\n+ int i, j;\n+ int phb_id = 0;\n+\n+ for (i = 0; i < PNV10_CHIP_MAX_PEC; i++) {\n+ PnvPhb4PecState *pec = &chip10->pecs[i];\n+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);\n+ uint32_t pec_nest_base;\n+ uint32_t pec_pci_base;\n+\n+ object_property_set_int(OBJECT(pec), \"index\", i, &error_fatal);\n+ /*\n+ * PEC0 -> 3 stacks\n+ * PEC1 -> 3 stacks\n+ */\n+ object_property_set_int(OBJECT(pec), \"num-stacks\", 3,\n+ &error_fatal);\n+ object_property_set_int(OBJECT(pec), \"chip-id\", chip->chip_id,\n+ &error_fatal);\n+ object_property_set_link(OBJECT(pec), \"system-memory\",\n+ OBJECT(get_system_memory()), &error_abort);\n+ if (!qdev_realize(DEVICE(pec), NULL, errp)) {\n+ return;\n+ }\n+\n+ pec_nest_base = pecc->xscom_nest_base(pec);\n+ pec_pci_base = pecc->xscom_pci_base(pec);\n+\n+ pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);\n+ pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);\n+\n+ for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs;\n+ j++, phb_id++) {\n+ PnvPhb4PecStack *stack = &pec->stacks[j];\n+ Object *obj = OBJECT(&stack->phb);\n+\n+ object_property_set_int(obj, \"index\", phb_id, &error_fatal);\n+ object_property_set_int(obj, \"chip-id\", chip->chip_id,\n+ &error_fatal);\n+ object_property_set_int(obj, \"version\", PNV_PHB5_VERSION,\n+ &error_fatal);\n+ object_property_set_int(obj, \"device-id\", PNV_PHB5_DEVICE_ID,\n+ &error_fatal);\n+ object_property_set_link(obj, \"stack\", OBJECT(stack), &error_abort);\n+ if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) {\n+ return;\n+ }\n+\n+ /* Populate the XSCOM address space. */\n+ pnv_xscom_add_subregion(chip,\n+ pec_nest_base + 0x40 * (stack->stack_no + 1),\n+ &stack->nest_regs_mr);\n+ pnv_xscom_add_subregion(chip,\n+ pec_pci_base + 0x40 * (stack->stack_no + 1),\n+ &stack->pci_regs_mr);\n+ pnv_xscom_add_subregion(chip,\n+ pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 +\n+ 0x40 * stack->stack_no,\n+ &stack->phb_regs_mr);\n+ }\n+ }\n+}\n+\n static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)\n {\n PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);\n@@ -1708,6 +1794,13 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)\n }\n pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,\n &chip10->occ.xscom_regs);\n+\n+ /* PHBs */\n+ pnv_chip_power10_phb_realize(chip, &local_err);\n+ if (local_err) {\n+ error_propagate(errp, local_err);\n+ return;\n+ }\n }\n \n static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)\n@@ -1734,6 +1827,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)\n k->xscom_core_base = pnv_chip_power10_xscom_core_base;\n k->xscom_pcba = pnv_chip_power10_xscom_pcba;\n dc->desc = \"PowerNV Chip POWER10\";\n+ k->num_phbs = 6;\n \n device_class_set_parent_realize(dc, pnv_chip_power10_realize,\n &k->parent_realize);\n", "prefixes": [ "v2", "08/20" ] }