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GET /api/patches/1523748/?format=api
{ "id": 1523748, "url": "http://patchwork.ozlabs.org/api/patches/1523748/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-11-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210902130928.528803-11-clg@kaod.org>", "list_archive_url": null, "date": "2021-09-02T13:09:18", "name": "[v2,10/20] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10)", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6b734071653d0f7e6bdb6103860f0548babc55bf", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210902130928.528803-11-clg@kaod.org/mbox/", "series": [ { "id": 260743, "url": "http://patchwork.ozlabs.org/api/series/260743/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=260743", "date": "2021-09-02T13:09:11", "name": "ppc/pnv: Extend the powernv10 machine", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/260743/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1523748/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1523748/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "garm.ovh; auth=pass\n (GARM-101G00457a177c4-43cd-4e42-98fc-8950b037ea46,\n 0F69C8711EE098B745CC44F7BEC1CAFBB1DDDEDC) smtp.auth=clg@kaod.org" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4H0hM13jxNz9sCD\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 2 Sep 2021 23:18:21 +1000 (AEST)", "from localhost ([::1]:45282 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1mLmbj-0003BT-AI\n\tfor incoming@patchwork.ozlabs.org; Thu, 02 Sep 2021 09:18:19 -0400", "from eggs.gnu.org ([2001:470:142:3::10]:42602)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTT-00068d-5e\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:09:47 -0400", "from 6.mo52.mail-out.ovh.net ([188.165.49.222]:39496)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <clg@kaod.org>) id 1mLmTM-0001xb-LM\n for qemu-devel@nongnu.org; Thu, 02 Sep 2021 09:09:46 -0400", "from mxplan5.mail.ovh.net (unknown [10.109.156.48])\n by mo52.mail-out.ovh.net (Postfix) with ESMTPS id 03D11295EEF;\n Thu, 2 Sep 2021 15:09:38 +0200 (CEST)", "from kaod.org (37.59.142.101) by DAG4EX1.mxp5.local (172.16.2.31)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Thu, 2 Sep\n 2021 15:09:34 +0200" ], "X-OVh-ClientIp": "82.64.250.170", "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>", "Subject": "[PATCH v2 10/20] ppc/psi: Add support for StoreEOI and 64k ESB pages\n (POWER10)", "Date": "Thu, 2 Sep 2021 15:09:18 +0200", "Message-ID": "<20210902130928.528803-11-clg@kaod.org>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20210902130928.528803-1-clg@kaod.org>", "References": "<20210902130928.528803-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[37.59.142.101]", "X-ClientProxiedBy": "DAG5EX1.mxp5.local (172.16.2.41) To DAG4EX1.mxp5.local\n (172.16.2.31)", "X-Ovh-Tracer-GUID": "0c2aa849-222b-4e77-809a-02dc47909bc7", "X-Ovh-Tracer-Id": "14776028903275006883", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "\n gggruggvucftvghtrhhoucdtuddrgedvtddruddvhedgieduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfhisehtkeertdertdejnecuhfhrohhmpeevrogurhhitgcunfgvucfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepheehfeegjeeitdfffeetjeduveejueefuefgtdefueelueetveeliefhhffgtdelnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrddutddunecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopegtlhhgsehkrghougdrohhrgh", "Received-SPF": "pass client-ip=188.165.49.222; envelope-from=clg@kaod.org;\n helo=6.mo52.mail-out.ovh.net", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?=\n\t=?utf-8?q?ter?= <clg@kaod.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "POWER10 adds support for StoreEOI operation and 64K ESB pages on PSIHB\nto be consistent with the other interrupt sources of the system.\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n hw/ppc/pnv.c | 6 ++++++\n hw/ppc/pnv_psi.c | 30 ++++++++++++++++++++++++------\n 2 files changed, 30 insertions(+), 6 deletions(-)", "diff": "diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c\nindex d510d2e1d917..96c908c753cb 100644\n--- a/hw/ppc/pnv.c\n+++ b/hw/ppc/pnv.c\n@@ -1526,6 +1526,9 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)\n /* Processor Service Interface (PSI) Host Bridge */\n object_property_set_int(OBJECT(&chip9->psi), \"bar\", PNV9_PSIHB_BASE(chip),\n &error_fatal);\n+ /* This is the only device with 4k ESB pages */\n+ object_property_set_int(OBJECT(&chip9->psi), \"shift\", XIVE_ESB_4K,\n+ &error_fatal);\n if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {\n return;\n }\n@@ -1768,6 +1771,9 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)\n /* Processor Service Interface (PSI) Host Bridge */\n object_property_set_int(OBJECT(&chip10->psi), \"bar\",\n PNV10_PSIHB_BASE(chip), &error_fatal);\n+ /* PSI can now be configured to use 64k ESB pages on POWER10 */\n+ object_property_set_int(OBJECT(&chip10->psi), \"shift\", XIVE_ESB_64K,\n+ &error_fatal);\n if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {\n return;\n }\ndiff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c\nindex cd9a2c5952a6..737486046d5a 100644\n--- a/hw/ppc/pnv_psi.c\n+++ b/hw/ppc/pnv_psi.c\n@@ -601,7 +601,6 @@ static const TypeInfo pnv_psi_power8_info = {\n #define PSIHB9_IRQ_METHOD PPC_BIT(0)\n #define PSIHB9_IRQ_RESET PPC_BIT(1)\n #define PSIHB9_ESB_CI_BASE 0x60\n-#define PSIHB9_ESB_CI_64K PPC_BIT(1)\n #define PSIHB9_ESB_CI_ADDR_MASK PPC_BITMASK(8, 47)\n #define PSIHB9_ESB_CI_VALID PPC_BIT(63)\n #define PSIHB9_ESB_NOTIF_ADDR 0x68\n@@ -646,6 +645,14 @@ static const TypeInfo pnv_psi_power8_info = {\n #define PSIHB9_IRQ_STAT_DIO PPC_BIT(12)\n #define PSIHB9_IRQ_STAT_PSU PPC_BIT(13)\n \n+/* P10 register extensions */\n+\n+#define PSIHB10_CR PSIHB9_CR\n+#define PSIHB10_CR_STORE_EOI PPC_BIT(12)\n+\n+#define PSIHB10_ESB_CI_BASE PSIHB9_ESB_CI_BASE\n+#define PSIHB10_ESB_CI_64K PPC_BIT(1)\n+\n static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)\n {\n PnvPsi *psi = PNV_PSI(xf);\n@@ -704,6 +711,13 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,\n \n switch (addr) {\n case PSIHB9_CR:\n+ if (val & PSIHB10_CR_STORE_EOI) {\n+ psi9->source.esb_flags |= XIVE_SRC_STORE_EOI;\n+ } else {\n+ psi9->source.esb_flags &= ~XIVE_SRC_STORE_EOI;\n+ }\n+ break;\n+\n case PSIHB9_SEMR:\n /* FSP stuff */\n break;\n@@ -715,15 +729,20 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,\n break;\n \n case PSIHB9_ESB_CI_BASE:\n+ if (val & PSIHB10_ESB_CI_64K) {\n+ psi9->source.esb_shift = XIVE_ESB_64K;\n+ } else {\n+ psi9->source.esb_shift = XIVE_ESB_4K;\n+ }\n if (!(val & PSIHB9_ESB_CI_VALID)) {\n if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) {\n memory_region_del_subregion(sysmem, &psi9->source.esb_mmio);\n }\n } else {\n if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) {\n- memory_region_add_subregion(sysmem,\n- val & ~PSIHB9_ESB_CI_VALID,\n- &psi9->source.esb_mmio);\n+ hwaddr addr = val & ~(PSIHB9_ESB_CI_VALID | PSIHB10_ESB_CI_64K);\n+ memory_region_add_subregion(sysmem, addr,\n+ &psi9->source.esb_mmio);\n }\n }\n psi->regs[reg] = val;\n@@ -831,6 +850,7 @@ static void pnv_psi_power9_instance_init(Object *obj)\n Pnv9Psi *psi = PNV9_PSI(obj);\n \n object_initialize_child(obj, \"source\", &psi->source, TYPE_XIVE_SOURCE);\n+ object_property_add_alias(obj, \"shift\", OBJECT(&psi->source), \"shift\");\n }\n \n static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)\n@@ -839,8 +859,6 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)\n XiveSource *xsrc = &PNV9_PSI(psi)->source;\n int i;\n \n- /* This is the only device with 4k ESB pages */\n- object_property_set_int(OBJECT(xsrc), \"shift\", XIVE_ESB_4K, &error_fatal);\n object_property_set_int(OBJECT(xsrc), \"nr-irqs\", PSIHB9_NUM_IRQS,\n &error_fatal);\n object_property_set_link(OBJECT(xsrc), \"xive\", OBJECT(psi), &error_abort);\n", "prefixes": [ "v2", "10/20" ] }