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GET /api/patches/1483909/?format=api
{ "id": 1483909, "url": "http://patchwork.ozlabs.org/api/patches/1483909/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/patch/1622011927-359-8-git-send-email-hsin-hsiung.wang@mediatek.com/", "project": { "id": 9, "url": "http://patchwork.ozlabs.org/api/projects/9/?format=api", "name": "Linux RTC development", "link_name": "rtc-linux", "list_id": "linux-rtc.vger.kernel.org", "list_email": "linux-rtc@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1622011927-359-8-git-send-email-hsin-hsiung.wang@mediatek.com>", "list_archive_url": null, "date": "2021-05-26T06:52:06", "name": "[v8,7/8] regulator: mt6359: Add support for MT6359P regulator", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "1ed6d0549b5f7e07f75670142dd27a625ec1643c", "submitter": { "id": 74946, "url": "http://patchwork.ozlabs.org/api/people/74946/?format=api", "name": "Hsin-Hsiung Wang", "email": "hsin-hsiung.wang@mediatek.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/rtc-linux/patch/1622011927-359-8-git-send-email-hsin-hsiung.wang@mediatek.com/mbox/", "series": [ { "id": 245778, "url": "http://patchwork.ozlabs.org/api/series/245778/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/list/?series=245778", "date": "2021-05-26T06:52:02", "name": "Add Support for MediaTek PMIC MT6359", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/245778/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1483909/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1483909/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-rtc-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=23.128.96.18; helo=vger.kernel.org;\n envelope-from=linux-rtc-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [23.128.96.18])\n\tby ozlabs.org (Postfix) with ESMTP id 4FqhTM70lMz9sW6\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 26 May 2021 16:52:23 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S232952AbhEZGxw (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n Wed, 26 May 2021 02:53:52 -0400", "from mailgw02.mediatek.com ([210.61.82.184]:40870 \"EHLO\n mailgw02.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org\n with ESMTP id S232876AbhEZGxt (ORCPT\n <rfc822;linux-rtc@vger.kernel.org>); Wed, 26 May 2021 02:53:49 -0400", "from mtkexhb01.mediatek.inc [(172.21.101.102)] by\n mailgw02.mediatek.com\n (envelope-from <hsin-hsiung.wang@mediatek.com>)\n (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256)\n with ESMTP id 468669468; Wed, 26 May 2021 14:52:14 +0800", "from mtkcas11.mediatek.inc (172.21.101.40) by\n mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Wed, 26 May 2021 14:52:13 +0800", "from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas11.mediatek.inc\n (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 26 May 2021 14:52:12 +0800" ], "X-UUID": [ "18561a817558451487531c56c06e65d9-20210526", "18561a817558451487531c56c06e65d9-20210526" ], "From": "Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>", "To": "Lee Jones <lee.jones@linaro.org>, Rob Herring <robh+dt@kernel.org>,\n Matthias Brugger <matthias.bgg@gmail.com>,\n Liam Girdwood <lgirdwood@gmail.com>,\n Mark Brown <broonie@kernel.org>,\n Eddie Huang <eddie.huang@mediatek.com>,\n Alessandro Zummo <a.zummo@towertech.it>,\n Alexandre Belloni <alexandre.belloni@bootlin.com>,\n Fei Shao <fshao@chromium.org>", "CC": "Sean Wang <sean.wang@mediatek.com>,\n Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>,\n Yuchen Huang <yuchen.huang@mediatek.com>,\n <devicetree@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>,\n <linux-mediatek@lists.infradead.org>,\n <linux-kernel@vger.kernel.org>, <linux-rtc@vger.kernel.org>,\n <srv_heupstream@mediatek.com>,\n <Project_Global_Chrome_Upstream_Group@mediatek.com>", "Subject": "[PATCH v8 7/8] regulator: mt6359: Add support for MT6359P regulator", "Date": "Wed, 26 May 2021 14:52:06 +0800", "Message-ID": "<1622011927-359-8-git-send-email-hsin-hsiung.wang@mediatek.com>", "X-Mailer": "git-send-email 2.6.4", "In-Reply-To": "<1622011927-359-1-git-send-email-hsin-hsiung.wang@mediatek.com>", "References": "<1622011927-359-1-git-send-email-hsin-hsiung.wang@mediatek.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MTK": "N", "Precedence": "bulk", "List-ID": "<linux-rtc.vger.kernel.org>", "X-Mailing-List": "linux-rtc@vger.kernel.org" }, "content": "The MT6359P is a eco version for MT6359 regulator.\nWe add support based on MT6359 regulator driver.\n\nSigned-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>\nAcked-by: Mark Brown <broonie@kernel.org>\n---\nchanges since v7:\n- no change.\n---\n drivers/regulator/mt6359-regulator.c | 379 ++++++++++++++++++++++++++++-\n include/linux/mfd/mt6359p/registers.h | 249 +++++++++++++++++++\n include/linux/regulator/mt6359-regulator.h | 1 +\n 3 files changed, 623 insertions(+), 6 deletions(-)\n create mode 100644 include/linux/mfd/mt6359p/registers.h", "diff": "diff --git a/drivers/regulator/mt6359-regulator.c b/drivers/regulator/mt6359-regulator.c\nindex 994d3f6..4f517c9 100644\n--- a/drivers/regulator/mt6359-regulator.c\n+++ b/drivers/regulator/mt6359-regulator.c\n@@ -4,6 +4,7 @@\n \n #include <linux/platform_device.h>\n #include <linux/mfd/mt6359/registers.h>\n+#include <linux/mfd/mt6359p/registers.h>\n #include <linux/mfd/mt6397/core.h>\n #include <linux/module.h>\n #include <linux/of_device.h>\n@@ -147,6 +148,29 @@ struct mt6359_regulator_info {\n \t.qi = BIT(0),\t\t\t\t\t\\\n }\n \n+#define MT6359P_LDO1(match, _name, _ops, _volt_table,\t\\\n+\t_enable_reg, _enable_mask, _status_reg,\t\t\\\n+\t_vsel_reg, _vsel_mask)\t\t\t\t\\\n+[MT6359_ID_##_name] = {\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\\\n+\t\t.name = #_name,\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\\\n+\t\t.ops = &_ops,\t\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\\\n+\t\t.id = MT6359_ID_##_name,\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\\\n+\t\t.n_voltages = ARRAY_SIZE(_volt_table),\t\\\n+\t\t.volt_table = _volt_table,\t\t\\\n+\t\t.vsel_reg = _vsel_reg,\t\t\t\\\n+\t\t.vsel_mask = _vsel_mask,\t\t\\\n+\t\t.enable_reg = _enable_reg,\t\t\\\n+\t\t.enable_mask = BIT(_enable_mask),\t\\\n+\t},\t\t\t\t\t\t\\\n+\t.status_reg = _status_reg,\t\t\t\\\n+\t.qi = BIT(0),\t\t\t\t\t\\\n+}\n+\n static const struct linear_range mt_volt_range1[] = {\n \tREGULATOR_LINEAR_RANGE(800000, 0, 0x70, 12500),\n };\n@@ -175,6 +199,10 @@ static const struct linear_range mt_volt_range7[] = {\n \tREGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),\n };\n \n+static const struct linear_range mt_volt_range8[] = {\n+\tREGULATOR_LINEAR_RANGE(506250, 0, 0x7f, 6250),\n+};\n+\n static const u32 vsim1_voltages[] = {\n \t0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000,\n };\n@@ -212,6 +240,10 @@ static const u32 vrfck_voltages[] = {\n \t0, 0, 1500000, 0, 0, 0, 0, 1600000, 0, 0, 0, 0, 1700000,\n };\n \n+static const u32 vrfck_voltages_1[] = {\n+\t1240000, 1600000,\n+};\n+\n static const u32 vio28_voltages[] = {\n \t0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 2900000, 3000000, 3100000, 3300000,\n };\n@@ -220,6 +252,11 @@ static const u32 vemc_voltages[] = {\n \t0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2900000, 3000000, 0, 3300000,\n };\n \n+static const u32 vemc_voltages_1[] = {\n+\t0, 0, 0, 0, 0, 0, 0, 0, 2500000, 2800000, 2900000, 3000000, 3100000,\n+\t3300000,\n+};\n+\n static const u32 va12_voltages[] = {\n \t0, 0, 0, 0, 0, 0, 1200000, 1300000,\n };\n@@ -356,6 +393,78 @@ static int mt6359_regulator_set_mode(struct regulator_dev *rdev,\n \treturn ret;\n }\n \n+static int mt6359p_vemc_set_voltage_sel(struct regulator_dev *rdev,\n+\t\t\t\t\tu32 sel)\n+{\n+\tstruct mt6359_regulator_info *info = rdev_get_drvdata(rdev);\n+\tint ret;\n+\tu32 val = 0;\n+\n+\tsel <<= ffs(info->desc.vsel_mask) - 1;\n+\tret = regmap_write(rdev->regmap, MT6359P_TMA_KEY_ADDR, TMA_KEY);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_read(rdev->regmap, MT6359P_VM_MODE_ADDR, &val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tswitch (val) {\n+\tcase 0:\n+\t\t/* If HW trapping is 0, use VEMC_VOSEL_0 */\n+\t\tret = regmap_update_bits(rdev->regmap,\n+\t\t\t\t\t info->desc.vsel_reg,\n+\t\t\t\t\t info->desc.vsel_mask, sel);\n+\t\tbreak;\n+\tcase 1:\n+\t\t/* If HW trapping is 1, use VEMC_VOSEL_1 */\n+\t\tret = regmap_update_bits(rdev->regmap,\n+\t\t\t\t\t info->desc.vsel_reg + 0x2,\n+\t\t\t\t\t info->desc.vsel_mask, sel);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_write(rdev->regmap, MT6359P_TMA_KEY_ADDR, 0);\n+\treturn ret;\n+}\n+\n+static int mt6359p_vemc_get_voltage_sel(struct regulator_dev *rdev)\n+{\n+\tstruct mt6359_regulator_info *info = rdev_get_drvdata(rdev);\n+\tint ret;\n+\tu32 val = 0;\n+\n+\tret = regmap_read(rdev->regmap, MT6359P_VM_MODE_ADDR, &val);\n+\tif (ret)\n+\t\treturn ret;\n+\tswitch (val) {\n+\tcase 0:\n+\t\t/* If HW trapping is 0, use VEMC_VOSEL_0 */\n+\t\tret = regmap_read(rdev->regmap,\n+\t\t\t\t info->desc.vsel_reg, &val);\n+\t\tbreak;\n+\tcase 1:\n+\t\t/* If HW trapping is 1, use VEMC_VOSEL_1 */\n+\t\tret = regmap_read(rdev->regmap,\n+\t\t\t\t info->desc.vsel_reg + 0x2, &val);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tval &= info->desc.vsel_mask;\n+\tval >>= ffs(info->desc.vsel_mask) - 1;\n+\n+\treturn val;\n+}\n+\n static const struct regulator_ops mt6359_volt_range_ops = {\n \t.list_voltage = regulator_list_voltage_linear_range,\n \t.map_voltage = regulator_map_voltage_linear_range,\n@@ -389,6 +498,18 @@ static const struct regulator_ops mt6359_volt_fixed_ops = {\n \t.get_status = mt6359_get_status,\n };\n \n+static const struct regulator_ops mt6359p_vemc_ops = {\n+\t.list_voltage = regulator_list_voltage_table,\n+\t.map_voltage = regulator_map_voltage_iterate,\n+\t.set_voltage_sel = mt6359p_vemc_set_voltage_sel,\n+\t.get_voltage_sel = mt6359p_vemc_get_voltage_sel,\n+\t.set_voltage_time_sel = regulator_set_voltage_time_sel,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.get_status = mt6359_get_status,\n+};\n+\n /* The array is indexed by id(MT6359_ID_XXX) */\n static struct mt6359_regulator_info mt6359_regulators[] = {\n \tMT6359_BUCK(\"buck_vs1\", VS1, 800000, 2200000, 12500, 0,\n@@ -626,21 +747,267 @@ static struct mt6359_regulator_info mt6359_regulators[] = {\n \t\t\t MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT),\n };\n \n+static struct mt6359_regulator_info mt6359p_regulators[] = {\n+\tMT6359_BUCK(\"buck_vs1\", VS1, 800000, 2200000, 12500, 0,\n+\t\t mt_volt_range1, MT6359_RG_BUCK_VS1_EN_ADDR,\n+\t\t MT6359_DA_VS1_EN_ADDR, MT6359_RG_BUCK_VS1_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VS1_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VS1_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT,\n+\t\t MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT),\n+\tMT6359_BUCK(\"buck_vgpu11\", VGPU11, 400000, 1193750, 6250, 0,\n+\t\t mt_volt_range2, MT6359_RG_BUCK_VGPU11_EN_ADDR,\n+\t\t MT6359_DA_VGPU11_EN_ADDR, MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VGPU11_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VGPU11_LP_ADDR,\n+\t\t MT6359_RG_BUCK_VGPU11_LP_SHIFT,\n+\t\t MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT),\n+\tMT6359_BUCK(\"buck_vmodem\", VMODEM, 400000, 1100000, 6250, 0,\n+\t\t mt_volt_range3, MT6359_RG_BUCK_VMODEM_EN_ADDR,\n+\t\t MT6359_DA_VMODEM_EN_ADDR, MT6359_RG_BUCK_VMODEM_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VMODEM_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VMODEM_LP_ADDR,\n+\t\t MT6359_RG_BUCK_VMODEM_LP_SHIFT,\n+\t\t MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT),\n+\tMT6359_BUCK(\"buck_vpu\", VPU, 400000, 1193750, 6250, 0,\n+\t\t mt_volt_range2, MT6359_RG_BUCK_VPU_EN_ADDR,\n+\t\t MT6359_DA_VPU_EN_ADDR, MT6359_RG_BUCK_VPU_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VPU_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VPU_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT,\n+\t\t MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT),\n+\tMT6359_BUCK(\"buck_vcore\", VCORE, 506250, 1300000, 6250, 0,\n+\t\t mt_volt_range8, MT6359_RG_BUCK_VCORE_EN_ADDR,\n+\t\t MT6359_DA_VCORE_EN_ADDR, MT6359P_RG_BUCK_VCORE_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VCORE_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VCORE_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT,\n+\t\t MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT),\n+\tMT6359_BUCK(\"buck_vs2\", VS2, 800000, 1600000, 12500, 0,\n+\t\t mt_volt_range4, MT6359_RG_BUCK_VS2_EN_ADDR,\n+\t\t MT6359_DA_VS2_EN_ADDR, MT6359_RG_BUCK_VS2_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VS2_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VS2_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT,\n+\t\t MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT),\n+\tMT6359_BUCK(\"buck_vpa\", VPA, 500000, 3650000, 50000, 0,\n+\t\t mt_volt_range5, MT6359_RG_BUCK_VPA_EN_ADDR,\n+\t\t MT6359_DA_VPA_EN_ADDR, MT6359_RG_BUCK_VPA_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VPA_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VPA_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT,\n+\t\t MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT),\n+\tMT6359_BUCK(\"buck_vproc2\", VPROC2, 400000, 1193750, 6250, 0,\n+\t\t mt_volt_range2, MT6359_RG_BUCK_VPROC2_EN_ADDR,\n+\t\t MT6359_DA_VPROC2_EN_ADDR, MT6359_RG_BUCK_VPROC2_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VPROC2_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VPROC2_LP_ADDR,\n+\t\t MT6359_RG_BUCK_VPROC2_LP_SHIFT,\n+\t\t MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT),\n+\tMT6359_BUCK(\"buck_vproc1\", VPROC1, 400000, 1193750, 6250, 0,\n+\t\t mt_volt_range2, MT6359_RG_BUCK_VPROC1_EN_ADDR,\n+\t\t MT6359_DA_VPROC1_EN_ADDR, MT6359_RG_BUCK_VPROC1_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VPROC1_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VPROC1_LP_ADDR,\n+\t\t MT6359_RG_BUCK_VPROC1_LP_SHIFT,\n+\t\t MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT),\n+\tMT6359_BUCK(\"buck_vgpu11_sshub\", VGPU11_SSHUB, 400000, 1193750, 6250, 0,\n+\t\t mt_volt_range2, MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR,\n+\t\t MT6359_DA_VGPU11_EN_ADDR,\n+\t\t MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR,\n+\t\t MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK <<\n+\t\t MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VGPU11_LP_ADDR,\n+\t\t MT6359_RG_BUCK_VGPU11_LP_SHIFT,\n+\t\t MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT),\n+\tMT6359_REG_FIXED(\"ldo_vaud18\", VAUD18, MT6359P_RG_LDO_VAUD18_EN_ADDR,\n+\t\t\t MT6359P_DA_VAUD18_B_EN_ADDR, 1800000),\n+\tMT6359_LDO(\"ldo_vsim1\", VSIM1, vsim1_voltages,\n+\t\t MT6359P_RG_LDO_VSIM1_EN_ADDR, MT6359P_RG_LDO_VSIM1_EN_SHIFT,\n+\t\t MT6359P_DA_VSIM1_B_EN_ADDR, MT6359P_RG_VSIM1_VOSEL_ADDR,\n+\t\t MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT,\n+\t\t 480),\n+\tMT6359_LDO(\"ldo_vibr\", VIBR, vibr_voltages,\n+\t\t MT6359P_RG_LDO_VIBR_EN_ADDR, MT6359P_RG_LDO_VIBR_EN_SHIFT,\n+\t\t MT6359P_DA_VIBR_B_EN_ADDR, MT6359P_RG_VIBR_VOSEL_ADDR,\n+\t\t MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT,\n+\t\t 240),\n+\tMT6359_LDO(\"ldo_vrf12\", VRF12, vrf12_voltages,\n+\t\t MT6359P_RG_LDO_VRF12_EN_ADDR, MT6359P_RG_LDO_VRF12_EN_SHIFT,\n+\t\t MT6359P_DA_VRF12_B_EN_ADDR, MT6359P_RG_VRF12_VOSEL_ADDR,\n+\t\t MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT,\n+\t\t 480),\n+\tMT6359_REG_FIXED(\"ldo_vusb\", VUSB, MT6359P_RG_LDO_VUSB_EN_0_ADDR,\n+\t\t\t MT6359P_DA_VUSB_B_EN_ADDR, 3000000),\n+\tMT6359_LDO_LINEAR(\"ldo_vsram_proc2\", VSRAM_PROC2, 500000, 1293750, 6250,\n+\t\t\t 0, mt_volt_range6, MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR,\n+\t\t\t MT6359P_DA_VSRAM_PROC2_B_EN_ADDR,\n+\t\t\t MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK <<\n+\t\t\t MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT),\n+\tMT6359_LDO(\"ldo_vio18\", VIO18, volt18_voltages,\n+\t\t MT6359P_RG_LDO_VIO18_EN_ADDR, MT6359P_RG_LDO_VIO18_EN_SHIFT,\n+\t\t MT6359P_DA_VIO18_B_EN_ADDR, MT6359P_RG_VIO18_VOSEL_ADDR,\n+\t\t MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT,\n+\t\t 960),\n+\tMT6359_LDO(\"ldo_vcamio\", VCAMIO, volt18_voltages,\n+\t\t MT6359P_RG_LDO_VCAMIO_EN_ADDR,\n+\t\t MT6359P_RG_LDO_VCAMIO_EN_SHIFT,\n+\t\t MT6359P_DA_VCAMIO_B_EN_ADDR, MT6359P_RG_VCAMIO_VOSEL_ADDR,\n+\t\t MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT,\n+\t\t 1290),\n+\tMT6359_REG_FIXED(\"ldo_vcn18\", VCN18, MT6359P_RG_LDO_VCN18_EN_ADDR,\n+\t\t\t MT6359P_DA_VCN18_B_EN_ADDR, 1800000),\n+\tMT6359_REG_FIXED(\"ldo_vfe28\", VFE28, MT6359P_RG_LDO_VFE28_EN_ADDR,\n+\t\t\t MT6359P_DA_VFE28_B_EN_ADDR, 2800000),\n+\tMT6359_LDO(\"ldo_vcn13\", VCN13, vcn13_voltages,\n+\t\t MT6359P_RG_LDO_VCN13_EN_ADDR, MT6359P_RG_LDO_VCN13_EN_SHIFT,\n+\t\t MT6359P_DA_VCN13_B_EN_ADDR, MT6359P_RG_VCN13_VOSEL_ADDR,\n+\t\t MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT,\n+\t\t 240),\n+\tMT6359_LDO(\"ldo_vcn33_1_bt\", VCN33_1_BT, vcn33_voltages,\n+\t\t MT6359P_RG_LDO_VCN33_1_EN_0_ADDR,\n+\t\t MT6359_RG_LDO_VCN33_1_EN_0_SHIFT,\n+\t\t MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR,\n+\t\t MT6359_RG_VCN33_1_VOSEL_MASK <<\n+\t\t MT6359_RG_VCN33_1_VOSEL_SHIFT, 240),\n+\tMT6359_LDO(\"ldo_vcn33_1_wifi\", VCN33_1_WIFI, vcn33_voltages,\n+\t\t MT6359P_RG_LDO_VCN33_1_EN_1_ADDR,\n+\t\t MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT,\n+\t\t MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR,\n+\t\t MT6359_RG_VCN33_1_VOSEL_MASK <<\n+\t\t MT6359_RG_VCN33_1_VOSEL_SHIFT, 240),\n+\tMT6359_REG_FIXED(\"ldo_vaux18\", VAUX18, MT6359P_RG_LDO_VAUX18_EN_ADDR,\n+\t\t\t MT6359P_DA_VAUX18_B_EN_ADDR, 1800000),\n+\tMT6359_LDO_LINEAR(\"ldo_vsram_others\", VSRAM_OTHERS, 500000, 1293750,\n+\t\t\t 6250, 0, mt_volt_range6,\n+\t\t\t MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR,\n+\t\t\t MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR,\n+\t\t\t MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK <<\n+\t\t\t MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT),\n+\tMT6359_LDO(\"ldo_vefuse\", VEFUSE, vefuse_voltages,\n+\t\t MT6359P_RG_LDO_VEFUSE_EN_ADDR,\n+\t\t MT6359P_RG_LDO_VEFUSE_EN_SHIFT,\n+\t\t MT6359P_DA_VEFUSE_B_EN_ADDR, MT6359P_RG_VEFUSE_VOSEL_ADDR,\n+\t\t MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT,\n+\t\t 240),\n+\tMT6359_LDO(\"ldo_vxo22\", VXO22, vxo22_voltages,\n+\t\t MT6359P_RG_LDO_VXO22_EN_ADDR, MT6359P_RG_LDO_VXO22_EN_SHIFT,\n+\t\t MT6359P_DA_VXO22_B_EN_ADDR, MT6359P_RG_VXO22_VOSEL_ADDR,\n+\t\t MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT,\n+\t\t 480),\n+\tMT6359_LDO(\"ldo_vrfck_1\", VRFCK, vrfck_voltages_1,\n+\t\t MT6359P_RG_LDO_VRFCK_EN_ADDR, MT6359P_RG_LDO_VRFCK_EN_SHIFT,\n+\t\t MT6359P_DA_VRFCK_B_EN_ADDR, MT6359P_RG_VRFCK_VOSEL_ADDR,\n+\t\t MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT,\n+\t\t 480),\n+\tMT6359_REG_FIXED(\"ldo_vbif28\", VBIF28, MT6359P_RG_LDO_VBIF28_EN_ADDR,\n+\t\t\t MT6359P_DA_VBIF28_B_EN_ADDR, 2800000),\n+\tMT6359_LDO(\"ldo_vio28\", VIO28, vio28_voltages,\n+\t\t MT6359P_RG_LDO_VIO28_EN_ADDR, MT6359P_RG_LDO_VIO28_EN_SHIFT,\n+\t\t MT6359P_DA_VIO28_B_EN_ADDR, MT6359P_RG_VIO28_VOSEL_ADDR,\n+\t\t MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT,\n+\t\t 1920),\n+\tMT6359P_LDO1(\"ldo_vemc_1\", VEMC, mt6359p_vemc_ops, vemc_voltages_1,\n+\t\t MT6359P_RG_LDO_VEMC_EN_ADDR, MT6359P_RG_LDO_VEMC_EN_SHIFT,\n+\t\t MT6359P_DA_VEMC_B_EN_ADDR,\n+\t\t MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR,\n+\t\t MT6359P_RG_LDO_VEMC_VOSEL_0_MASK <<\n+\t\t MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT),\n+\tMT6359_LDO(\"ldo_vcn33_2_bt\", VCN33_2_BT, vcn33_voltages,\n+\t\t MT6359P_RG_LDO_VCN33_2_EN_0_ADDR,\n+\t\t MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT,\n+\t\t MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR,\n+\t\t MT6359_RG_VCN33_2_VOSEL_MASK <<\n+\t\t MT6359_RG_VCN33_2_VOSEL_SHIFT, 240),\n+\tMT6359_LDO(\"ldo_vcn33_2_wifi\", VCN33_2_WIFI, vcn33_voltages,\n+\t\t MT6359P_RG_LDO_VCN33_2_EN_1_ADDR,\n+\t\t MT6359_RG_LDO_VCN33_2_EN_1_SHIFT,\n+\t\t MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR,\n+\t\t MT6359_RG_VCN33_2_VOSEL_MASK <<\n+\t\t MT6359_RG_VCN33_2_VOSEL_SHIFT, 240),\n+\tMT6359_LDO(\"ldo_va12\", VA12, va12_voltages,\n+\t\t MT6359P_RG_LDO_VA12_EN_ADDR, MT6359P_RG_LDO_VA12_EN_SHIFT,\n+\t\t MT6359P_DA_VA12_B_EN_ADDR, MT6359P_RG_VA12_VOSEL_ADDR,\n+\t\t MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT,\n+\t\t 960),\n+\tMT6359_LDO(\"ldo_va09\", VA09, va09_voltages,\n+\t\t MT6359P_RG_LDO_VA09_EN_ADDR, MT6359P_RG_LDO_VA09_EN_SHIFT,\n+\t\t MT6359P_DA_VA09_B_EN_ADDR, MT6359P_RG_VA09_VOSEL_ADDR,\n+\t\t MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT,\n+\t\t 960),\n+\tMT6359_LDO(\"ldo_vrf18\", VRF18, vrf18_voltages,\n+\t\t MT6359P_RG_LDO_VRF18_EN_ADDR, MT6359P_RG_LDO_VRF18_EN_SHIFT,\n+\t\t MT6359P_DA_VRF18_B_EN_ADDR, MT6359P_RG_VRF18_VOSEL_ADDR,\n+\t\t MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT,\n+\t\t 240),\n+\tMT6359_LDO_LINEAR(\"ldo_vsram_md\", VSRAM_MD, 500000, 1293750, 6250,\n+\t\t\t 0, mt_volt_range7, MT6359P_RG_LDO_VSRAM_MD_EN_ADDR,\n+\t\t\t MT6359P_DA_VSRAM_MD_B_EN_ADDR,\n+\t\t\t MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK <<\n+\t\t\t MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT),\n+\tMT6359_LDO(\"ldo_vufs\", VUFS, volt18_voltages,\n+\t\t MT6359P_RG_LDO_VUFS_EN_ADDR, MT6359P_RG_LDO_VUFS_EN_SHIFT,\n+\t\t MT6359P_DA_VUFS_B_EN_ADDR, MT6359P_RG_VUFS_VOSEL_ADDR,\n+\t\t MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT,\n+\t\t 1920),\n+\tMT6359_LDO(\"ldo_vm18\", VM18, volt18_voltages,\n+\t\t MT6359P_RG_LDO_VM18_EN_ADDR, MT6359P_RG_LDO_VM18_EN_SHIFT,\n+\t\t MT6359P_DA_VM18_B_EN_ADDR, MT6359P_RG_VM18_VOSEL_ADDR,\n+\t\t MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT,\n+\t\t 1920),\n+\tMT6359_LDO(\"ldo_vbbck\", VBBCK, vbbck_voltages,\n+\t\t MT6359P_RG_LDO_VBBCK_EN_ADDR, MT6359P_RG_LDO_VBBCK_EN_SHIFT,\n+\t\t MT6359P_DA_VBBCK_B_EN_ADDR, MT6359P_RG_VBBCK_VOSEL_ADDR,\n+\t\t MT6359P_RG_VBBCK_VOSEL_MASK << MT6359P_RG_VBBCK_VOSEL_SHIFT,\n+\t\t 480),\n+\tMT6359_LDO_LINEAR(\"ldo_vsram_proc1\", VSRAM_PROC1, 500000, 1293750, 6250,\n+\t\t\t 0, mt_volt_range6, MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR,\n+\t\t\t MT6359P_DA_VSRAM_PROC1_B_EN_ADDR,\n+\t\t\t MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK <<\n+\t\t\t MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT),\n+\tMT6359_LDO(\"ldo_vsim2\", VSIM2, vsim2_voltages,\n+\t\t MT6359P_RG_LDO_VSIM2_EN_ADDR, MT6359P_RG_LDO_VSIM2_EN_SHIFT,\n+\t\t MT6359P_DA_VSIM2_B_EN_ADDR, MT6359P_RG_VSIM2_VOSEL_ADDR,\n+\t\t MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT,\n+\t\t 480),\n+\tMT6359_LDO_LINEAR(\"ldo_vsram_others_sshub\", VSRAM_OTHERS_SSHUB,\n+\t\t\t 500000, 1293750, 6250, 0, mt_volt_range6,\n+\t\t\t MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR,\n+\t\t\t MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR,\n+\t\t\t MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK <<\n+\t\t\t MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT),\n+};\n+\n static int mt6359_regulator_probe(struct platform_device *pdev)\n {\n \tstruct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);\n \tstruct regulator_config config = {};\n \tstruct regulator_dev *rdev;\n-\tint i;\n+\tstruct mt6359_regulator_info *mt6359_info;\n+\tint i, hw_ver;\n+\n+\tregmap_read(mt6397->regmap, MT6359P_HWCID, &hw_ver);\n+\tif (hw_ver >= MT6359P_CHIP_VER)\n+\t\tmt6359_info = mt6359p_regulators;\n+\telse\n+\t\tmt6359_info = mt6359_regulators;\n \n \tconfig.dev = mt6397->dev;\n \tconfig.regmap = mt6397->regmap;\n-\tfor (i = 0; i < MT6359_MAX_REGULATOR; i++) {\n-\t\tconfig.driver_data = &mt6359_regulators[i];\n-\t\trdev = devm_regulator_register(&pdev->dev, &mt6359_regulators[i].desc, &config);\n+\tfor (i = 0; i < MT6359_MAX_REGULATOR; i++, mt6359_info++) {\n+\t\tconfig.driver_data = mt6359_info;\n+\t\trdev = devm_regulator_register(&pdev->dev, &mt6359_info->desc, &config);\n \t\tif (IS_ERR(rdev)) {\n-\t\t\tdev_err(&pdev->dev, \"failed to register %s\\n\",\n-\t\t\t\tmt6359_regulators[i].desc.name);\n+\t\t\tdev_err(&pdev->dev, \"failed to register %s\\n\", mt6359_info->desc.name);\n \t\t\treturn PTR_ERR(rdev);\n \t\t}\n \t}\ndiff --git a/include/linux/mfd/mt6359p/registers.h b/include/linux/mfd/mt6359p/registers.h\nnew file mode 100644\nindex 0000000..3d97c18\n--- /dev/null\n+++ b/include/linux/mfd/mt6359p/registers.h\n@@ -0,0 +1,249 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2021 MediaTek Inc.\n+ */\n+\n+#ifndef __MFD_MT6359P_REGISTERS_H__\n+#define __MFD_MT6359P_REGISTERS_H__\n+\n+#define MT6359P_CHIP_VER 0x5930\n+\n+/* PMIC Registers */\n+#define MT6359P_HWCID 0x8\n+#define MT6359P_TOP_TRAP 0x50\n+#define MT6359P_TOP_TMA_KEY 0x3a8\n+#define MT6359P_BUCK_VCORE_ELR_NUM 0x152a\n+#define MT6359P_BUCK_VCORE_ELR0 0x152c\n+#define MT6359P_BUCK_VGPU11_SSHUB_CON0 0x15aa\n+#define MT6359P_BUCK_VGPU11_ELR0 0x15b4\n+#define MT6359P_LDO_VSRAM_PROC1_ELR 0x1b44\n+#define MT6359P_LDO_VSRAM_PROC2_ELR 0x1b46\n+#define MT6359P_LDO_VSRAM_OTHERS_ELR 0x1b48\n+#define MT6359P_LDO_VSRAM_MD_ELR 0x1b4a\n+#define MT6359P_LDO_VEMC_ELR_0 0x1b4c\n+#define MT6359P_LDO_VFE28_CON0 0x1b88\n+#define MT6359P_LDO_VFE28_MON 0x1b8c\n+#define MT6359P_LDO_VXO22_CON0 0x1b9a\n+#define MT6359P_LDO_VXO22_MON 0x1b9e\n+#define MT6359P_LDO_VRF18_CON0 0x1bac\n+#define MT6359P_LDO_VRF18_MON 0x1bb0\n+#define MT6359P_LDO_VRF12_CON0 0x1bbe\n+#define MT6359P_LDO_VRF12_MON 0x1bc2\n+#define MT6359P_LDO_VEFUSE_CON0 0x1bd0\n+#define MT6359P_LDO_VEFUSE_MON 0x1bd4\n+#define MT6359P_LDO_VCN33_1_CON0 0x1be2\n+#define MT6359P_LDO_VCN33_1_MON 0x1be6\n+#define MT6359P_LDO_VCN33_1_MULTI_SW 0x1bf4\n+#define MT6359P_LDO_VCN33_2_CON0 0x1c08\n+#define MT6359P_LDO_VCN33_2_MON 0x1c0c\n+#define MT6359P_LDO_VCN33_2_MULTI_SW 0x1c1a\n+#define MT6359P_LDO_VCN13_CON0 0x1c1c\n+#define MT6359P_LDO_VCN13_MON 0x1c20\n+#define MT6359P_LDO_VCN18_CON0 0x1c2e\n+#define MT6359P_LDO_VCN18_MON 0x1c32\n+#define MT6359P_LDO_VA09_CON0 0x1c40\n+#define MT6359P_LDO_VA09_MON 0x1c44\n+#define MT6359P_LDO_VCAMIO_CON0 0x1c52\n+#define MT6359P_LDO_VCAMIO_MON 0x1c56\n+#define MT6359P_LDO_VA12_CON0 0x1c64\n+#define MT6359P_LDO_VA12_MON 0x1c68\n+#define MT6359P_LDO_VAUX18_CON0 0x1c88\n+#define MT6359P_LDO_VAUX18_MON 0x1c8c\n+#define MT6359P_LDO_VAUD18_CON0 0x1c9a\n+#define MT6359P_LDO_VAUD18_MON 0x1c9e\n+#define MT6359P_LDO_VIO18_CON0 0x1cac\n+#define MT6359P_LDO_VIO18_MON 0x1cb0\n+#define MT6359P_LDO_VEMC_CON0 0x1cbe\n+#define MT6359P_LDO_VEMC_MON 0x1cc2\n+#define MT6359P_LDO_VSIM1_CON0 0x1cd0\n+#define MT6359P_LDO_VSIM1_MON 0x1cd4\n+#define MT6359P_LDO_VSIM2_CON0 0x1ce2\n+#define MT6359P_LDO_VSIM2_MON 0x1ce6\n+#define MT6359P_LDO_VUSB_CON0 0x1d08\n+#define MT6359P_LDO_VUSB_MON 0x1d0c\n+#define MT6359P_LDO_VUSB_MULTI_SW 0x1d1a\n+#define MT6359P_LDO_VRFCK_CON0 0x1d1c\n+#define MT6359P_LDO_VRFCK_MON 0x1d20\n+#define MT6359P_LDO_VBBCK_CON0 0x1d2e\n+#define MT6359P_LDO_VBBCK_MON 0x1d32\n+#define MT6359P_LDO_VBIF28_CON0 0x1d40\n+#define MT6359P_LDO_VBIF28_MON 0x1d44\n+#define MT6359P_LDO_VIBR_CON0 0x1d52\n+#define MT6359P_LDO_VIBR_MON 0x1d56\n+#define MT6359P_LDO_VIO28_CON0 0x1d64\n+#define MT6359P_LDO_VIO28_MON 0x1d68\n+#define MT6359P_LDO_VM18_CON0 0x1d88\n+#define MT6359P_LDO_VM18_MON 0x1d8c\n+#define MT6359P_LDO_VUFS_CON0 0x1d9a\n+#define MT6359P_LDO_VUFS_MON 0x1d9e\n+#define MT6359P_LDO_VSRAM_PROC1_CON0 0x1e88\n+#define MT6359P_LDO_VSRAM_PROC1_MON 0x1e8c\n+#define MT6359P_LDO_VSRAM_PROC1_VOSEL1 0x1e90\n+#define MT6359P_LDO_VSRAM_PROC2_CON0 0x1ea8\n+#define MT6359P_LDO_VSRAM_PROC2_MON 0x1eac\n+#define MT6359P_LDO_VSRAM_PROC2_VOSEL1 0x1eb0\n+#define MT6359P_LDO_VSRAM_OTHERS_CON0 0x1f08\n+#define MT6359P_LDO_VSRAM_OTHERS_MON 0x1f0c\n+#define MT6359P_LDO_VSRAM_OTHERS_VOSEL1 0x1f10\n+#define MT6359P_LDO_VSRAM_OTHERS_SSHUB 0x1f28\n+#define MT6359P_LDO_VSRAM_MD_CON0 0x1f2e\n+#define MT6359P_LDO_VSRAM_MD_MON 0x1f32\n+#define MT6359P_LDO_VSRAM_MD_VOSEL1 0x1f36\n+#define MT6359P_VFE28_ANA_CON0 0x1f88\n+#define MT6359P_VAUX18_ANA_CON0 0x1f8c\n+#define MT6359P_VUSB_ANA_CON0 0x1f90\n+#define MT6359P_VBIF28_ANA_CON0 0x1f94\n+#define MT6359P_VCN33_1_ANA_CON0 0x1f98\n+#define MT6359P_VCN33_2_ANA_CON0 0x1f9c\n+#define MT6359P_VEMC_ANA_CON0 0x1fa0\n+#define MT6359P_VSIM1_ANA_CON0 0x1fa2\n+#define MT6359P_VSIM2_ANA_CON0 0x1fa6\n+#define MT6359P_VIO28_ANA_CON0 0x1faa\n+#define MT6359P_VIBR_ANA_CON0 0x1fae\n+#define MT6359P_VFE28_ELR_4 0x1fc0\n+#define MT6359P_VRF18_ANA_CON0 0x2008\n+#define MT6359P_VEFUSE_ANA_CON0 0x200c\n+#define MT6359P_VCN18_ANA_CON0 0x2010\n+#define MT6359P_VCAMIO_ANA_CON0 0x2014\n+#define MT6359P_VAUD18_ANA_CON0 0x2018\n+#define MT6359P_VIO18_ANA_CON0 0x201c\n+#define MT6359P_VM18_ANA_CON0 0x2020\n+#define MT6359P_VUFS_ANA_CON0 0x2024\n+#define MT6359P_VRF12_ANA_CON0 0x202a\n+#define MT6359P_VCN13_ANA_CON0 0x202e\n+#define MT6359P_VA09_ANA_CON0 0x2032\n+#define MT6359P_VRF18_ELR_3 0x204e\n+#define MT6359P_VXO22_ANA_CON0 0x2088\n+#define MT6359P_VRFCK_ANA_CON0 0x208c\n+#define MT6359P_VBBCK_ANA_CON0 0x2096\n+\n+#define MT6359P_RG_BUCK_VCORE_VOSEL_ADDR MT6359P_BUCK_VCORE_ELR0\n+#define MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0\n+#define MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR MT6359P_BUCK_VGPU11_ELR0\n+#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0\n+#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK 0x7F\n+#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT 4\n+#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_ELR\n+#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_ELR\n+#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_ELR\n+#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_ELR\n+#define MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR MT6359P_LDO_VEMC_ELR_0\n+#define MT6359P_RG_LDO_VEMC_VOSEL_0_MASK 0xF\n+#define MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT 0\n+#define MT6359P_RG_LDO_VFE28_EN_ADDR MT6359P_LDO_VFE28_CON0\n+#define MT6359P_DA_VFE28_B_EN_ADDR MT6359P_LDO_VFE28_MON\n+#define MT6359P_RG_LDO_VXO22_EN_ADDR MT6359P_LDO_VXO22_CON0\n+#define MT6359P_RG_LDO_VXO22_EN_SHIFT 0\n+#define MT6359P_DA_VXO22_B_EN_ADDR MT6359P_LDO_VXO22_MON\n+#define MT6359P_RG_LDO_VRF18_EN_ADDR MT6359P_LDO_VRF18_CON0\n+#define MT6359P_RG_LDO_VRF18_EN_SHIFT 0\n+#define MT6359P_DA_VRF18_B_EN_ADDR MT6359P_LDO_VRF18_MON\n+#define MT6359P_RG_LDO_VRF12_EN_ADDR MT6359P_LDO_VRF12_CON0\n+#define MT6359P_RG_LDO_VRF12_EN_SHIFT 0\n+#define MT6359P_DA_VRF12_B_EN_ADDR MT6359P_LDO_VRF12_MON\n+#define MT6359P_RG_LDO_VEFUSE_EN_ADDR MT6359P_LDO_VEFUSE_CON0\n+#define MT6359P_RG_LDO_VEFUSE_EN_SHIFT 0\n+#define MT6359P_DA_VEFUSE_B_EN_ADDR MT6359P_LDO_VEFUSE_MON\n+#define MT6359P_RG_LDO_VCN33_1_EN_0_ADDR MT6359P_LDO_VCN33_1_CON0\n+#define MT6359P_DA_VCN33_1_B_EN_ADDR MT6359P_LDO_VCN33_1_MON\n+#define MT6359P_RG_LDO_VCN33_1_EN_1_ADDR MT6359P_LDO_VCN33_1_MULTI_SW\n+#define MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT 15\n+#define MT6359P_RG_LDO_VCN33_2_EN_0_ADDR MT6359P_LDO_VCN33_2_CON0\n+#define MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT 0\n+#define MT6359P_DA_VCN33_2_B_EN_ADDR MT6359P_LDO_VCN33_2_MON\n+#define MT6359P_RG_LDO_VCN33_2_EN_1_ADDR MT6359P_LDO_VCN33_2_MULTI_SW\n+#define MT6359P_RG_LDO_VCN13_EN_ADDR MT6359P_LDO_VCN13_CON0\n+#define MT6359P_RG_LDO_VCN13_EN_SHIFT 0\n+#define MT6359P_DA_VCN13_B_EN_ADDR MT6359P_LDO_VCN13_MON\n+#define MT6359P_RG_LDO_VCN18_EN_ADDR MT6359P_LDO_VCN18_CON0\n+#define MT6359P_DA_VCN18_B_EN_ADDR MT6359P_LDO_VCN18_MON\n+#define MT6359P_RG_LDO_VA09_EN_ADDR MT6359P_LDO_VA09_CON0\n+#define MT6359P_RG_LDO_VA09_EN_SHIFT 0\n+#define MT6359P_DA_VA09_B_EN_ADDR MT6359P_LDO_VA09_MON\n+#define MT6359P_RG_LDO_VCAMIO_EN_ADDR MT6359P_LDO_VCAMIO_CON0\n+#define MT6359P_RG_LDO_VCAMIO_EN_SHIFT 0\n+#define MT6359P_DA_VCAMIO_B_EN_ADDR MT6359P_LDO_VCAMIO_MON\n+#define MT6359P_RG_LDO_VA12_EN_ADDR MT6359P_LDO_VA12_CON0\n+#define MT6359P_RG_LDO_VA12_EN_SHIFT 0\n+#define MT6359P_DA_VA12_B_EN_ADDR MT6359P_LDO_VA12_MON\n+#define MT6359P_RG_LDO_VAUX18_EN_ADDR MT6359P_LDO_VAUX18_CON0\n+#define MT6359P_DA_VAUX18_B_EN_ADDR MT6359P_LDO_VAUX18_MON\n+#define MT6359P_RG_LDO_VAUD18_EN_ADDR MT6359P_LDO_VAUD18_CON0\n+#define MT6359P_DA_VAUD18_B_EN_ADDR MT6359P_LDO_VAUD18_MON\n+#define MT6359P_RG_LDO_VIO18_EN_ADDR MT6359P_LDO_VIO18_CON0\n+#define MT6359P_RG_LDO_VIO18_EN_SHIFT 0\n+#define MT6359P_DA_VIO18_B_EN_ADDR MT6359P_LDO_VIO18_MON\n+#define MT6359P_RG_LDO_VEMC_EN_ADDR MT6359P_LDO_VEMC_CON0\n+#define MT6359P_RG_LDO_VEMC_EN_SHIFT 0\n+#define MT6359P_DA_VEMC_B_EN_ADDR MT6359P_LDO_VEMC_MON\n+#define MT6359P_RG_LDO_VSIM1_EN_ADDR MT6359P_LDO_VSIM1_CON0\n+#define MT6359P_RG_LDO_VSIM1_EN_SHIFT 0\n+#define MT6359P_DA_VSIM1_B_EN_ADDR MT6359P_LDO_VSIM1_MON\n+#define MT6359P_RG_LDO_VSIM2_EN_ADDR MT6359P_LDO_VSIM2_CON0\n+#define MT6359P_RG_LDO_VSIM2_EN_SHIFT 0\n+#define MT6359P_DA_VSIM2_B_EN_ADDR MT6359P_LDO_VSIM2_MON\n+#define MT6359P_RG_LDO_VUSB_EN_0_ADDR MT6359P_LDO_VUSB_CON0\n+#define MT6359P_DA_VUSB_B_EN_ADDR MT6359P_LDO_VUSB_MON\n+#define MT6359P_RG_LDO_VUSB_EN_1_ADDR MT6359P_LDO_VUSB_MULTI_SW\n+#define MT6359P_RG_LDO_VRFCK_EN_ADDR MT6359P_LDO_VRFCK_CON0\n+#define MT6359P_RG_LDO_VRFCK_EN_SHIFT 0\n+#define MT6359P_DA_VRFCK_B_EN_ADDR MT6359P_LDO_VRFCK_MON\n+#define MT6359P_RG_LDO_VBBCK_EN_ADDR MT6359P_LDO_VBBCK_CON0\n+#define MT6359P_RG_LDO_VBBCK_EN_SHIFT 0\n+#define MT6359P_DA_VBBCK_B_EN_ADDR MT6359P_LDO_VBBCK_MON\n+#define MT6359P_RG_LDO_VBIF28_EN_ADDR MT6359P_LDO_VBIF28_CON0\n+#define MT6359P_DA_VBIF28_B_EN_ADDR MT6359P_LDO_VBIF28_MON\n+#define MT6359P_RG_LDO_VIBR_EN_ADDR MT6359P_LDO_VIBR_CON0\n+#define MT6359P_RG_LDO_VIBR_EN_SHIFT 0\n+#define MT6359P_DA_VIBR_B_EN_ADDR MT6359P_LDO_VIBR_MON\n+#define MT6359P_RG_LDO_VIO28_EN_ADDR MT6359P_LDO_VIO28_CON0\n+#define MT6359P_RG_LDO_VIO28_EN_SHIFT 0\n+#define MT6359P_DA_VIO28_B_EN_ADDR MT6359P_LDO_VIO28_MON\n+#define MT6359P_RG_LDO_VM18_EN_ADDR MT6359P_LDO_VM18_CON0\n+#define MT6359P_RG_LDO_VM18_EN_SHIFT 0\n+#define MT6359P_DA_VM18_B_EN_ADDR MT6359P_LDO_VM18_MON\n+#define MT6359P_RG_LDO_VUFS_EN_ADDR MT6359P_LDO_VUFS_CON0\n+#define MT6359P_RG_LDO_VUFS_EN_SHIFT 0\n+#define MT6359P_DA_VUFS_B_EN_ADDR MT6359P_LDO_VUFS_MON\n+#define MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359P_LDO_VSRAM_PROC1_CON0\n+#define MT6359P_DA_VSRAM_PROC1_B_EN_ADDR MT6359P_LDO_VSRAM_PROC1_MON\n+#define MT6359P_DA_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_VOSEL1\n+#define MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359P_LDO_VSRAM_PROC2_CON0\n+#define MT6359P_DA_VSRAM_PROC2_B_EN_ADDR MT6359P_LDO_VSRAM_PROC2_MON\n+#define MT6359P_DA_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_VOSEL1\n+#define MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_CON0\n+#define MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_MON\n+#define MT6359P_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_VOSEL1\n+#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB\n+#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB\n+#define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR MT6359P_LDO_VSRAM_MD_CON0\n+#define MT6359P_DA_VSRAM_MD_B_EN_ADDR MT6359P_LDO_VSRAM_MD_MON\n+#define MT6359P_DA_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_VOSEL1\n+#define MT6359P_RG_VCN33_1_VOSEL_ADDR MT6359P_VCN33_1_ANA_CON0\n+#define MT6359P_RG_VCN33_2_VOSEL_ADDR MT6359P_VCN33_2_ANA_CON0\n+#define MT6359P_RG_VEMC_VOSEL_ADDR MT6359P_VEMC_ANA_CON0\n+#define MT6359P_RG_VSIM1_VOSEL_ADDR MT6359P_VSIM1_ANA_CON0\n+#define MT6359P_RG_VSIM2_VOSEL_ADDR MT6359P_VSIM2_ANA_CON0\n+#define MT6359P_RG_VIO28_VOSEL_ADDR MT6359P_VIO28_ANA_CON0\n+#define MT6359P_RG_VIBR_VOSEL_ADDR MT6359P_VIBR_ANA_CON0\n+#define MT6359P_RG_VRF18_VOSEL_ADDR MT6359P_VRF18_ANA_CON0\n+#define MT6359P_RG_VEFUSE_VOSEL_ADDR MT6359P_VEFUSE_ANA_CON0\n+#define MT6359P_RG_VCAMIO_VOSEL_ADDR MT6359P_VCAMIO_ANA_CON0\n+#define MT6359P_RG_VIO18_VOSEL_ADDR MT6359P_VIO18_ANA_CON0\n+#define MT6359P_RG_VM18_VOSEL_ADDR MT6359P_VM18_ANA_CON0\n+#define MT6359P_RG_VUFS_VOSEL_ADDR MT6359P_VUFS_ANA_CON0\n+#define MT6359P_RG_VRF12_VOSEL_ADDR MT6359P_VRF12_ANA_CON0\n+#define MT6359P_RG_VCN13_VOSEL_ADDR MT6359P_VCN13_ANA_CON0\n+#define MT6359P_RG_VA09_VOSEL_ADDR MT6359P_VRF18_ELR_3\n+#define MT6359P_RG_VA12_VOSEL_ADDR MT6359P_VFE28_ELR_4\n+#define MT6359P_RG_VXO22_VOSEL_ADDR MT6359P_VXO22_ANA_CON0\n+#define MT6359P_RG_VRFCK_VOSEL_ADDR MT6359P_VRFCK_ANA_CON0\n+#define MT6359P_RG_VBBCK_VOSEL_ADDR MT6359P_VBBCK_ANA_CON0\n+#define MT6359P_RG_VBBCK_VOSEL_MASK 0xF\n+#define MT6359P_RG_VBBCK_VOSEL_SHIFT 4\n+#define MT6359P_VM_MODE_ADDR MT6359P_TOP_TRAP\n+#define MT6359P_TMA_KEY_ADDR MT6359P_TOP_TMA_KEY\n+\n+#define TMA_KEY 0x9CA6\n+\n+#endif /* __MFD_MT6359P_REGISTERS_H__ */\ndiff --git a/include/linux/regulator/mt6359-regulator.h b/include/linux/regulator/mt6359-regulator.h\nindex 14c4b71..6d6e5a5 100644\n--- a/include/linux/regulator/mt6359-regulator.h\n+++ b/include/linux/regulator/mt6359-regulator.h\n@@ -17,6 +17,7 @@ enum {\n \tMT6359_ID_VPROC2,\n \tMT6359_ID_VPROC1,\n \tMT6359_ID_VCORE_SSHUB,\n+\tMT6359_ID_VGPU11_SSHUB = MT6359_ID_VCORE_SSHUB,\n \tMT6359_ID_VAUD18 = 10,\n \tMT6359_ID_VSIM1,\n \tMT6359_ID_VIBR,\n", "prefixes": [ "v8", "7/8" ] }