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GET /api/patches/1483908/?format=api
{ "id": 1483908, "url": "http://patchwork.ozlabs.org/api/patches/1483908/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/patch/1622011927-359-7-git-send-email-hsin-hsiung.wang@mediatek.com/", "project": { "id": 9, "url": "http://patchwork.ozlabs.org/api/projects/9/?format=api", "name": "Linux RTC development", "link_name": "rtc-linux", "list_id": "linux-rtc.vger.kernel.org", "list_email": "linux-rtc@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1622011927-359-7-git-send-email-hsin-hsiung.wang@mediatek.com>", "list_archive_url": null, "date": "2021-05-26T06:52:05", "name": "[v8,6/8] regulator: mt6359: Add support for MT6359 regulator", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "a3662ded7dfd2eeba498b3e0e96fecefbd418658", "submitter": { "id": 74946, "url": "http://patchwork.ozlabs.org/api/people/74946/?format=api", "name": "Hsin-Hsiung Wang", "email": "hsin-hsiung.wang@mediatek.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/rtc-linux/patch/1622011927-359-7-git-send-email-hsin-hsiung.wang@mediatek.com/mbox/", "series": [ { "id": 245778, "url": "http://patchwork.ozlabs.org/api/series/245778/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/list/?series=245778", "date": "2021-05-26T06:52:02", "name": "Add Support for MediaTek PMIC MT6359", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/245778/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1483908/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1483908/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-rtc-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=23.128.96.18; helo=vger.kernel.org;\n envelope-from=linux-rtc-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [23.128.96.18])\n\tby ozlabs.org (Postfix) with ESMTP id 4FqhTM0M5Bz9sRN\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 26 May 2021 16:52:23 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S232943AbhEZGxv (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n Wed, 26 May 2021 02:53:51 -0400", "from mailgw02.mediatek.com ([210.61.82.184]:40893 \"EHLO\n mailgw02.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org\n with ESMTP id S232873AbhEZGxt (ORCPT\n <rfc822;linux-rtc@vger.kernel.org>); Wed, 26 May 2021 02:53:49 -0400", "from mtkcas06.mediatek.inc [(172.21.101.30)] by\n mailgw02.mediatek.com\n (envelope-from <hsin-hsiung.wang@mediatek.com>)\n (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256)\n with ESMTP id 257999154; Wed, 26 May 2021 14:52:14 +0800", "from mtkcas11.mediatek.inc (172.21.101.40) by\n mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Wed, 26 May 2021 14:52:12 +0800", "from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas11.mediatek.inc\n (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 26 May 2021 14:52:12 +0800" ], "X-UUID": [ "090556da3a6f4f33a7697e2547e2cc4c-20210526", "090556da3a6f4f33a7697e2547e2cc4c-20210526" ], "From": "Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>", "To": "Lee Jones <lee.jones@linaro.org>, Rob Herring <robh+dt@kernel.org>,\n Matthias Brugger <matthias.bgg@gmail.com>,\n Liam Girdwood <lgirdwood@gmail.com>,\n Mark Brown <broonie@kernel.org>,\n Eddie Huang <eddie.huang@mediatek.com>,\n Alessandro Zummo <a.zummo@towertech.it>,\n Alexandre Belloni <alexandre.belloni@bootlin.com>,\n Fei Shao <fshao@chromium.org>", "CC": "Sean Wang <sean.wang@mediatek.com>,\n Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>,\n Yuchen Huang <yuchen.huang@mediatek.com>,\n <devicetree@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>,\n <linux-mediatek@lists.infradead.org>,\n <linux-kernel@vger.kernel.org>, <linux-rtc@vger.kernel.org>,\n <srv_heupstream@mediatek.com>,\n <Project_Global_Chrome_Upstream_Group@mediatek.com>,\n Wen Su <wen.su@mediatek.com>", "Subject": "[PATCH v8 6/8] regulator: mt6359: Add support for MT6359 regulator", "Date": "Wed, 26 May 2021 14:52:05 +0800", "Message-ID": "<1622011927-359-7-git-send-email-hsin-hsiung.wang@mediatek.com>", "X-Mailer": "git-send-email 2.6.4", "In-Reply-To": "<1622011927-359-1-git-send-email-hsin-hsiung.wang@mediatek.com>", "References": "<1622011927-359-1-git-send-email-hsin-hsiung.wang@mediatek.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MTK": "N", "Precedence": "bulk", "List-ID": "<linux-rtc.vger.kernel.org>", "X-Mailing-List": "linux-rtc@vger.kernel.org" }, "content": "From: Wen Su <wen.su@mediatek.com>\n\nThe MT6359 is a regulator found on boards based on MediaTek MT6779 and\nprobably other SoCs. It is a so called pmic and connects as a slave to\nSoC using SPI, wrapped inside the pmic-wrapper.\n\nSigned-off-by: Wen Su <wen.su@mediatek.com>\nSigned-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>\nAcked-by: Mark Brown <broonie@kernel.org>\n---\nchanges since v7:\n- no change.\n---\n drivers/regulator/Kconfig | 9 +\n drivers/regulator/Makefile | 1 +\n drivers/regulator/mt6359-regulator.c | 669 +++++++++++++++++++++++++++++\n include/linux/regulator/mt6359-regulator.h | 58 +++\n 4 files changed, 737 insertions(+)\n create mode 100644 drivers/regulator/mt6359-regulator.c\n create mode 100644 include/linux/regulator/mt6359-regulator.h", "diff": "diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig\nindex 9d84d92..1ef47c9 100644\n--- a/drivers/regulator/Kconfig\n+++ b/drivers/regulator/Kconfig\n@@ -779,6 +779,15 @@ config REGULATOR_MT6358\n \t This driver supports the control of different power rails of device\n \t through regulator interface.\n \n+config REGULATOR_MT6359\n+\ttristate \"MediaTek MT6359 PMIC\"\n+\tdepends on MFD_MT6397\n+\thelp\n+\t Say y here to select this option to enable the power regulator of\n+\t MediaTek MT6359 PMIC.\n+\t This driver supports the control of different power rails of device\n+\t through regulator interface.\n+\n config REGULATOR_MT6360\n \ttristate \"MT6360 SubPMIC Regulator\"\n \tdepends on MFD_MT6360\ndiff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile\nindex 580b015..4f4d996 100644\n--- a/drivers/regulator/Makefile\n+++ b/drivers/regulator/Makefile\n@@ -94,6 +94,7 @@ obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o\n obj-$(CONFIG_REGULATOR_MT6315) += mt6315-regulator.o\n obj-$(CONFIG_REGULATOR_MT6323)\t+= mt6323-regulator.o\n obj-$(CONFIG_REGULATOR_MT6358)\t+= mt6358-regulator.o\n+obj-$(CONFIG_REGULATOR_MT6359)\t+= mt6359-regulator.o\n obj-$(CONFIG_REGULATOR_MT6360) += mt6360-regulator.o\n obj-$(CONFIG_REGULATOR_MT6380)\t+= mt6380-regulator.o\n obj-$(CONFIG_REGULATOR_MT6397)\t+= mt6397-regulator.o\ndiff --git a/drivers/regulator/mt6359-regulator.c b/drivers/regulator/mt6359-regulator.c\nnew file mode 100644\nindex 0000000..994d3f6\n--- /dev/null\n+++ b/drivers/regulator/mt6359-regulator.c\n@@ -0,0 +1,669 @@\n+// SPDX-License-Identifier: GPL-2.0\n+//\n+// Copyright (c) 2021 MediaTek Inc.\n+\n+#include <linux/platform_device.h>\n+#include <linux/mfd/mt6359/registers.h>\n+#include <linux/mfd/mt6397/core.h>\n+#include <linux/module.h>\n+#include <linux/of_device.h>\n+#include <linux/regmap.h>\n+#include <linux/regulator/driver.h>\n+#include <linux/regulator/machine.h>\n+#include <linux/regulator/mt6359-regulator.h>\n+#include <linux/regulator/of_regulator.h>\n+\n+#define MT6359_BUCK_MODE_AUTO\t\t0\n+#define MT6359_BUCK_MODE_FORCE_PWM\t1\n+#define MT6359_BUCK_MODE_NORMAL\t\t0\n+#define MT6359_BUCK_MODE_LP\t\t2\n+\n+/*\n+ * MT6359 regulators' information\n+ *\n+ * @desc: standard fields of regulator description.\n+ * @status_reg: for query status of regulators.\n+ * @qi: Mask for query enable signal status of regulators.\n+ * @modeset_reg: for operating AUTO/PWM mode register.\n+ * @modeset_mask: MASK for operating modeset register.\n+ * @modeset_shift: SHIFT for operating modeset register.\n+ */\n+struct mt6359_regulator_info {\n+\tstruct regulator_desc desc;\n+\tu32 status_reg;\n+\tu32 qi;\n+\tu32 modeset_reg;\n+\tu32 modeset_mask;\n+\tu32 modeset_shift;\n+\tu32 lp_mode_reg;\n+\tu32 lp_mode_mask;\n+\tu32 lp_mode_shift;\n+};\n+\n+#define MT6359_BUCK(match, _name, min, max, step, min_sel,\t\\\n+\tvolt_ranges, _enable_reg, _status_reg,\t\t\t\\\n+\t_vsel_reg, _vsel_mask,\t\t\t\t\t\\\n+\t_lp_mode_reg, _lp_mode_shift,\t\t\t\t\\\n+\t_modeset_reg, _modeset_shift)\t\t\t\t\\\n+[MT6359_ID_##_name] = {\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\\\n+\t\t.name = #_name,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\\\n+\t\t.ops = &mt6359_volt_range_ops,\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\\\n+\t\t.id = MT6359_ID_##_name,\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\\\n+\t\t.uV_step = (step),\t\t\t\t\\\n+\t\t.linear_min_sel = (min_sel),\t\t\t\\\n+\t\t.n_voltages = ((max) - (min)) / (step) + 1,\t\\\n+\t\t.min_uV = (min),\t\t\t\t\\\n+\t\t.linear_ranges = volt_ranges,\t\t\t\\\n+\t\t.n_linear_ranges = ARRAY_SIZE(volt_ranges),\t\\\n+\t\t.vsel_reg = _vsel_reg,\t\t\t\t\\\n+\t\t.vsel_mask = _vsel_mask,\t\t\t\\\n+\t\t.enable_reg = _enable_reg,\t\t\t\\\n+\t\t.enable_mask = BIT(0),\t\t\t\t\\\n+\t\t.of_map_mode = mt6359_map_mode,\t\t\t\\\n+\t},\t\t\t\t\t\t\t\\\n+\t.status_reg = _status_reg,\t\t\t\t\\\n+\t.qi = BIT(0),\t\t\t\t\t\t\\\n+\t.lp_mode_reg = _lp_mode_reg,\t\t\t\t\\\n+\t.lp_mode_mask = BIT(_lp_mode_shift),\t\t\t\\\n+\t.lp_mode_shift = _lp_mode_shift,\t\t\t\\\n+\t.modeset_reg = _modeset_reg,\t\t\t\t\\\n+\t.modeset_mask = BIT(_modeset_shift),\t\t\t\\\n+\t.modeset_shift = _modeset_shift\t\t\t\t\\\n+}\n+\n+#define MT6359_LDO_LINEAR(match, _name, min, max, step, min_sel,\\\n+\tvolt_ranges, _enable_reg, _status_reg,\t\t\t\\\n+\t_vsel_reg, _vsel_mask)\t\t\t\t\t\\\n+[MT6359_ID_##_name] = {\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\\\n+\t\t.name = #_name,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\\\n+\t\t.ops = &mt6359_volt_range_ops,\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\\\n+\t\t.id = MT6359_ID_##_name,\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\\\n+\t\t.uV_step = (step),\t\t\t\t\\\n+\t\t.linear_min_sel = (min_sel),\t\t\t\\\n+\t\t.n_voltages = ((max) - (min)) / (step) + 1,\t\\\n+\t\t.min_uV = (min),\t\t\t\t\\\n+\t\t.linear_ranges = volt_ranges,\t\t\t\\\n+\t\t.n_linear_ranges = ARRAY_SIZE(volt_ranges),\t\\\n+\t\t.vsel_reg = _vsel_reg,\t\t\t\t\\\n+\t\t.vsel_mask = _vsel_mask,\t\t\t\\\n+\t\t.enable_reg = _enable_reg,\t\t\t\\\n+\t\t.enable_mask = BIT(0),\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\\\n+\t.status_reg = _status_reg,\t\t\t\t\\\n+\t.qi = BIT(0),\t\t\t\t\t\t\\\n+}\n+\n+#define MT6359_LDO(match, _name, _volt_table,\t\t\t\\\n+\t_enable_reg, _enable_mask, _status_reg,\t\t\t\\\n+\t_vsel_reg, _vsel_mask, _en_delay)\t\t\t\\\n+[MT6359_ID_##_name] = {\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\\\n+\t\t.name = #_name,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\\\n+\t\t.ops = &mt6359_volt_table_ops,\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\\\n+\t\t.id = MT6359_ID_##_name,\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\\\n+\t\t.n_voltages = ARRAY_SIZE(_volt_table),\t\t\\\n+\t\t.volt_table = _volt_table,\t\t\t\\\n+\t\t.vsel_reg = _vsel_reg,\t\t\t\t\\\n+\t\t.vsel_mask = _vsel_mask,\t\t\t\\\n+\t\t.enable_reg = _enable_reg,\t\t\t\\\n+\t\t.enable_mask = BIT(_enable_mask),\t\t\\\n+\t\t.enable_time = _en_delay,\t\t\t\\\n+\t},\t\t\t\t\t\t\t\\\n+\t.status_reg = _status_reg,\t\t\t\t\\\n+\t.qi = BIT(0),\t\t\t\t\t\t\\\n+}\n+\n+#define MT6359_REG_FIXED(match, _name, _enable_reg,\t\\\n+\t_status_reg, _fixed_volt)\t\t\t\\\n+[MT6359_ID_##_name] = {\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\\\n+\t\t.name = #_name,\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\\\n+\t\t.ops = &mt6359_volt_fixed_ops,\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\\\n+\t\t.id = MT6359_ID_##_name,\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\\\n+\t\t.n_voltages = 1,\t\t\t\\\n+\t\t.enable_reg = _enable_reg,\t\t\\\n+\t\t.enable_mask = BIT(0),\t\t\t\\\n+\t\t.fixed_uV = (_fixed_volt),\t\t\\\n+\t},\t\t\t\t\t\t\\\n+\t.status_reg = _status_reg,\t\t\t\\\n+\t.qi = BIT(0),\t\t\t\t\t\\\n+}\n+\n+static const struct linear_range mt_volt_range1[] = {\n+\tREGULATOR_LINEAR_RANGE(800000, 0, 0x70, 12500),\n+};\n+\n+static const struct linear_range mt_volt_range2[] = {\n+\tREGULATOR_LINEAR_RANGE(400000, 0, 0x7f, 6250),\n+};\n+\n+static const struct linear_range mt_volt_range3[] = {\n+\tREGULATOR_LINEAR_RANGE(400000, 0, 0x70, 6250),\n+};\n+\n+static const struct linear_range mt_volt_range4[] = {\n+\tREGULATOR_LINEAR_RANGE(800000, 0, 0x40, 12500),\n+};\n+\n+static const struct linear_range mt_volt_range5[] = {\n+\tREGULATOR_LINEAR_RANGE(500000, 0, 0x3F, 50000),\n+};\n+\n+static const struct linear_range mt_volt_range6[] = {\n+\tREGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),\n+};\n+\n+static const struct linear_range mt_volt_range7[] = {\n+\tREGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),\n+};\n+\n+static const u32 vsim1_voltages[] = {\n+\t0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000,\n+};\n+\n+static const u32 vibr_voltages[] = {\n+\t1200000, 1300000, 1500000, 0, 1800000, 2000000, 0, 0, 2700000, 2800000,\n+\t0, 3000000, 0, 3300000,\n+};\n+\n+static const u32 vrf12_voltages[] = {\n+\t0, 0, 1100000, 1200000,\t1300000,\n+};\n+\n+static const u32 volt18_voltages[] = {\n+\t0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000,\n+};\n+\n+static const u32 vcn13_voltages[] = {\n+\t900000, 1000000, 0, 1200000, 1300000,\n+};\n+\n+static const u32 vcn33_voltages[] = {\n+\t0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 0, 0, 0, 3300000, 3400000, 3500000,\n+};\n+\n+static const u32 vefuse_voltages[] = {\n+\t0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, 2000000,\n+};\n+\n+static const u32 vxo22_voltages[] = {\n+\t1800000, 0, 0, 0, 2200000,\n+};\n+\n+static const u32 vrfck_voltages[] = {\n+\t0, 0, 1500000, 0, 0, 0, 0, 1600000, 0, 0, 0, 0, 1700000,\n+};\n+\n+static const u32 vio28_voltages[] = {\n+\t0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 2900000, 3000000, 3100000, 3300000,\n+};\n+\n+static const u32 vemc_voltages[] = {\n+\t0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2900000, 3000000, 0, 3300000,\n+};\n+\n+static const u32 va12_voltages[] = {\n+\t0, 0, 0, 0, 0, 0, 1200000, 1300000,\n+};\n+\n+static const u32 va09_voltages[] = {\n+\t0, 0, 800000, 900000, 0, 0, 1200000,\n+};\n+\n+static const u32 vrf18_voltages[] = {\n+\t0, 0, 0, 0, 0, 1700000, 1800000, 1810000,\n+};\n+\n+static const u32 vbbck_voltages[] = {\n+\t0, 0, 0, 0, 1100000, 0, 0, 0, 1150000, 0, 0, 0, 1200000,\n+};\n+\n+static const u32 vsim2_voltages[] = {\n+\t0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000,\n+};\n+\n+static inline unsigned int mt6359_map_mode(unsigned int mode)\n+{\n+\tswitch (mode) {\n+\tcase MT6359_BUCK_MODE_NORMAL:\n+\t\treturn REGULATOR_MODE_NORMAL;\n+\tcase MT6359_BUCK_MODE_FORCE_PWM:\n+\t\treturn REGULATOR_MODE_FAST;\n+\tcase MT6359_BUCK_MODE_LP:\n+\t\treturn REGULATOR_MODE_IDLE;\n+\tdefault:\n+\t\treturn REGULATOR_MODE_INVALID;\n+\t}\n+}\n+\n+static int mt6359_get_status(struct regulator_dev *rdev)\n+{\n+\tint ret;\n+\tu32 regval;\n+\tstruct mt6359_regulator_info *info = rdev_get_drvdata(rdev);\n+\n+\tret = regmap_read(rdev->regmap, info->status_reg, ®val);\n+\tif (ret != 0) {\n+\t\tdev_err(&rdev->dev, \"Failed to get enable reg: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tif (regval & info->qi)\n+\t\treturn REGULATOR_STATUS_ON;\n+\telse\n+\t\treturn REGULATOR_STATUS_OFF;\n+}\n+\n+static unsigned int mt6359_regulator_get_mode(struct regulator_dev *rdev)\n+{\n+\tstruct mt6359_regulator_info *info = rdev_get_drvdata(rdev);\n+\tint ret, regval;\n+\n+\tret = regmap_read(rdev->regmap, info->modeset_reg, ®val);\n+\tif (ret != 0) {\n+\t\tdev_err(&rdev->dev,\n+\t\t\t\"Failed to get mt6359 buck mode: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tif ((regval & info->modeset_mask) >> info->modeset_shift ==\n+\t\tMT6359_BUCK_MODE_FORCE_PWM)\n+\t\treturn REGULATOR_MODE_FAST;\n+\n+\tret = regmap_read(rdev->regmap, info->lp_mode_reg, ®val);\n+\tif (ret != 0) {\n+\t\tdev_err(&rdev->dev,\n+\t\t\t\"Failed to get mt6359 buck lp mode: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tif (regval & info->lp_mode_mask)\n+\t\treturn REGULATOR_MODE_IDLE;\n+\telse\n+\t\treturn REGULATOR_MODE_NORMAL;\n+}\n+\n+static int mt6359_regulator_set_mode(struct regulator_dev *rdev,\n+\t\t\t\t unsigned int mode)\n+{\n+\tstruct mt6359_regulator_info *info = rdev_get_drvdata(rdev);\n+\tint ret = 0, val;\n+\tint curr_mode;\n+\n+\tcurr_mode = mt6359_regulator_get_mode(rdev);\n+\tswitch (mode) {\n+\tcase REGULATOR_MODE_FAST:\n+\t\tval = MT6359_BUCK_MODE_FORCE_PWM;\n+\t\tval <<= info->modeset_shift;\n+\t\tret = regmap_update_bits(rdev->regmap,\n+\t\t\t\t\t info->modeset_reg,\n+\t\t\t\t\t info->modeset_mask,\n+\t\t\t\t\t val);\n+\t\tbreak;\n+\tcase REGULATOR_MODE_NORMAL:\n+\t\tif (curr_mode == REGULATOR_MODE_FAST) {\n+\t\t\tval = MT6359_BUCK_MODE_AUTO;\n+\t\t\tval <<= info->modeset_shift;\n+\t\t\tret = regmap_update_bits(rdev->regmap,\n+\t\t\t\t\t\t info->modeset_reg,\n+\t\t\t\t\t\t info->modeset_mask,\n+\t\t\t\t\t\t val);\n+\t\t} else if (curr_mode == REGULATOR_MODE_IDLE) {\n+\t\t\tval = MT6359_BUCK_MODE_NORMAL;\n+\t\t\tval <<= info->lp_mode_shift;\n+\t\t\tret = regmap_update_bits(rdev->regmap,\n+\t\t\t\t\t\t info->lp_mode_reg,\n+\t\t\t\t\t\t info->lp_mode_mask,\n+\t\t\t\t\t\t val);\n+\t\t\tudelay(100);\n+\t\t}\n+\t\tbreak;\n+\tcase REGULATOR_MODE_IDLE:\n+\t\tval = MT6359_BUCK_MODE_LP >> 1;\n+\t\tval <<= info->lp_mode_shift;\n+\t\tret = regmap_update_bits(rdev->regmap,\n+\t\t\t\t\t info->lp_mode_reg,\n+\t\t\t\t\t info->lp_mode_mask,\n+\t\t\t\t\t val);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (ret != 0) {\n+\t\tdev_err(&rdev->dev,\n+\t\t\t\"Failed to set mt6359 buck mode: %d\\n\", ret);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static const struct regulator_ops mt6359_volt_range_ops = {\n+\t.list_voltage = regulator_list_voltage_linear_range,\n+\t.map_voltage = regulator_map_voltage_linear_range,\n+\t.set_voltage_sel = regulator_set_voltage_sel_regmap,\n+\t.get_voltage_sel = regulator_get_voltage_sel_regmap,\n+\t.set_voltage_time_sel = regulator_set_voltage_time_sel,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.get_status = mt6359_get_status,\n+\t.set_mode = mt6359_regulator_set_mode,\n+\t.get_mode = mt6359_regulator_get_mode,\n+};\n+\n+static const struct regulator_ops mt6359_volt_table_ops = {\n+\t.list_voltage = regulator_list_voltage_table,\n+\t.map_voltage = regulator_map_voltage_iterate,\n+\t.set_voltage_sel = regulator_set_voltage_sel_regmap,\n+\t.get_voltage_sel = regulator_get_voltage_sel_regmap,\n+\t.set_voltage_time_sel = regulator_set_voltage_time_sel,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.get_status = mt6359_get_status,\n+};\n+\n+static const struct regulator_ops mt6359_volt_fixed_ops = {\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.get_status = mt6359_get_status,\n+};\n+\n+/* The array is indexed by id(MT6359_ID_XXX) */\n+static struct mt6359_regulator_info mt6359_regulators[] = {\n+\tMT6359_BUCK(\"buck_vs1\", VS1, 800000, 2200000, 12500, 0,\n+\t\t mt_volt_range1, MT6359_RG_BUCK_VS1_EN_ADDR,\n+\t\t MT6359_DA_VS1_EN_ADDR, MT6359_RG_BUCK_VS1_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VS1_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VS1_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT,\n+\t\t MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT),\n+\tMT6359_BUCK(\"buck_vgpu11\", VGPU11, 400000, 1193750, 6250, 0,\n+\t\t mt_volt_range2, MT6359_RG_BUCK_VGPU11_EN_ADDR,\n+\t\t MT6359_DA_VGPU11_EN_ADDR, MT6359_RG_BUCK_VGPU11_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VGPU11_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VGPU11_LP_ADDR,\n+\t\t MT6359_RG_BUCK_VGPU11_LP_SHIFT,\n+\t\t MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT),\n+\tMT6359_BUCK(\"buck_vmodem\", VMODEM, 400000, 1100000, 6250, 0,\n+\t\t mt_volt_range3, MT6359_RG_BUCK_VMODEM_EN_ADDR,\n+\t\t MT6359_DA_VMODEM_EN_ADDR, MT6359_RG_BUCK_VMODEM_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VMODEM_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VMODEM_LP_ADDR,\n+\t\t MT6359_RG_BUCK_VMODEM_LP_SHIFT,\n+\t\t MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT),\n+\tMT6359_BUCK(\"buck_vpu\", VPU, 400000, 1193750, 6250, 0,\n+\t\t mt_volt_range2, MT6359_RG_BUCK_VPU_EN_ADDR,\n+\t\t MT6359_DA_VPU_EN_ADDR, MT6359_RG_BUCK_VPU_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VPU_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VPU_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT,\n+\t\t MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT),\n+\tMT6359_BUCK(\"buck_vcore\", VCORE, 400000, 1193750, 6250, 0,\n+\t\t mt_volt_range2, MT6359_RG_BUCK_VCORE_EN_ADDR,\n+\t\t MT6359_DA_VCORE_EN_ADDR, MT6359_RG_BUCK_VCORE_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VCORE_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VCORE_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT,\n+\t\t MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT),\n+\tMT6359_BUCK(\"buck_vs2\", VS2, 800000, 1600000, 12500, 0,\n+\t\t mt_volt_range4, MT6359_RG_BUCK_VS2_EN_ADDR,\n+\t\t MT6359_DA_VS2_EN_ADDR, MT6359_RG_BUCK_VS2_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VS2_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VS2_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT,\n+\t\t MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT),\n+\tMT6359_BUCK(\"buck_vpa\", VPA, 500000, 3650000, 50000, 0,\n+\t\t mt_volt_range5, MT6359_RG_BUCK_VPA_EN_ADDR,\n+\t\t MT6359_DA_VPA_EN_ADDR, MT6359_RG_BUCK_VPA_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VPA_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VPA_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT,\n+\t\t MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT),\n+\tMT6359_BUCK(\"buck_vproc2\", VPROC2, 400000, 1193750, 6250, 0,\n+\t\t mt_volt_range2, MT6359_RG_BUCK_VPROC2_EN_ADDR,\n+\t\t MT6359_DA_VPROC2_EN_ADDR, MT6359_RG_BUCK_VPROC2_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VPROC2_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VPROC2_LP_ADDR,\n+\t\t MT6359_RG_BUCK_VPROC2_LP_SHIFT,\n+\t\t MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT),\n+\tMT6359_BUCK(\"buck_vproc1\", VPROC1, 400000, 1193750, 6250, 0,\n+\t\t mt_volt_range2, MT6359_RG_BUCK_VPROC1_EN_ADDR,\n+\t\t MT6359_DA_VPROC1_EN_ADDR, MT6359_RG_BUCK_VPROC1_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VPROC1_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VPROC1_LP_ADDR,\n+\t\t MT6359_RG_BUCK_VPROC1_LP_SHIFT,\n+\t\t MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT),\n+\tMT6359_BUCK(\"buck_vcore_sshub\", VCORE_SSHUB, 400000, 1193750, 6250, 0,\n+\t\t mt_volt_range2, MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR,\n+\t\t MT6359_DA_VCORE_EN_ADDR,\n+\t\t MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR,\n+\t\t MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK <<\n+\t\t MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT,\n+\t\t MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT,\n+\t\t MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT),\n+\tMT6359_REG_FIXED(\"ldo_vaud18\", VAUD18, MT6359_RG_LDO_VAUD18_EN_ADDR,\n+\t\t\t MT6359_DA_VAUD18_B_EN_ADDR, 1800000),\n+\tMT6359_LDO(\"ldo_vsim1\", VSIM1, vsim1_voltages,\n+\t\t MT6359_RG_LDO_VSIM1_EN_ADDR, MT6359_RG_LDO_VSIM1_EN_SHIFT,\n+\t\t MT6359_DA_VSIM1_B_EN_ADDR, MT6359_RG_VSIM1_VOSEL_ADDR,\n+\t\t MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT,\n+\t\t 480),\n+\tMT6359_LDO(\"ldo_vibr\", VIBR, vibr_voltages,\n+\t\t MT6359_RG_LDO_VIBR_EN_ADDR, MT6359_RG_LDO_VIBR_EN_SHIFT,\n+\t\t MT6359_DA_VIBR_B_EN_ADDR, MT6359_RG_VIBR_VOSEL_ADDR,\n+\t\t MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT,\n+\t\t 240),\n+\tMT6359_LDO(\"ldo_vrf12\", VRF12, vrf12_voltages,\n+\t\t MT6359_RG_LDO_VRF12_EN_ADDR, MT6359_RG_LDO_VRF12_EN_SHIFT,\n+\t\t MT6359_DA_VRF12_B_EN_ADDR, MT6359_RG_VRF12_VOSEL_ADDR,\n+\t\t MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT,\n+\t\t 120),\n+\tMT6359_REG_FIXED(\"ldo_vusb\", VUSB, MT6359_RG_LDO_VUSB_EN_0_ADDR,\n+\t\t\t MT6359_DA_VUSB_B_EN_ADDR, 3000000),\n+\tMT6359_LDO_LINEAR(\"ldo_vsram_proc2\", VSRAM_PROC2, 500000, 1293750, 6250,\n+\t\t\t 0, mt_volt_range6, MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR,\n+\t\t\t MT6359_DA_VSRAM_PROC2_B_EN_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK <<\n+\t\t\t MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT),\n+\tMT6359_LDO(\"ldo_vio18\", VIO18, volt18_voltages,\n+\t\t MT6359_RG_LDO_VIO18_EN_ADDR, MT6359_RG_LDO_VIO18_EN_SHIFT,\n+\t\t MT6359_DA_VIO18_B_EN_ADDR, MT6359_RG_VIO18_VOSEL_ADDR,\n+\t\t MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT,\n+\t\t 960),\n+\tMT6359_LDO(\"ldo_vcamio\", VCAMIO, volt18_voltages,\n+\t\t MT6359_RG_LDO_VCAMIO_EN_ADDR, MT6359_RG_LDO_VCAMIO_EN_SHIFT,\n+\t\t MT6359_DA_VCAMIO_B_EN_ADDR, MT6359_RG_VCAMIO_VOSEL_ADDR,\n+\t\t MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT,\n+\t\t 1290),\n+\tMT6359_REG_FIXED(\"ldo_vcn18\", VCN18, MT6359_RG_LDO_VCN18_EN_ADDR,\n+\t\t\t MT6359_DA_VCN18_B_EN_ADDR, 1800000),\n+\tMT6359_REG_FIXED(\"ldo_vfe28\", VFE28, MT6359_RG_LDO_VFE28_EN_ADDR,\n+\t\t\t MT6359_DA_VFE28_B_EN_ADDR, 2800000),\n+\tMT6359_LDO(\"ldo_vcn13\", VCN13, vcn13_voltages,\n+\t\t MT6359_RG_LDO_VCN13_EN_ADDR, MT6359_RG_LDO_VCN13_EN_SHIFT,\n+\t\t MT6359_DA_VCN13_B_EN_ADDR, MT6359_RG_VCN13_VOSEL_ADDR,\n+\t\t MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT,\n+\t\t 240),\n+\tMT6359_LDO(\"ldo_vcn33_1_bt\", VCN33_1_BT, vcn33_voltages,\n+\t\t MT6359_RG_LDO_VCN33_1_EN_0_ADDR,\n+\t\t MT6359_RG_LDO_VCN33_1_EN_0_SHIFT,\n+\t\t MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR,\n+\t\t MT6359_RG_VCN33_1_VOSEL_MASK <<\n+\t\t MT6359_RG_VCN33_1_VOSEL_SHIFT, 240),\n+\tMT6359_LDO(\"ldo_vcn33_1_wifi\", VCN33_1_WIFI, vcn33_voltages,\n+\t\t MT6359_RG_LDO_VCN33_1_EN_1_ADDR,\n+\t\t MT6359_RG_LDO_VCN33_1_EN_1_SHIFT,\n+\t\t MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR,\n+\t\t MT6359_RG_VCN33_1_VOSEL_MASK <<\n+\t\t MT6359_RG_VCN33_1_VOSEL_SHIFT, 240),\n+\tMT6359_REG_FIXED(\"ldo_vaux18\", VAUX18, MT6359_RG_LDO_VAUX18_EN_ADDR,\n+\t\t\t MT6359_DA_VAUX18_B_EN_ADDR, 1800000),\n+\tMT6359_LDO_LINEAR(\"ldo_vsram_others\", VSRAM_OTHERS, 500000, 1293750,\n+\t\t\t 6250, 0, mt_volt_range6,\n+\t\t\t MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR,\n+\t\t\t MT6359_DA_VSRAM_OTHERS_B_EN_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK <<\n+\t\t\t MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT),\n+\tMT6359_LDO(\"ldo_vefuse\", VEFUSE, vefuse_voltages,\n+\t\t MT6359_RG_LDO_VEFUSE_EN_ADDR, MT6359_RG_LDO_VEFUSE_EN_SHIFT,\n+\t\t MT6359_DA_VEFUSE_B_EN_ADDR, MT6359_RG_VEFUSE_VOSEL_ADDR,\n+\t\t MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT,\n+\t\t 240),\n+\tMT6359_LDO(\"ldo_vxo22\", VXO22, vxo22_voltages,\n+\t\t MT6359_RG_LDO_VXO22_EN_ADDR, MT6359_RG_LDO_VXO22_EN_SHIFT,\n+\t\t MT6359_DA_VXO22_B_EN_ADDR, MT6359_RG_VXO22_VOSEL_ADDR,\n+\t\t MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT,\n+\t\t 120),\n+\tMT6359_LDO(\"ldo_vrfck\", VRFCK, vrfck_voltages,\n+\t\t MT6359_RG_LDO_VRFCK_EN_ADDR, MT6359_RG_LDO_VRFCK_EN_SHIFT,\n+\t\t MT6359_DA_VRFCK_B_EN_ADDR, MT6359_RG_VRFCK_VOSEL_ADDR,\n+\t\t MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT,\n+\t\t 480),\n+\tMT6359_REG_FIXED(\"ldo_vbif28\", VBIF28, MT6359_RG_LDO_VBIF28_EN_ADDR,\n+\t\t\t MT6359_DA_VBIF28_B_EN_ADDR, 2800000),\n+\tMT6359_LDO(\"ldo_vio28\", VIO28, vio28_voltages,\n+\t\t MT6359_RG_LDO_VIO28_EN_ADDR, MT6359_RG_LDO_VIO28_EN_SHIFT,\n+\t\t MT6359_DA_VIO28_B_EN_ADDR, MT6359_RG_VIO28_VOSEL_ADDR,\n+\t\t MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT,\n+\t\t 240),\n+\tMT6359_LDO(\"ldo_vemc\", VEMC, vemc_voltages,\n+\t\t MT6359_RG_LDO_VEMC_EN_ADDR, MT6359_RG_LDO_VEMC_EN_SHIFT,\n+\t\t MT6359_DA_VEMC_B_EN_ADDR, MT6359_RG_VEMC_VOSEL_ADDR,\n+\t\t MT6359_RG_VEMC_VOSEL_MASK << MT6359_RG_VEMC_VOSEL_SHIFT,\n+\t\t 240),\n+\tMT6359_LDO(\"ldo_vcn33_2_bt\", VCN33_2_BT, vcn33_voltages,\n+\t\t MT6359_RG_LDO_VCN33_2_EN_0_ADDR,\n+\t\t MT6359_RG_LDO_VCN33_2_EN_0_SHIFT,\n+\t\t MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR,\n+\t\t MT6359_RG_VCN33_2_VOSEL_MASK <<\n+\t\t MT6359_RG_VCN33_2_VOSEL_SHIFT, 240),\n+\tMT6359_LDO(\"ldo_vcn33_2_wifi\", VCN33_2_WIFI, vcn33_voltages,\n+\t\t MT6359_RG_LDO_VCN33_2_EN_1_ADDR,\n+\t\t MT6359_RG_LDO_VCN33_2_EN_1_SHIFT,\n+\t\t MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR,\n+\t\t MT6359_RG_VCN33_2_VOSEL_MASK <<\n+\t\t MT6359_RG_VCN33_2_VOSEL_SHIFT, 240),\n+\tMT6359_LDO(\"ldo_va12\", VA12, va12_voltages,\n+\t\t MT6359_RG_LDO_VA12_EN_ADDR, MT6359_RG_LDO_VA12_EN_SHIFT,\n+\t\t MT6359_DA_VA12_B_EN_ADDR, MT6359_RG_VA12_VOSEL_ADDR,\n+\t\t MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT,\n+\t\t 240),\n+\tMT6359_LDO(\"ldo_va09\", VA09, va09_voltages,\n+\t\t MT6359_RG_LDO_VA09_EN_ADDR, MT6359_RG_LDO_VA09_EN_SHIFT,\n+\t\t MT6359_DA_VA09_B_EN_ADDR, MT6359_RG_VA09_VOSEL_ADDR,\n+\t\t MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT,\n+\t\t 240),\n+\tMT6359_LDO(\"ldo_vrf18\", VRF18, vrf18_voltages,\n+\t\t MT6359_RG_LDO_VRF18_EN_ADDR, MT6359_RG_LDO_VRF18_EN_SHIFT,\n+\t\t MT6359_DA_VRF18_B_EN_ADDR, MT6359_RG_VRF18_VOSEL_ADDR,\n+\t\t MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT,\n+\t\t 120),\n+\tMT6359_LDO_LINEAR(\"ldo_vsram_md\", VSRAM_MD, 500000, 1100000, 6250,\n+\t\t\t 0, mt_volt_range7, MT6359_RG_LDO_VSRAM_MD_EN_ADDR,\n+\t\t\t MT6359_DA_VSRAM_MD_B_EN_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK <<\n+\t\t\t MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT),\n+\tMT6359_LDO(\"ldo_vufs\", VUFS, volt18_voltages,\n+\t\t MT6359_RG_LDO_VUFS_EN_ADDR, MT6359_RG_LDO_VUFS_EN_SHIFT,\n+\t\t MT6359_DA_VUFS_B_EN_ADDR, MT6359_RG_VUFS_VOSEL_ADDR,\n+\t\t MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT,\n+\t\t 1920),\n+\tMT6359_LDO(\"ldo_vm18\", VM18, volt18_voltages,\n+\t\t MT6359_RG_LDO_VM18_EN_ADDR, MT6359_RG_LDO_VM18_EN_SHIFT,\n+\t\t MT6359_DA_VM18_B_EN_ADDR, MT6359_RG_VM18_VOSEL_ADDR,\n+\t\t MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT,\n+\t\t 1920),\n+\tMT6359_LDO(\"ldo_vbbck\", VBBCK, vbbck_voltages,\n+\t\t MT6359_RG_LDO_VBBCK_EN_ADDR, MT6359_RG_LDO_VBBCK_EN_SHIFT,\n+\t\t MT6359_DA_VBBCK_B_EN_ADDR, MT6359_RG_VBBCK_VOSEL_ADDR,\n+\t\t MT6359_RG_VBBCK_VOSEL_MASK << MT6359_RG_VBBCK_VOSEL_SHIFT,\n+\t\t 240),\n+\tMT6359_LDO_LINEAR(\"ldo_vsram_proc1\", VSRAM_PROC1, 500000, 1293750, 6250,\n+\t\t\t 0, mt_volt_range6, MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR,\n+\t\t\t MT6359_DA_VSRAM_PROC1_B_EN_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK <<\n+\t\t\t MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT),\n+\tMT6359_LDO(\"ldo_vsim2\", VSIM2, vsim2_voltages,\n+\t\t MT6359_RG_LDO_VSIM2_EN_ADDR, MT6359_RG_LDO_VSIM2_EN_SHIFT,\n+\t\t MT6359_DA_VSIM2_B_EN_ADDR, MT6359_RG_VSIM2_VOSEL_ADDR,\n+\t\t MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT,\n+\t\t 480),\n+\tMT6359_LDO_LINEAR(\"ldo_vsram_others_sshub\", VSRAM_OTHERS_SSHUB,\n+\t\t\t 500000, 1293750, 6250, 0, mt_volt_range6,\n+\t\t\t MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR,\n+\t\t\t MT6359_DA_VSRAM_OTHERS_B_EN_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR,\n+\t\t\t MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK <<\n+\t\t\t MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT),\n+};\n+\n+static int mt6359_regulator_probe(struct platform_device *pdev)\n+{\n+\tstruct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);\n+\tstruct regulator_config config = {};\n+\tstruct regulator_dev *rdev;\n+\tint i;\n+\n+\tconfig.dev = mt6397->dev;\n+\tconfig.regmap = mt6397->regmap;\n+\tfor (i = 0; i < MT6359_MAX_REGULATOR; i++) {\n+\t\tconfig.driver_data = &mt6359_regulators[i];\n+\t\trdev = devm_regulator_register(&pdev->dev, &mt6359_regulators[i].desc, &config);\n+\t\tif (IS_ERR(rdev)) {\n+\t\t\tdev_err(&pdev->dev, \"failed to register %s\\n\",\n+\t\t\t\tmt6359_regulators[i].desc.name);\n+\t\t\treturn PTR_ERR(rdev);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct platform_device_id mt6359_platform_ids[] = {\n+\t{\"mt6359-regulator\", 0},\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(platform, mt6359_platform_ids);\n+\n+static struct platform_driver mt6359_regulator_driver = {\n+\t.driver = {\n+\t\t.name = \"mt6359-regulator\",\n+\t},\n+\t.probe = mt6359_regulator_probe,\n+\t.id_table = mt6359_platform_ids,\n+};\n+\n+module_platform_driver(mt6359_regulator_driver);\n+\n+MODULE_AUTHOR(\"Wen Su <wen.su@mediatek.com>\");\n+MODULE_DESCRIPTION(\"Regulator Driver for MediaTek MT6359 PMIC\");\n+MODULE_LICENSE(\"GPL\");\ndiff --git a/include/linux/regulator/mt6359-regulator.h b/include/linux/regulator/mt6359-regulator.h\nnew file mode 100644\nindex 0000000..14c4b71\n--- /dev/null\n+++ b/include/linux/regulator/mt6359-regulator.h\n@@ -0,0 +1,58 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2021 MediaTek Inc.\n+ */\n+\n+#ifndef __LINUX_REGULATOR_MT6359_H\n+#define __LINUX_REGULATOR_MT6359_H\n+\n+enum {\n+\tMT6359_ID_VS1 = 0,\n+\tMT6359_ID_VGPU11,\n+\tMT6359_ID_VMODEM,\n+\tMT6359_ID_VPU,\n+\tMT6359_ID_VCORE,\n+\tMT6359_ID_VS2,\n+\tMT6359_ID_VPA,\n+\tMT6359_ID_VPROC2,\n+\tMT6359_ID_VPROC1,\n+\tMT6359_ID_VCORE_SSHUB,\n+\tMT6359_ID_VAUD18 = 10,\n+\tMT6359_ID_VSIM1,\n+\tMT6359_ID_VIBR,\n+\tMT6359_ID_VRF12,\n+\tMT6359_ID_VUSB,\n+\tMT6359_ID_VSRAM_PROC2,\n+\tMT6359_ID_VIO18,\n+\tMT6359_ID_VCAMIO,\n+\tMT6359_ID_VCN18,\n+\tMT6359_ID_VFE28,\n+\tMT6359_ID_VCN13,\n+\tMT6359_ID_VCN33_1_BT,\n+\tMT6359_ID_VCN33_1_WIFI,\n+\tMT6359_ID_VAUX18,\n+\tMT6359_ID_VSRAM_OTHERS,\n+\tMT6359_ID_VEFUSE,\n+\tMT6359_ID_VXO22,\n+\tMT6359_ID_VRFCK,\n+\tMT6359_ID_VBIF28,\n+\tMT6359_ID_VIO28,\n+\tMT6359_ID_VEMC,\n+\tMT6359_ID_VCN33_2_BT,\n+\tMT6359_ID_VCN33_2_WIFI,\n+\tMT6359_ID_VA12,\n+\tMT6359_ID_VA09,\n+\tMT6359_ID_VRF18,\n+\tMT6359_ID_VSRAM_MD,\n+\tMT6359_ID_VUFS,\n+\tMT6359_ID_VM18,\n+\tMT6359_ID_VBBCK,\n+\tMT6359_ID_VSRAM_PROC1,\n+\tMT6359_ID_VSIM2,\n+\tMT6359_ID_VSRAM_OTHERS_SSHUB,\n+\tMT6359_ID_RG_MAX,\n+};\n+\n+#define MT6359_MAX_REGULATOR\tMT6359_ID_RG_MAX\n+\n+#endif /* __LINUX_REGULATOR_MT6359_H */\n", "prefixes": [ "v8", "6/8" ] }