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GET /api/patches/1483907/?format=api
{ "id": 1483907, "url": "http://patchwork.ozlabs.org/api/patches/1483907/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/patch/1622011927-359-2-git-send-email-hsin-hsiung.wang@mediatek.com/", "project": { "id": 9, "url": "http://patchwork.ozlabs.org/api/projects/9/?format=api", "name": "Linux RTC development", "link_name": "rtc-linux", "list_id": "linux-rtc.vger.kernel.org", "list_email": "linux-rtc@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1622011927-359-2-git-send-email-hsin-hsiung.wang@mediatek.com>", "list_archive_url": null, "date": "2021-05-26T06:52:00", "name": "[v8,1/8] mfd: mt6358: refine interrupt code", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "e8f9ee95d55702188ed239da7c4c204d7b53cfa1", "submitter": { "id": 74946, "url": "http://patchwork.ozlabs.org/api/people/74946/?format=api", "name": "Hsin-Hsiung Wang", "email": "hsin-hsiung.wang@mediatek.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/rtc-linux/patch/1622011927-359-2-git-send-email-hsin-hsiung.wang@mediatek.com/mbox/", "series": [ { "id": 245778, "url": "http://patchwork.ozlabs.org/api/series/245778/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/list/?series=245778", "date": "2021-05-26T06:52:02", "name": "Add Support for MediaTek PMIC MT6359", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/245778/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1483907/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1483907/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-rtc-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=23.128.96.18; helo=vger.kernel.org;\n envelope-from=linux-rtc-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [23.128.96.18])\n\tby ozlabs.org (Postfix) with ESMTP id 4FqhTK6Kl1z9sW6\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 26 May 2021 16:52:21 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S232927AbhEZGxu (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n Wed, 26 May 2021 02:53:50 -0400", "from mailgw01.mediatek.com ([210.61.82.183]:37255 \"EHLO\n mailgw01.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org\n with ESMTP id S232336AbhEZGxt (ORCPT\n <rfc822;linux-rtc@vger.kernel.org>); Wed, 26 May 2021 02:53:49 -0400", "from mtkcas07.mediatek.inc [(172.21.101.84)] by\n mailgw01.mediatek.com\n (envelope-from <hsin-hsiung.wang@mediatek.com>)\n (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256)\n with ESMTP id 2098683584; Wed, 26 May 2021 14:52:13 +0800", "from mtkcas11.mediatek.inc (172.21.101.40) by\n mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Wed, 26 May 2021 14:52:12 +0800", "from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas11.mediatek.inc\n (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 26 May 2021 14:52:11 +0800" ], "X-UUID": [ "1b47c5e58580455e8c23abb22cd0e188-20210526", "1b47c5e58580455e8c23abb22cd0e188-20210526" ], "From": "Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>", "To": "Lee Jones <lee.jones@linaro.org>, Rob Herring <robh+dt@kernel.org>,\n Matthias Brugger <matthias.bgg@gmail.com>,\n Liam Girdwood <lgirdwood@gmail.com>,\n Mark Brown <broonie@kernel.org>,\n Eddie Huang <eddie.huang@mediatek.com>,\n Alessandro Zummo <a.zummo@towertech.it>,\n Alexandre Belloni <alexandre.belloni@bootlin.com>,\n Fei Shao <fshao@chromium.org>", "CC": "Sean Wang <sean.wang@mediatek.com>,\n Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>,\n Yuchen Huang <yuchen.huang@mediatek.com>,\n <devicetree@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>,\n <linux-mediatek@lists.infradead.org>,\n <linux-kernel@vger.kernel.org>, <linux-rtc@vger.kernel.org>,\n <srv_heupstream@mediatek.com>,\n <Project_Global_Chrome_Upstream_Group@mediatek.com>", "Subject": "[PATCH v8 1/8] mfd: mt6358: refine interrupt code", "Date": "Wed, 26 May 2021 14:52:00 +0800", "Message-ID": "<1622011927-359-2-git-send-email-hsin-hsiung.wang@mediatek.com>", "X-Mailer": "git-send-email 2.6.4", "In-Reply-To": "<1622011927-359-1-git-send-email-hsin-hsiung.wang@mediatek.com>", "References": "<1622011927-359-1-git-send-email-hsin-hsiung.wang@mediatek.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MTK": "N", "Precedence": "bulk", "List-ID": "<linux-rtc.vger.kernel.org>", "X-Mailing-List": "linux-rtc@vger.kernel.org" }, "content": "This patch refines the interrupt related code to support new chips.\n\nSigned-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>\nAcked-for-MFD-by: Lee Jones <lee.jones@linaro.org>\n---\nchanges since v7:\n- no change.\n---\n drivers/mfd/mt6358-irq.c | 65 ++++++++++++++++++++++++-----------------\n include/linux/mfd/mt6358/core.h | 8 ++---\n 2 files changed, 41 insertions(+), 32 deletions(-)", "diff": "diff --git a/drivers/mfd/mt6358-irq.c b/drivers/mfd/mt6358-irq.c\nindex db734f2..4b094e5 100644\n--- a/drivers/mfd/mt6358-irq.c\n+++ b/drivers/mfd/mt6358-irq.c\n@@ -13,7 +13,9 @@\n #include <linux/platform_device.h>\n #include <linux/regmap.h>\n \n-static struct irq_top_t mt6358_ints[] = {\n+#define MTK_PMIC_REG_WIDTH 16\n+\n+static const struct irq_top_t mt6358_ints[] = {\n \tMT6358_TOP_GEN(BUCK),\n \tMT6358_TOP_GEN(LDO),\n \tMT6358_TOP_GEN(PSC),\n@@ -24,6 +26,13 @@ static struct irq_top_t mt6358_ints[] = {\n \tMT6358_TOP_GEN(MISC),\n };\n \n+static struct pmic_irq_data mt6358_irqd = {\n+\t.num_top = ARRAY_SIZE(mt6358_ints),\n+\t.num_pmic_irqs = MT6358_IRQ_NR,\n+\t.top_int_status_reg = MT6358_TOP_INT_STATUS0,\n+\t.pmic_ints = mt6358_ints,\n+};\n+\n static void pmic_irq_enable(struct irq_data *data)\n {\n \tunsigned int hwirq = irqd_to_hwirq(data);\n@@ -62,15 +71,15 @@ static void pmic_irq_sync_unlock(struct irq_data *data)\n \t\t/* Find out the IRQ group */\n \t\ttop_gp = 0;\n \t\twhile ((top_gp + 1) < irqd->num_top &&\n-\t\t i >= mt6358_ints[top_gp + 1].hwirq_base)\n+\t\t i >= irqd->pmic_ints[top_gp + 1].hwirq_base)\n \t\t\ttop_gp++;\n \n \t\t/* Find the IRQ registers */\n-\t\tgp_offset = i - mt6358_ints[top_gp].hwirq_base;\n-\t\tint_regs = gp_offset / MT6358_REG_WIDTH;\n-\t\tshift = gp_offset % MT6358_REG_WIDTH;\n-\t\ten_reg = mt6358_ints[top_gp].en_reg +\n-\t\t\t (mt6358_ints[top_gp].en_reg_shift * int_regs);\n+\t\tgp_offset = i - irqd->pmic_ints[top_gp].hwirq_base;\n+\t\tint_regs = gp_offset / MTK_PMIC_REG_WIDTH;\n+\t\tshift = gp_offset % MTK_PMIC_REG_WIDTH;\n+\t\ten_reg = irqd->pmic_ints[top_gp].en_reg +\n+\t\t\t (irqd->pmic_ints[top_gp].en_reg_shift * int_regs);\n \n \t\tregmap_update_bits(chip->regmap, en_reg, BIT(shift),\n \t\t\t\t irqd->enable_hwirq[i] << shift);\n@@ -95,10 +104,11 @@ static void mt6358_irq_sp_handler(struct mt6397_chip *chip,\n \tunsigned int irq_status, sta_reg, status;\n \tunsigned int hwirq, virq;\n \tint i, j, ret;\n+\tstruct pmic_irq_data *irqd = chip->irq_data;\n \n-\tfor (i = 0; i < mt6358_ints[top_gp].num_int_regs; i++) {\n-\t\tsta_reg = mt6358_ints[top_gp].sta_reg +\n-\t\t\tmt6358_ints[top_gp].sta_reg_shift * i;\n+\tfor (i = 0; i < irqd->pmic_ints[top_gp].num_int_regs; i++) {\n+\t\tsta_reg = irqd->pmic_ints[top_gp].sta_reg +\n+\t\t\tirqd->pmic_ints[top_gp].sta_reg_shift * i;\n \n \t\tret = regmap_read(chip->regmap, sta_reg, &irq_status);\n \t\tif (ret) {\n@@ -114,8 +124,8 @@ static void mt6358_irq_sp_handler(struct mt6397_chip *chip,\n \t\tdo {\n \t\t\tj = __ffs(status);\n \n-\t\t\thwirq = mt6358_ints[top_gp].hwirq_base +\n-\t\t\t\tMT6358_REG_WIDTH * i + j;\n+\t\t\thwirq = irqd->pmic_ints[top_gp].hwirq_base +\n+\t\t\t\tMTK_PMIC_REG_WIDTH * i + j;\n \n \t\t\tvirq = irq_find_mapping(chip->irq_domain, hwirq);\n \t\t\tif (virq)\n@@ -131,12 +141,12 @@ static void mt6358_irq_sp_handler(struct mt6397_chip *chip,\n static irqreturn_t mt6358_irq_handler(int irq, void *data)\n {\n \tstruct mt6397_chip *chip = data;\n-\tstruct pmic_irq_data *mt6358_irq_data = chip->irq_data;\n+\tstruct pmic_irq_data *irqd = chip->irq_data;\n \tunsigned int bit, i, top_irq_status = 0;\n \tint ret;\n \n \tret = regmap_read(chip->regmap,\n-\t\t\t mt6358_irq_data->top_int_status_reg,\n+\t\t\t irqd->top_int_status_reg,\n \t\t\t &top_irq_status);\n \tif (ret) {\n \t\tdev_err(chip->dev,\n@@ -144,8 +154,8 @@ static irqreturn_t mt6358_irq_handler(int irq, void *data)\n \t\treturn IRQ_NONE;\n \t}\n \n-\tfor (i = 0; i < mt6358_irq_data->num_top; i++) {\n-\t\tbit = BIT(mt6358_ints[i].top_offset);\n+\tfor (i = 0; i < irqd->num_top; i++) {\n+\t\tbit = BIT(irqd->pmic_ints[i].top_offset);\n \t\tif (top_irq_status & bit) {\n \t\t\tmt6358_irq_sp_handler(chip, i);\n \t\t\ttop_irq_status &= ~bit;\n@@ -180,17 +190,18 @@ int mt6358_irq_init(struct mt6397_chip *chip)\n \tint i, j, ret;\n \tstruct pmic_irq_data *irqd;\n \n-\tirqd = devm_kzalloc(chip->dev, sizeof(*irqd), GFP_KERNEL);\n-\tif (!irqd)\n-\t\treturn -ENOMEM;\n+\tswitch (chip->chip_id) {\n+\tcase MT6358_CHIP_ID:\n+\t\tchip->irq_data = &mt6358_irqd;\n+\t\tbreak;\n \n-\tchip->irq_data = irqd;\n+\tdefault:\n+\t\tdev_err(chip->dev, \"unsupported chip: 0x%x\\n\", chip->chip_id);\n+\t\treturn -ENODEV;\n+\t}\n \n \tmutex_init(&chip->irqlock);\n-\tirqd->top_int_status_reg = MT6358_TOP_INT_STATUS0;\n-\tirqd->num_pmic_irqs = MT6358_IRQ_NR;\n-\tirqd->num_top = ARRAY_SIZE(mt6358_ints);\n-\n+\tirqd = chip->irq_data;\n \tirqd->enable_hwirq = devm_kcalloc(chip->dev,\n \t\t\t\t\t irqd->num_pmic_irqs,\n \t\t\t\t\t sizeof(*irqd->enable_hwirq),\n@@ -207,10 +218,10 @@ int mt6358_irq_init(struct mt6397_chip *chip)\n \n \t/* Disable all interrupts for initializing */\n \tfor (i = 0; i < irqd->num_top; i++) {\n-\t\tfor (j = 0; j < mt6358_ints[i].num_int_regs; j++)\n+\t\tfor (j = 0; j < irqd->pmic_ints[i].num_int_regs; j++)\n \t\t\tregmap_write(chip->regmap,\n-\t\t\t\t mt6358_ints[i].en_reg +\n-\t\t\t\t mt6358_ints[i].en_reg_shift * j, 0);\n+\t\t\t\t irqd->pmic_ints[i].en_reg +\n+\t\t\t\t irqd->pmic_ints[i].en_reg_shift * j, 0);\n \t}\n \n \tchip->irq_domain = irq_domain_add_linear(chip->dev->of_node,\ndiff --git a/include/linux/mfd/mt6358/core.h b/include/linux/mfd/mt6358/core.h\nindex c5a11b7..68578e2 100644\n--- a/include/linux/mfd/mt6358/core.h\n+++ b/include/linux/mfd/mt6358/core.h\n@@ -6,12 +6,9 @@\n #ifndef __MFD_MT6358_CORE_H__\n #define __MFD_MT6358_CORE_H__\n \n-#define MT6358_REG_WIDTH 16\n-\n struct irq_top_t {\n \tint hwirq_base;\n \tunsigned int num_int_regs;\n-\tunsigned int num_int_bits;\n \tunsigned int en_reg;\n \tunsigned int en_reg_shift;\n \tunsigned int sta_reg;\n@@ -25,6 +22,7 @@ struct pmic_irq_data {\n \tunsigned short top_int_status_reg;\n \tbool *enable_hwirq;\n \tbool *cache_hwirq;\n+\tconst struct irq_top_t *pmic_ints;\n };\n \n enum mt6358_irq_top_status_shift {\n@@ -146,8 +144,8 @@ enum mt6358_irq_numbers {\n {\t\\\n \t.hwirq_base = MT6358_IRQ_##sp##_BASE,\t\\\n \t.num_int_regs =\t\\\n-\t\t((MT6358_IRQ_##sp##_BITS - 1) / MT6358_REG_WIDTH) + 1,\t\\\n-\t.num_int_bits = MT6358_IRQ_##sp##_BITS, \\\n+\t\t((MT6358_IRQ_##sp##_BITS - 1) /\t\\\n+\t\tMTK_PMIC_REG_WIDTH) + 1,\t\\\n \t.en_reg = MT6358_##sp##_TOP_INT_CON0,\t\\\n \t.en_reg_shift = 0x6,\t\\\n \t.sta_reg = MT6358_##sp##_TOP_INT_STATUS0,\t\\\n", "prefixes": [ "v8", "1/8" ] }