Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1483906/?format=api
{ "id": 1483906, "url": "http://patchwork.ozlabs.org/api/patches/1483906/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/patch/1622011927-359-3-git-send-email-hsin-hsiung.wang@mediatek.com/", "project": { "id": 9, "url": "http://patchwork.ozlabs.org/api/projects/9/?format=api", "name": "Linux RTC development", "link_name": "rtc-linux", "list_id": "linux-rtc.vger.kernel.org", "list_email": "linux-rtc@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1622011927-359-3-git-send-email-hsin-hsiung.wang@mediatek.com>", "list_archive_url": null, "date": "2021-05-26T06:52:01", "name": "[v8,2/8] rtc: mt6397: refine RTC_TC_MTH", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "f807ff9ef1368a5a98dec145018fcd7412cc41ae", "submitter": { "id": 74946, "url": "http://patchwork.ozlabs.org/api/people/74946/?format=api", "name": "Hsin-Hsiung Wang", "email": "hsin-hsiung.wang@mediatek.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/rtc-linux/patch/1622011927-359-3-git-send-email-hsin-hsiung.wang@mediatek.com/mbox/", "series": [ { "id": 245778, "url": "http://patchwork.ozlabs.org/api/series/245778/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/list/?series=245778", "date": "2021-05-26T06:52:02", "name": "Add Support for MediaTek PMIC MT6359", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/245778/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1483906/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1483906/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-rtc-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=23.128.96.18; helo=vger.kernel.org;\n envelope-from=linux-rtc-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [23.128.96.18])\n\tby ozlabs.org (Postfix) with ESMTP id 4FqhTK12tGz9sV5\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 26 May 2021 16:52:21 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S232919AbhEZGxt (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n Wed, 26 May 2021 02:53:49 -0400", "from mailgw01.mediatek.com ([210.61.82.183]:37230 \"EHLO\n mailgw01.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org\n with ESMTP id S232869AbhEZGxs (ORCPT\n <rfc822;linux-rtc@vger.kernel.org>); Wed, 26 May 2021 02:53:48 -0400", "from mtkcas11.mediatek.inc [(172.21.101.40)] by\n mailgw01.mediatek.com\n (envelope-from <hsin-hsiung.wang@mediatek.com>)\n (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256)\n with ESMTP id 941265013; Wed, 26 May 2021 14:52:13 +0800", "from mtkcas11.mediatek.inc (172.21.101.40) by\n mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Wed, 26 May 2021 14:52:12 +0800", "from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas11.mediatek.inc\n (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 26 May 2021 14:52:12 +0800" ], "X-UUID": [ "bbcbee18ddf841739a1cc09ddd5a1bd2-20210526", "bbcbee18ddf841739a1cc09ddd5a1bd2-20210526" ], "From": "Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>", "To": "Lee Jones <lee.jones@linaro.org>, Rob Herring <robh+dt@kernel.org>,\n Matthias Brugger <matthias.bgg@gmail.com>,\n Liam Girdwood <lgirdwood@gmail.com>,\n Mark Brown <broonie@kernel.org>,\n Eddie Huang <eddie.huang@mediatek.com>,\n Alessandro Zummo <a.zummo@towertech.it>,\n Alexandre Belloni <alexandre.belloni@bootlin.com>,\n Fei Shao <fshao@chromium.org>", "CC": "Sean Wang <sean.wang@mediatek.com>,\n Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>,\n Yuchen Huang <yuchen.huang@mediatek.com>,\n <devicetree@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>,\n <linux-mediatek@lists.infradead.org>,\n <linux-kernel@vger.kernel.org>, <linux-rtc@vger.kernel.org>,\n <srv_heupstream@mediatek.com>,\n <Project_Global_Chrome_Upstream_Group@mediatek.com>", "Subject": "[PATCH v8 2/8] rtc: mt6397: refine RTC_TC_MTH", "Date": "Wed, 26 May 2021 14:52:01 +0800", "Message-ID": "<1622011927-359-3-git-send-email-hsin-hsiung.wang@mediatek.com>", "X-Mailer": "git-send-email 2.6.4", "In-Reply-To": "<1622011927-359-1-git-send-email-hsin-hsiung.wang@mediatek.com>", "References": "<1622011927-359-1-git-send-email-hsin-hsiung.wang@mediatek.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MTK": "N", "Precedence": "bulk", "List-ID": "<linux-rtc.vger.kernel.org>", "X-Mailing-List": "linux-rtc@vger.kernel.org" }, "content": "This patch adds RTC_TC_MTH_MASK to support new chips.\n\nSigned-off-by: Yuchen Huang <yuchen.huang@mediatek.com>\nSigned-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>\nAcked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>\n---\nchanges since v7:\n- no change.\n---\n drivers/rtc/rtc-mt6397.c | 2 +-\n include/linux/mfd/mt6397/rtc.h | 1 +\n 2 files changed, 2 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c\nindex 6655035..80dc479 100644\n--- a/drivers/rtc/rtc-mt6397.c\n+++ b/drivers/rtc/rtc-mt6397.c\n@@ -75,7 +75,7 @@ static int __mtk_rtc_read_time(struct mt6397_rtc *rtc,\n \ttm->tm_min = data[RTC_OFFSET_MIN];\n \ttm->tm_hour = data[RTC_OFFSET_HOUR];\n \ttm->tm_mday = data[RTC_OFFSET_DOM];\n-\ttm->tm_mon = data[RTC_OFFSET_MTH];\n+\ttm->tm_mon = data[RTC_OFFSET_MTH] & RTC_TC_MTH_MASK;\n \ttm->tm_year = data[RTC_OFFSET_YEAR];\n \n \tret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec);\ndiff --git a/include/linux/mfd/mt6397/rtc.h b/include/linux/mfd/mt6397/rtc.h\nindex c3748b5..068ae1c 100644\n--- a/include/linux/mfd/mt6397/rtc.h\n+++ b/include/linux/mfd/mt6397/rtc.h\n@@ -36,6 +36,7 @@\n #define RTC_AL_MASK_DOW BIT(4)\n \n #define RTC_TC_SEC 0x000a\n+#define RTC_TC_MTH_MASK 0x000f\n /* Min, Hour, Dom... register offset to RTC_TC_SEC */\n #define RTC_OFFSET_SEC 0\n #define RTC_OFFSET_MIN 1\n", "prefixes": [ "v8", "2/8" ] }