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GET /api/patches/1475772/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
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{
    "id": 1475772,
    "url": "http://patchwork.ozlabs.org/api/patches/1475772/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-58-richard.henderson@linaro.org/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20210508014802.892561-58-richard.henderson@linaro.org>",
    "list_archive_url": null,
    "date": "2021-05-08T01:47:47",
    "name": "[57/72] softfloat: Adjust parts_uncanon_normal for floatx80",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "0d070a5768dde3df27f83d3635c9125eb6f5e248",
    "submitter": {
        "id": 72104,
        "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api",
        "name": "Richard Henderson",
        "email": "richard.henderson@linaro.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-58-richard.henderson@linaro.org/mbox/",
    "series": [
        {
            "id": 242770,
            "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770",
            "date": "2021-05-08T01:46:53",
            "name": "Convert floatx80 and float128 to FloatParts",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1475772/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1475772/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Richard Henderson <richard.henderson@linaro.org>",
        "To": "qemu-devel@nongnu.org",
        "Subject": "[PATCH 57/72] softfloat: Adjust parts_uncanon_normal for floatx80",
        "Date": "Fri,  7 May 2021 18:47:47 -0700",
        "Message-Id": "<20210508014802.892561-58-richard.henderson@linaro.org>",
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        "In-Reply-To": "<20210508014802.892561-1-richard.henderson@linaro.org>",
        "References": "<20210508014802.892561-1-richard.henderson@linaro.org>",
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        "Cc": "alex.bennee@linaro.org, david@redhat.com",
        "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org",
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    },
    "content": "With floatx80_precision_x, the rounding happens across\nthe break between words.  Notice this case with\n\n  frac_lsb = round_mask + 1 -> 0\n\nand check the bits in frac_hi as needed.\n\nIn addition, since frac_shift == 0, we won't implicitly clear\nround_mask via the right-shift, so explicitly clear those bits.\nThis fixes rounding for floatx80_precision_[sd].\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat-parts.c.inc | 36 ++++++++++++++++++++++++++++++------\n 1 file changed, 30 insertions(+), 6 deletions(-)",
    "diff": "diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex 3ee6552d5a..c18f77f2cf 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -156,7 +156,13 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,\n     switch (s->float_rounding_mode) {\n     case float_round_nearest_even:\n         overflow_norm = false;\n-        inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1 ? frac_lsbm1 : 0);\n+        if (N > 64 && frac_lsb == 0) {\n+            inc = ((p->frac_hi & 1) || (p->frac_lo & round_mask) != frac_lsbm1\n+                   ? frac_lsbm1 : 0);\n+        } else {\n+            inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1\n+                   ? frac_lsbm1 : 0);\n+        }\n         break;\n     case float_round_ties_away:\n         overflow_norm = false;\n@@ -176,7 +182,11 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,\n         break;\n     case float_round_to_odd:\n         overflow_norm = true;\n-        inc = p->frac_lo & frac_lsb ? 0 : round_mask;\n+        if (N > 64 && frac_lsb == 0) {\n+            inc = p->frac_hi & 1 ? 0 : round_mask;\n+        } else {\n+            inc = p->frac_lo & frac_lsb ? 0 : round_mask;\n+        }\n         break;\n     default:\n         g_assert_not_reached();\n@@ -191,8 +201,8 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,\n                 p->frac_hi |= DECOMPOSED_IMPLICIT_BIT;\n                 exp++;\n             }\n+            p->frac_lo &= ~round_mask;\n         }\n-        frac_shr(p, frac_shift);\n \n         if (fmt->arm_althp) {\n             /* ARM Alt HP eschews Inf and NaN for a wider exponent.  */\n@@ -201,18 +211,21 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,\n                 flags = float_flag_invalid;\n                 exp = exp_max;\n                 frac_allones(p);\n+                p->frac_lo &= ~round_mask;\n             }\n         } else if (unlikely(exp >= exp_max)) {\n             flags |= float_flag_overflow | float_flag_inexact;\n             if (overflow_norm) {\n                 exp = exp_max - 1;\n                 frac_allones(p);\n+                p->frac_lo &= ~round_mask;\n             } else {\n                 p->cls = float_class_inf;\n                 exp = exp_max;\n                 frac_clear(p);\n             }\n         }\n+        frac_shr(p, frac_shift);\n     } else if (s->flush_to_zero) {\n         flags |= float_flag_output_denormal;\n         p->cls = float_class_zero;\n@@ -232,17 +245,28 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,\n             /* Need to recompute round-to-even/round-to-odd. */\n             switch (s->float_rounding_mode) {\n             case float_round_nearest_even:\n-                inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1\n-                       ? frac_lsbm1 : 0);\n+                if (N > 64 && frac_lsb == 0) {\n+                    inc = ((p->frac_hi & 1) ||\n+                           (p->frac_lo & round_mask) != frac_lsbm1\n+                           ? frac_lsbm1 : 0);\n+                } else {\n+                    inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1\n+                           ? frac_lsbm1 : 0);\n+                }\n                 break;\n             case float_round_to_odd:\n-                inc = p->frac_lo & frac_lsb ? 0 : round_mask;\n+                if (N > 64 && frac_lsb == 0) {\n+                    inc = p->frac_hi & 1 ? 0 : round_mask;\n+                } else {\n+                    inc = p->frac_lo & frac_lsb ? 0 : round_mask;\n+                }\n                 break;\n             default:\n                 break;\n             }\n             flags |= float_flag_inexact;\n             frac_addi(p, p, inc);\n+            p->frac_lo &= ~round_mask;\n         }\n \n         exp = (p->frac_hi & DECOMPOSED_IMPLICIT_BIT) != 0;\n",
    "prefixes": [
        "57/72"
    ]
}