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GET /api/patches/1475771/?format=api
{ "id": 1475771, "url": "http://patchwork.ozlabs.org/api/patches/1475771/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-72-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-72-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:48:01", "name": "[71/72] softfloat: Move floatN_log2 to softfloat-parts.c.inc", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "79c9f527cfa785461902ef8be1a2abfe81bb4161", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-72-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475771/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475771/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pg1-x535.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Rename to parts$N_log2. Though this is partly a ruse, since I do not\nbelieve the code will succeed for float128 without work. Which is ok\nfor now, because we do not need this for more than float32 and float64.\n\nSince berkeley-testfloat-3 doesn't support log2, compare float64_log2\nvs the system log2. Fix the errors for inputs near 1.0:\n\ntest: 3ff00000000000b0 +0x1.00000000000b0p+0\n sf: 3d2fa00000000000 +0x1.fa00000000000p-45\nlibm: 3d2fbd422b1bd36f +0x1.fbd422b1bd36fp-45\nError in fraction: 32170028290927 ulp\n\ntest: 3feec24f6770b100 +0x1.ec24f6770b100p-1\n sf: bfad3740d13c9ec0 -0x1.d3740d13c9ec0p-5\nlibm: bfad3740d13c9e98 -0x1.d3740d13c9e98p-5\nError in fraction: 40 ulp\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat.c | 126 ++++++++------------------------------\n tests/fp/fp-test-log2.c | 118 +++++++++++++++++++++++++++++++++++\n fpu/softfloat-parts.c.inc | 125 +++++++++++++++++++++++++++++++++++++\n tests/fp/meson.build | 11 ++++\n 4 files changed, 281 insertions(+), 99 deletions(-)\n create mode 100644 tests/fp/fp-test-log2.c", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 906bb427ae..3823a7ec6f 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -926,6 +926,12 @@ static void parts128_scalbn(FloatParts128 *a, int n, float_status *s);\n #define parts_scalbn(A, N, S) \\\n PARTS_GENERIC_64_128(scalbn, A)(A, N, S)\n \n+static void parts64_log2(FloatParts64 *a, float_status *s, const FloatFmt *f);\n+static void parts128_log2(FloatParts128 *a, float_status *s, const FloatFmt *f);\n+\n+#define parts_log2(A, S, F) \\\n+ PARTS_GENERIC_64_128(log2, A)(A, S, F)\n+\n /*\n * Helper functions for softfloat-parts.c.inc, per-size operations.\n */\n@@ -4062,6 +4068,27 @@ floatx80 floatx80_sqrt(floatx80 a, float_status *s)\n return floatx80_round_pack_canonical(&p, s);\n }\n \n+/*\n+ * log2\n+ */\n+float32 float32_log2(float32 a, float_status *status)\n+{\n+ FloatParts64 p;\n+\n+ float32_unpack_canonical(&p, a, status);\n+ parts_log2(&p, status, &float32_params);\n+ return float32_round_pack_canonical(&p, status);\n+}\n+\n+float64 float64_log2(float64 a, float_status *status)\n+{\n+ FloatParts64 p;\n+\n+ float64_unpack_canonical(&p, a, status);\n+ parts_log2(&p, status, &float64_params);\n+ return float64_round_pack_canonical(&p, status);\n+}\n+\n /*----------------------------------------------------------------------------\n | The pattern for a default generated NaN.\n *----------------------------------------------------------------------------*/\n@@ -5248,56 +5275,6 @@ float32 float32_exp2(float32 a, float_status *status)\n return float32_round_pack_canonical(&rp, status);\n }\n \n-/*----------------------------------------------------------------------------\n-| Returns the binary log of the single-precision floating-point value `a'.\n-| The operation is performed according to the IEC/IEEE Standard for Binary\n-| Floating-Point Arithmetic.\n-*----------------------------------------------------------------------------*/\n-float32 float32_log2(float32 a, float_status *status)\n-{\n- bool aSign, zSign;\n- int aExp;\n- uint32_t aSig, zSig, i;\n-\n- a = float32_squash_input_denormal(a, status);\n- aSig = extractFloat32Frac( a );\n- aExp = extractFloat32Exp( a );\n- aSign = extractFloat32Sign( a );\n-\n- if ( aExp == 0 ) {\n- if ( aSig == 0 ) return packFloat32( 1, 0xFF, 0 );\n- normalizeFloat32Subnormal( aSig, &aExp, &aSig );\n- }\n- if ( aSign ) {\n- float_raise(float_flag_invalid, status);\n- return float32_default_nan(status);\n- }\n- if ( aExp == 0xFF ) {\n- if (aSig) {\n- return propagateFloat32NaN(a, float32_zero, status);\n- }\n- return a;\n- }\n-\n- aExp -= 0x7F;\n- aSig |= 0x00800000;\n- zSign = aExp < 0;\n- zSig = aExp << 23;\n-\n- for (i = 1 << 22; i > 0; i >>= 1) {\n- aSig = ( (uint64_t)aSig * aSig ) >> 23;\n- if ( aSig & 0x01000000 ) {\n- aSig >>= 1;\n- zSig |= i;\n- }\n- }\n-\n- if ( zSign )\n- zSig = -zSig;\n-\n- return normalizeRoundAndPackFloat32(zSign, 0x85, zSig, status);\n-}\n-\n /*----------------------------------------------------------------------------\n | Returns the remainder of the double-precision floating-point value `a'\n | with respect to the corresponding value `b'. The operation is performed\n@@ -5386,55 +5363,6 @@ float64 float64_rem(float64 a, float64 b, float_status *status)\n \n }\n \n-/*----------------------------------------------------------------------------\n-| Returns the binary log of the double-precision floating-point value `a'.\n-| The operation is performed according to the IEC/IEEE Standard for Binary\n-| Floating-Point Arithmetic.\n-*----------------------------------------------------------------------------*/\n-float64 float64_log2(float64 a, float_status *status)\n-{\n- bool aSign, zSign;\n- int aExp;\n- uint64_t aSig, aSig0, aSig1, zSig, i;\n- a = float64_squash_input_denormal(a, status);\n-\n- aSig = extractFloat64Frac( a );\n- aExp = extractFloat64Exp( a );\n- aSign = extractFloat64Sign( a );\n-\n- if ( aExp == 0 ) {\n- if ( aSig == 0 ) return packFloat64( 1, 0x7FF, 0 );\n- normalizeFloat64Subnormal( aSig, &aExp, &aSig );\n- }\n- if ( aSign ) {\n- float_raise(float_flag_invalid, status);\n- return float64_default_nan(status);\n- }\n- if ( aExp == 0x7FF ) {\n- if (aSig) {\n- return propagateFloat64NaN(a, float64_zero, status);\n- }\n- return a;\n- }\n-\n- aExp -= 0x3FF;\n- aSig |= UINT64_C(0x0010000000000000);\n- zSign = aExp < 0;\n- zSig = (uint64_t)aExp << 52;\n- for (i = 1LL << 51; i > 0; i >>= 1) {\n- mul64To128( aSig, aSig, &aSig0, &aSig1 );\n- aSig = ( aSig0 << 12 ) | ( aSig1 >> 52 );\n- if ( aSig & UINT64_C(0x0020000000000000) ) {\n- aSig >>= 1;\n- zSig |= i;\n- }\n- }\n-\n- if ( zSign )\n- zSig = -zSig;\n- return normalizeRoundAndPackFloat64(zSign, 0x408, zSig, status);\n-}\n-\n /*----------------------------------------------------------------------------\n | Rounds the extended double-precision floating-point value `a'\n | to the precision provided by floatx80_rounding_precision and returns the\ndiff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c\nnew file mode 100644\nindex 0000000000..8ad856509b\n--- /dev/null\n+++ b/tests/fp/fp-test-log2.c\n@@ -0,0 +1,118 @@\n+/*\n+ * fp-test-log2.c - test QEMU's softfloat log2\n+ *\n+ * Copyright (C) 2020, Linaro, Ltd.\n+ *\n+ * License: GNU GPL, version 2 or later.\n+ * See the COPYING file in the top-level directory.\n+ */\n+#ifndef HW_POISON_H\n+#error Must define HW_POISON_H to work around TARGET_* poisoning\n+#endif\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/cutils.h\"\n+#include <math.h>\n+#include \"fpu/softfloat.h\"\n+\n+typedef union {\n+ double d;\n+ float64 i;\n+} ufloat64;\n+\n+static int errors;\n+\n+static void compare(ufloat64 test, ufloat64 real, ufloat64 soft, bool exact)\n+{\n+ int msb;\n+ uint64_t ulp = UINT64_MAX;\n+\n+ if (real.i == soft.i) {\n+ return;\n+ }\n+ msb = 63 - __builtin_clzll(real.i ^ soft.i);\n+\n+ if (msb < 52) {\n+ if (real.i > soft.i) {\n+ ulp = real.i - soft.i;\n+ } else {\n+ ulp = soft.i - real.i;\n+ }\n+ }\n+\n+ /* glibc allows 3 ulp error in its libm-test-ulps; allow 4 here */\n+ if (!exact && ulp <= 4) {\n+ return;\n+ }\n+ \n+ printf(\"test: %016\" PRIx64 \" %+.13a\\n\"\n+ \" sf: %016\" PRIx64 \" %+.13a\\n\"\n+ \"libm: %016\" PRIx64 \" %+.13a\\n\",\n+ test.i, test.d, soft.i, soft.d, real.i, real.d);\n+\n+ if (msb == 63) {\n+ printf(\"Error in sign!\\n\\n\");\n+ } else if (msb >= 52) {\n+ printf(\"Error in exponent: %d\\n\\n\",\n+ (int)(soft.i >> 52) - (int)(real.i >> 52));\n+ } else {\n+ printf(\"Error in fraction: %\" PRIu64 \" ulp\\n\\n\", ulp);\n+ }\n+\n+ if (++errors == 20) {\n+ exit(1);\n+ }\n+}\n+\n+int main(int ac, char **av)\n+{\n+ ufloat64 test, real, soft;\n+ float_status qsf = {0};\n+ int i;\n+\n+ set_float_rounding_mode(float_round_nearest_even, &qsf);\n+\n+ test.d = 0.0;\n+ real.d = -__builtin_inf();\n+ soft.i = float64_log2(test.i, &qsf);\n+ compare(test, real, soft, true);\n+\n+ test.d = 1.0;\n+ real.d = 0.0;\n+ soft.i = float64_log2(test.i, &qsf);\n+ compare(test, real, soft, true);\n+\n+ test.d = 2.0;\n+ real.d = 1.0;\n+ soft.i = float64_log2(test.i, &qsf);\n+ compare(test, real, soft, true);\n+\n+ test.d = 4.0;\n+ real.d = 2.0;\n+ soft.i = float64_log2(test.i, &qsf);\n+ compare(test, real, soft, true);\n+\n+ test.d = 0x1p64;\n+ real.d = 64.0;\n+ soft.i = float64_log2(test.i, &qsf);\n+ compare(test, real, soft, true);\n+\n+ test.d = __builtin_inf();\n+ real.d = __builtin_inf();\n+ soft.i = float64_log2(test.i, &qsf);\n+ compare(test, real, soft, true);\n+\n+ for (i = 0; i < 10000; ++i) {\n+ test.d = drand48() + 1.0; /* [1.0, 2.0) */\n+ real.d = log2(test.d);\n+ soft.i = float64_log2(test.i, &qsf);\n+ compare(test, real, soft, false);\n+\n+ test.d = drand48() * 100; /* [0.0, 100) */\n+ real.d = log2(test.d);\n+ soft.i = float64_log2(test.i, &qsf);\n+ compare(test, real, soft, false);\n+ }\n+\n+ return 0;\n+}\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex c18f77f2cf..3659c6a4c0 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -1319,3 +1319,128 @@ static void partsN(scalbn)(FloatPartsN *a, int n, float_status *s)\n g_assert_not_reached();\n }\n }\n+\n+/*\n+ * Return log2(A)\n+ */\n+static void partsN(log2)(FloatPartsN *a, float_status *s, const FloatFmt *fmt)\n+{\n+ uint64_t a0, a1, r, t, ign;\n+ FloatPartsN f;\n+ int i, n, a_exp, f_exp;\n+\n+ if (unlikely(a->cls != float_class_normal)) {\n+ switch (a->cls) {\n+ case float_class_snan:\n+ case float_class_qnan:\n+ parts_return_nan(a, s);\n+ return;\n+ case float_class_zero:\n+ /* log2(0) = -inf */\n+ a->cls = float_class_inf;\n+ a->sign = 1;\n+ return;\n+ case float_class_inf:\n+ if (unlikely(a->sign)) {\n+ goto d_nan;\n+ }\n+ return;\n+ default:\n+ break;\n+ }\n+ g_assert_not_reached();\n+ }\n+ if (unlikely(a->sign)) {\n+ goto d_nan;\n+ }\n+\n+ /* TODO: This algorithm looses bits too quickly for float128. */\n+ g_assert(N == 64);\n+\n+ a_exp = a->exp;\n+ f_exp = -1;\n+\n+ r = 0;\n+ t = DECOMPOSED_IMPLICIT_BIT;\n+ a0 = a->frac_hi;\n+ a1 = 0;\n+\n+ n = fmt->frac_size + 2;\n+ if (unlikely(a_exp == -1)) {\n+ /*\n+ * When a_exp == -1, we're computing the log2 of a value [0.5,1.0).\n+ * When the value is very close to 1.0, there are lots of 1's in\n+ * the msb parts of the fraction. At the end, when we subtract\n+ * this value from -1.0, we can see a catastrophic loss of precision,\n+ * as 0x800..000 - 0x7ff..ffx becomes 0x000..00y, leaving only the\n+ * bits of y in the final result. To minimize this, compute as many\n+ * digits as we can.\n+ * ??? This case needs another algorithm to avoid this.\n+ */\n+ n = fmt->frac_size * 2 + 2;\n+ /* Don't compute a value overlapping the sticky bit */\n+ n = MIN(n, 62);\n+ }\n+\n+ for (i = 0; i < n; i++) {\n+ if (a1) {\n+ mul128To256(a0, a1, a0, a1, &a0, &a1, &ign, &ign);\n+ } else if (a0 & 0xffffffffull) {\n+ mul64To128(a0, a0, &a0, &a1);\n+ } else if (a0 & ~DECOMPOSED_IMPLICIT_BIT) {\n+ a0 >>= 32;\n+ a0 *= a0;\n+ } else {\n+ goto exact;\n+ }\n+\n+ if (a0 & DECOMPOSED_IMPLICIT_BIT) {\n+ if (unlikely(a_exp == 0 && r == 0)) {\n+ /*\n+ * When a_exp == 0, we're computing the log2 of a value\n+ * [1.0,2.0). When the value is very close to 1.0, there\n+ * are lots of 0's in the msb parts of the fraction.\n+ * We need to compute more digits to produce a correct\n+ * result -- restart at the top of the fraction.\n+ * ??? This is likely to lose precision quickly, as for\n+ * float128; we may need another method.\n+ */\n+ f_exp -= i;\n+ t = r = DECOMPOSED_IMPLICIT_BIT;\n+ i = 0;\n+ } else {\n+ r |= t;\n+ }\n+ } else {\n+ add128(a0, a1, a0, a1, &a0, &a1);\n+ }\n+ t >>= 1;\n+ }\n+\n+ /* Set sticky for inexact. */\n+ r |= (a1 || a0 & ~DECOMPOSED_IMPLICIT_BIT);\n+\n+ exact:\n+ parts_sint_to_float(a, a_exp, 0, s);\n+ if (r == 0) {\n+ return;\n+ }\n+\n+ memset(&f, 0, sizeof(f));\n+ f.cls = float_class_normal;\n+ f.frac_hi = r;\n+ f.exp = f_exp - frac_normalize(&f);\n+\n+ if (a_exp < 0) {\n+ parts_sub_normal(a, &f);\n+ } else if (a_exp > 0) {\n+ parts_add_normal(a, &f);\n+ } else {\n+ *a = f;\n+ }\n+ return;\n+\n+ d_nan:\n+ float_raise(float_flag_invalid, s);\n+ parts_default_nan(a, s);\n+}\ndiff --git a/tests/fp/meson.build b/tests/fp/meson.build\nindex 1c3eee9955..9218bfd3b0 100644\n--- a/tests/fp/meson.build\n+++ b/tests/fp/meson.build\n@@ -634,3 +634,14 @@ fpbench = executable(\n include_directories: [sfinc, include_directories(tfdir)],\n c_args: fpcflags,\n )\n+\n+fptestlog2 = executable(\n+ 'fp-test-log2',\n+ ['fp-test-log2.c', '../../fpu/softfloat.c'],\n+ link_with: [libsoftfloat],\n+ dependencies: [qemuutil],\n+ include_directories: [sfinc],\n+ c_args: fpcflags,\n+)\n+test('fp-test-log2', fptestlog2,\n+ suite: ['softfloat', 'softfloat-ops'])\n", "prefixes": [ "71/72" ] }