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GET /api/patches/1475753/?format=api
{ "id": 1475753, "url": "http://patchwork.ozlabs.org/api/patches/1475753/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-44-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-44-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:47:33", "name": "[43/72] softfloat: Split float_to_float", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b27f3560af17dd35ed6ee3f95da6bd14ad8081bd", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-44-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475753/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475753/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x102d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Split out parts_float_to_ahp and parts_float_to_float.\nConvert to pointers.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat.c | 174 ++++++++++++++++++++++++++++--------------------\n 1 file changed, 101 insertions(+), 73 deletions(-)", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 8efa52f7ec..06fac8f41c 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -2036,83 +2036,105 @@ float128_div(float128 a, float128 b, float_status *status)\n * conversion is performed according to the IEC/IEEE Standard for\n * Binary Floating-Point Arithmetic.\n *\n- * The float_to_float helper only needs to take care of raising\n- * invalid exceptions and handling the conversion on NaNs.\n+ * Usually this only needs to take care of raising invalid exceptions\n+ * and handling the conversion on NaNs.\n */\n \n-static FloatParts64 float_to_float(FloatParts64 a, const FloatFmt *dstf,\n- float_status *s)\n+static void parts_float_to_ahp(FloatParts64 *a, float_status *s)\n {\n- if (dstf->arm_althp) {\n- switch (a.cls) {\n- case float_class_qnan:\n- case float_class_snan:\n- /* There is no NaN in the destination format. Raise Invalid\n- * and return a zero with the sign of the input NaN.\n- */\n- float_raise(float_flag_invalid, s);\n- a.cls = float_class_zero;\n- a.frac = 0;\n- a.exp = 0;\n- break;\n+ switch (a->cls) {\n+ case float_class_qnan:\n+ case float_class_snan:\n+ /*\n+ * There is no NaN in the destination format. Raise Invalid\n+ * and return a zero with the sign of the input NaN.\n+ */\n+ float_raise(float_flag_invalid, s);\n+ a->cls = float_class_zero;\n+ break;\n \n- case float_class_inf:\n- /* There is no Inf in the destination format. Raise Invalid\n- * and return the maximum normal with the correct sign.\n- */\n- float_raise(float_flag_invalid, s);\n- a.cls = float_class_normal;\n- a.exp = dstf->exp_max;\n- a.frac = ((1ull << dstf->frac_size) - 1) << dstf->frac_shift;\n- break;\n+ case float_class_inf:\n+ /*\n+ * There is no Inf in the destination format. Raise Invalid\n+ * and return the maximum normal with the correct sign.\n+ */\n+ float_raise(float_flag_invalid, s);\n+ a->cls = float_class_normal;\n+ a->exp = float16_params_ahp.exp_max;\n+ a->frac = MAKE_64BIT_MASK(float16_params_ahp.frac_shift,\n+ float16_params_ahp.frac_size + 1);\n+ break;\n \n- default:\n- break;\n- }\n- } else if (is_nan(a.cls)) {\n- parts_return_nan(&a, s);\n+ case float_class_normal:\n+ case float_class_zero:\n+ break;\n+\n+ default:\n+ g_assert_not_reached();\n }\n- return a;\n }\n \n+static void parts64_float_to_float(FloatParts64 *a, float_status *s)\n+{\n+ if (is_nan(a->cls)) {\n+ parts_return_nan(a, s);\n+ }\n+}\n+\n+static void parts128_float_to_float(FloatParts128 *a, float_status *s)\n+{\n+ if (is_nan(a->cls)) {\n+ parts_return_nan(a, s);\n+ }\n+}\n+\n+#define parts_float_to_float(P, S) \\\n+ PARTS_GENERIC_64_128(float_to_float, P)(P, S)\n+\n float32 float16_to_float32(float16 a, bool ieee, float_status *s)\n {\n const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp;\n- FloatParts64 pa, pr;\n+ FloatParts64 p;\n \n- float16a_unpack_canonical(&pa, a, s, fmt16);\n- pr = float_to_float(pa, &float32_params, s);\n- return float32_round_pack_canonical(&pr, s);\n+ float16a_unpack_canonical(&p, a, s, fmt16);\n+ parts_float_to_float(&p, s);\n+ return float32_round_pack_canonical(&p, s);\n }\n \n float64 float16_to_float64(float16 a, bool ieee, float_status *s)\n {\n const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp;\n- FloatParts64 pa, pr;\n+ FloatParts64 p;\n \n- float16a_unpack_canonical(&pa, a, s, fmt16);\n- pr = float_to_float(pa, &float64_params, s);\n- return float64_round_pack_canonical(&pr, s);\n+ float16a_unpack_canonical(&p, a, s, fmt16);\n+ parts_float_to_float(&p, s);\n+ return float64_round_pack_canonical(&p, s);\n }\n \n float16 float32_to_float16(float32 a, bool ieee, float_status *s)\n {\n- const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp;\n- FloatParts64 pa, pr;\n+ FloatParts64 p;\n+ const FloatFmt *fmt;\n \n- float32_unpack_canonical(&pa, a, s);\n- pr = float_to_float(pa, fmt16, s);\n- return float16a_round_pack_canonical(&pr, s, fmt16);\n+ float32_unpack_canonical(&p, a, s);\n+ if (ieee) {\n+ parts_float_to_float(&p, s);\n+ fmt = &float16_params;\n+ } else {\n+ parts_float_to_ahp(&p, s);\n+ fmt = &float16_params_ahp;\n+ }\n+ return float16a_round_pack_canonical(&p, s, fmt);\n }\n \n static float64 QEMU_SOFTFLOAT_ATTR\n soft_float32_to_float64(float32 a, float_status *s)\n {\n- FloatParts64 pa, pr;\n+ FloatParts64 p;\n \n- float32_unpack_canonical(&pa, a, s);\n- pr = float_to_float(pa, &float64_params, s);\n- return float64_round_pack_canonical(&pr, s);\n+ float32_unpack_canonical(&p, a, s);\n+ parts_float_to_float(&p, s);\n+ return float64_round_pack_canonical(&p, s);\n }\n \n float64 float32_to_float64(float32 a, float_status *s)\n@@ -2133,57 +2155,63 @@ float64 float32_to_float64(float32 a, float_status *s)\n \n float16 float64_to_float16(float64 a, bool ieee, float_status *s)\n {\n- const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp;\n- FloatParts64 pa, pr;\n+ FloatParts64 p;\n+ const FloatFmt *fmt;\n \n- float64_unpack_canonical(&pa, a, s);\n- pr = float_to_float(pa, fmt16, s);\n- return float16a_round_pack_canonical(&pr, s, fmt16);\n+ float64_unpack_canonical(&p, a, s);\n+ if (ieee) {\n+ parts_float_to_float(&p, s);\n+ fmt = &float16_params;\n+ } else {\n+ parts_float_to_ahp(&p, s);\n+ fmt = &float16_params_ahp;\n+ }\n+ return float16a_round_pack_canonical(&p, s, fmt);\n }\n \n float32 float64_to_float32(float64 a, float_status *s)\n {\n- FloatParts64 pa, pr;\n+ FloatParts64 p;\n \n- float64_unpack_canonical(&pa, a, s);\n- pr = float_to_float(pa, &float32_params, s);\n- return float32_round_pack_canonical(&pr, s);\n+ float64_unpack_canonical(&p, a, s);\n+ parts_float_to_float(&p, s);\n+ return float32_round_pack_canonical(&p, s);\n }\n \n float32 bfloat16_to_float32(bfloat16 a, float_status *s)\n {\n- FloatParts64 pa, pr;\n+ FloatParts64 p;\n \n- bfloat16_unpack_canonical(&pa, a, s);\n- pr = float_to_float(pa, &float32_params, s);\n- return float32_round_pack_canonical(&pr, s);\n+ bfloat16_unpack_canonical(&p, a, s);\n+ parts_float_to_float(&p, s);\n+ return float32_round_pack_canonical(&p, s);\n }\n \n float64 bfloat16_to_float64(bfloat16 a, float_status *s)\n {\n- FloatParts64 pa, pr;\n+ FloatParts64 p;\n \n- bfloat16_unpack_canonical(&pa, a, s);\n- pr = float_to_float(pa, &float64_params, s);\n- return float64_round_pack_canonical(&pr, s);\n+ bfloat16_unpack_canonical(&p, a, s);\n+ parts_float_to_float(&p, s);\n+ return float64_round_pack_canonical(&p, s);\n }\n \n bfloat16 float32_to_bfloat16(float32 a, float_status *s)\n {\n- FloatParts64 pa, pr;\n+ FloatParts64 p;\n \n- float32_unpack_canonical(&pa, a, s);\n- pr = float_to_float(pa, &bfloat16_params, s);\n- return bfloat16_round_pack_canonical(&pr, s);\n+ float32_unpack_canonical(&p, a, s);\n+ parts_float_to_float(&p, s);\n+ return bfloat16_round_pack_canonical(&p, s);\n }\n \n bfloat16 float64_to_bfloat16(float64 a, float_status *s)\n {\n- FloatParts64 pa, pr;\n+ FloatParts64 p;\n \n- float64_unpack_canonical(&pa, a, s);\n- pr = float_to_float(pa, &bfloat16_params, s);\n- return bfloat16_round_pack_canonical(&pr, s);\n+ float64_unpack_canonical(&p, a, s);\n+ parts_float_to_float(&p, s);\n+ return bfloat16_round_pack_canonical(&p, s);\n }\n \n /*\n", "prefixes": [ "43/72" ] }