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GET /api/patches/1475751/?format=api
{ "id": 1475751, "url": "http://patchwork.ozlabs.org/api/patches/1475751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-51-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-51-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:47:40", "name": "[50/72] softfloat: Move minmax_flags to softfloat-parts.c.inc", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "dc5e223fb6acd1072d371b2a42ca3554f813c4d0", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-51-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475751/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475751/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x1030.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Rename to parts$N_minmax. Combine 3 bool arguments to a bitmask,\nreturn a tri-state value to indicate nan vs unchanged operand.\nIntroduce ftype_minmax functions as a common optimization point.\nFold bfloat16 expansions into the same macro as the other types.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat.c | 216 ++++++++++++++++----------------------\n fpu/softfloat-parts.c.inc | 69 ++++++++++++\n 2 files changed, 158 insertions(+), 127 deletions(-)", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 586ea5d67a..4c04e88a3a 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -482,6 +482,15 @@ enum {\n float_cmask_anynan = float_cmask_qnan | float_cmask_snan,\n };\n \n+/* Flags for parts_minmax. */\n+enum {\n+ /* Set for minimum; clear for maximum. */\n+ minmax_ismin = 1,\n+ /* Set for the IEEE 754-2008 minNum() and maxNum() operations. */\n+ minmax_isnum = 2,\n+ /* Set for the IEEE 754-2008 minNumMag() and minNumMag() operations. */\n+ minmax_ismag = 4 | minmax_isnum\n+};\n \n /* Simple helpers for checking if, or what kind of, NaN we have */\n static inline __attribute__((unused)) bool is_nan(FloatClass c)\n@@ -864,6 +873,14 @@ static void parts128_uint_to_float(FloatParts128 *p, uint64_t a,\n #define parts_uint_to_float(P, I, Z, S) \\\n PARTS_GENERIC_64_128(uint_to_float, P)(P, I, Z, S)\n \n+static int parts64_minmax(FloatParts64 *a, FloatParts64 *b,\n+ float_status *s, int flags, const FloatFmt *fmt);\n+static int parts128_minmax(FloatParts128 *a, FloatParts128 *b,\n+ float_status *s, int flags, const FloatFmt *fmt);\n+\n+#define parts_minmax(A, B, S, Z, F) \\\n+ PARTS_GENERIC_64_128(minmax, A)(A, B, S, Z, F)\n+\n /*\n * Helper functions for softfloat-parts.c.inc, per-size operations.\n */\n@@ -3257,145 +3274,90 @@ float128 uint64_to_float128(uint64_t a, float_status *status)\n return float128_round_pack_canonical(&p, status);\n }\n \n-/* Float Min/Max */\n-/* min() and max() functions. These can't be implemented as\n- * 'compare and pick one input' because that would mishandle\n- * NaNs and +0 vs -0.\n- *\n- * minnum() and maxnum() functions. These are similar to the min()\n- * and max() functions but if one of the arguments is a QNaN and\n- * the other is numerical then the numerical argument is returned.\n- * SNaNs will get quietened before being returned.\n- * minnum() and maxnum correspond to the IEEE 754-2008 minNum()\n- * and maxNum() operations. min() and max() are the typical min/max\n- * semantics provided by many CPUs which predate that specification.\n- *\n- * minnummag() and maxnummag() functions correspond to minNumMag()\n- * and minNumMag() from the IEEE-754 2008.\n+/*\n+ * Minimum and maximum\n */\n-static FloatParts64 minmax_floats(FloatParts64 a, FloatParts64 b, bool ismin,\n- bool ieee, bool ismag, float_status *s)\n+\n+static float16 float16_minmax(float16 a, float16 b, float_status *s, int flags)\n {\n- if (unlikely(is_nan(a.cls) || is_nan(b.cls))) {\n- if (ieee) {\n- /* Takes two floating-point values `a' and `b', one of\n- * which is a NaN, and returns the appropriate NaN\n- * result. If either `a' or `b' is a signaling NaN,\n- * the invalid exception is raised.\n- */\n- if (is_snan(a.cls) || is_snan(b.cls)) {\n- return *parts_pick_nan(&a, &b, s);\n- } else if (is_nan(a.cls) && !is_nan(b.cls)) {\n- return b;\n- } else if (is_nan(b.cls) && !is_nan(a.cls)) {\n- return a;\n- }\n- }\n- return *parts_pick_nan(&a, &b, s);\n- } else {\n- int a_exp, b_exp;\n+ FloatParts64 pa, pb;\n+ int which;\n \n- switch (a.cls) {\n- case float_class_normal:\n- a_exp = a.exp;\n- break;\n- case float_class_inf:\n- a_exp = INT_MAX;\n- break;\n- case float_class_zero:\n- a_exp = INT_MIN;\n- break;\n- default:\n- g_assert_not_reached();\n- break;\n- }\n- switch (b.cls) {\n- case float_class_normal:\n- b_exp = b.exp;\n- break;\n- case float_class_inf:\n- b_exp = INT_MAX;\n- break;\n- case float_class_zero:\n- b_exp = INT_MIN;\n- break;\n- default:\n- g_assert_not_reached();\n- break;\n- }\n-\n- if (ismag && (a_exp != b_exp || a.frac != b.frac)) {\n- bool a_less = a_exp < b_exp;\n- if (a_exp == b_exp) {\n- a_less = a.frac < b.frac;\n- }\n- return a_less ^ ismin ? b : a;\n- }\n-\n- if (a.sign == b.sign) {\n- bool a_less = a_exp < b_exp;\n- if (a_exp == b_exp) {\n- a_less = a.frac < b.frac;\n- }\n- return a.sign ^ a_less ^ ismin ? b : a;\n- } else {\n- return a.sign ^ ismin ? b : a;\n- }\n+ float16_unpack_canonical(&pa, a, s);\n+ float16_unpack_canonical(&pb, b, s);\n+ which = parts_minmax(&pa, &pb, s, flags, &float16_params);\n+ if (unlikely(which < 0)) {\n+ /* Some sort of nan, need to repack default and silenced nans. */\n+ return float16_round_pack_canonical(&pa, s);\n }\n+ return which ? b : a;\n }\n \n-#define MINMAX(sz, name, ismin, isiee, ismag) \\\n-float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \\\n- float_status *s) \\\n-{ \\\n- FloatParts64 pa, pb, pr; \\\n- float ## sz ## _unpack_canonical(&pa, a, s); \\\n- float ## sz ## _unpack_canonical(&pb, b, s); \\\n- pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \\\n- return float ## sz ## _round_pack_canonical(&pr, s); \\\n+static bfloat16 bfloat16_minmax(bfloat16 a, bfloat16 b,\n+ float_status *s, int flags)\n+{\n+ FloatParts64 pa, pb;\n+ int which;\n+\n+ bfloat16_unpack_canonical(&pa, a, s);\n+ bfloat16_unpack_canonical(&pb, b, s);\n+ which = parts_minmax(&pa, &pb, s, flags, &float16_params);\n+ if (unlikely(which < 0)) {\n+ /* Some sort of nan, need to repack default and silenced nans. */\n+ return bfloat16_round_pack_canonical(&pa, s);\n+ }\n+ return which ? b : a;\n }\n \n-MINMAX(16, min, true, false, false)\n-MINMAX(16, minnum, true, true, false)\n-MINMAX(16, minnummag, true, true, true)\n-MINMAX(16, max, false, false, false)\n-MINMAX(16, maxnum, false, true, false)\n-MINMAX(16, maxnummag, false, true, true)\n+static float32 float32_minmax(float32 a, float32 b, float_status *s, int flags)\n+{\n+ FloatParts64 pa, pb;\n+ int which;\n \n-MINMAX(32, min, true, false, false)\n-MINMAX(32, minnum, true, true, false)\n-MINMAX(32, minnummag, true, true, true)\n-MINMAX(32, max, false, false, false)\n-MINMAX(32, maxnum, false, true, false)\n-MINMAX(32, maxnummag, false, true, true)\n-\n-MINMAX(64, min, true, false, false)\n-MINMAX(64, minnum, true, true, false)\n-MINMAX(64, minnummag, true, true, true)\n-MINMAX(64, max, false, false, false)\n-MINMAX(64, maxnum, false, true, false)\n-MINMAX(64, maxnummag, false, true, true)\n-\n-#undef MINMAX\n-\n-#define BF16_MINMAX(name, ismin, isiee, ismag) \\\n-bfloat16 bfloat16_ ## name(bfloat16 a, bfloat16 b, float_status *s) \\\n-{ \\\n- FloatParts64 pa, pb, pr; \\\n- bfloat16_unpack_canonical(&pa, a, s); \\\n- bfloat16_unpack_canonical(&pb, b, s); \\\n- pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \\\n- return bfloat16_round_pack_canonical(&pr, s); \\\n+ float32_unpack_canonical(&pa, a, s);\n+ float32_unpack_canonical(&pb, b, s);\n+ which = parts_minmax(&pa, &pb, s, flags, &float32_params);\n+ if (unlikely(which < 0)) {\n+ /* Some sort of nan, need to repack default and silenced nans. */\n+ return float32_round_pack_canonical(&pa, s);\n+ }\n+ return which ? b : a;\n }\n \n-BF16_MINMAX(min, true, false, false)\n-BF16_MINMAX(minnum, true, true, false)\n-BF16_MINMAX(minnummag, true, true, true)\n-BF16_MINMAX(max, false, false, false)\n-BF16_MINMAX(maxnum, false, true, false)\n-BF16_MINMAX(maxnummag, false, true, true)\n+static float64 float64_minmax(float64 a, float64 b, float_status *s, int flags)\n+{\n+ FloatParts64 pa, pb;\n+ int which;\n \n-#undef BF16_MINMAX\n+ float64_unpack_canonical(&pa, a, s);\n+ float64_unpack_canonical(&pb, b, s);\n+ which = parts_minmax(&pa, &pb, s, flags, &float64_params);\n+ if (unlikely(which < 0)) {\n+ /* Some sort of nan, need to repack default and silenced nans. */\n+ return float64_round_pack_canonical(&pa, s);\n+ }\n+ return which ? b : a;\n+}\n+\n+#define MINMAX_1(type, name, flags) \\\n+ type type##_##name(type a, type b, float_status *s) \\\n+ { return type##_minmax(a, b, s, flags); }\n+\n+#define MINMAX_2(type) \\\n+ MINMAX_1(type, max, 0) \\\n+ MINMAX_1(type, maxnum, minmax_isnum) \\\n+ MINMAX_1(type, maxnummag, minmax_ismag) \\\n+ MINMAX_1(type, min, minmax_ismin) \\\n+ MINMAX_1(type, minnum, minmax_ismin | minmax_isnum) \\\n+ MINMAX_1(type, minnummag, minmax_ismin | minmax_ismag)\n+\n+MINMAX_2(float16)\n+MINMAX_2(bfloat16)\n+MINMAX_2(float32)\n+MINMAX_2(float64)\n+\n+#undef MINMAX_1\n+#undef MINMAX_2\n \n /* Floating point compare */\n static FloatRelation compare_floats(FloatParts64 a, FloatParts64 b, bool is_quiet,\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex f3c4f8c8d2..4d91ef0d32 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -936,3 +936,72 @@ static void partsN(uint_to_float)(FloatPartsN *p, uint64_t a,\n p->frac_hi = a << shift;\n }\n }\n+\n+/*\n+ * Float min/max.\n+ *\n+ * Return -1 to return the chosen nan in *a;\n+ * return 0 to use the a input unchanged; 1 to use the b input unchanged.\n+ */\n+static int partsN(minmax)(FloatPartsN *a, FloatPartsN *b,\n+ float_status *s, int flags, const FloatFmt *fmt)\n+{\n+ int ab_mask = float_cmask(a->cls) | float_cmask(b->cls);\n+ int a_exp, b_exp;\n+ bool a_less;\n+\n+ if (unlikely(ab_mask & float_cmask_anynan)) {\n+ /*\n+ * For minnum/maxnum, if one operand is a QNaN, and the other\n+ * operand is numerical, then return numerical argument.\n+ */\n+ if ((flags & minmax_isnum)\n+ && !(ab_mask & float_cmask_snan)\n+ && (ab_mask & ~float_cmask_qnan)) {\n+ return is_nan(a->cls);\n+ }\n+ *a = *parts_pick_nan(a, b, s);\n+ return -1;\n+ }\n+\n+ a_exp = a->exp;\n+ b_exp = b->exp;\n+\n+ if (unlikely(ab_mask != float_cmask_normal)) {\n+ switch (a->cls) {\n+ case float_class_normal:\n+ break;\n+ case float_class_inf:\n+ a_exp = INT_MAX;\n+ break;\n+ case float_class_zero:\n+ a_exp = INT_MIN;\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ break;\n+ }\n+ switch (b->cls) {\n+ case float_class_normal:\n+ break;\n+ case float_class_inf:\n+ b_exp = INT_MAX;\n+ break;\n+ case float_class_zero:\n+ b_exp = INT_MIN;\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ break;\n+ }\n+ }\n+\n+ if (a->sign != b->sign && !(flags & minmax_ismag)) {\n+ a_less = a->sign;\n+ } else if (a_exp != b_exp) {\n+ a_less = a_exp < b_exp;\n+ } else {\n+ a_less = frac_cmp(a, b) < 0;\n+ }\n+ return a_less ^ !!(flags & minmax_ismin);\n+}\n", "prefixes": [ "50/72" ] }