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GET /api/patches/1475750/?format=api
{ "id": 1475750, "url": "http://patchwork.ozlabs.org/api/patches/1475750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-43-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-43-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:47:32", "name": "[42/72] softfloat: Move div_floats to softfloat-parts.c.inc", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f93e574f7a3f8f8821b8062b65e8537bcffe157a", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-43-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475750/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475750/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x102a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Rename to parts$N_div.\nImplement float128_div with FloatParts128.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat.c | 290 +++++++++++++++-----------------------\n fpu/softfloat-parts.c.inc | 55 ++++++++\n 2 files changed, 171 insertions(+), 174 deletions(-)", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex a42c297828..8efa52f7ec 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -802,6 +802,14 @@ static FloatParts128 *parts128_muladd(FloatParts128 *a, FloatParts128 *b,\n #define parts_muladd(A, B, C, Z, S) \\\n PARTS_GENERIC_64_128(muladd, A)(A, B, C, Z, S)\n \n+static FloatParts64 *parts64_div(FloatParts64 *a, FloatParts64 *b,\n+ float_status *s);\n+static FloatParts128 *parts128_div(FloatParts128 *a, FloatParts128 *b,\n+ float_status *s);\n+\n+#define parts_div(A, B, S) \\\n+ PARTS_GENERIC_64_128(div, A)(A, B, S)\n+\n /*\n * Helper functions for softfloat-parts.c.inc, per-size operations.\n */\n@@ -894,6 +902,87 @@ static void frac128_clear(FloatParts128 *a)\n \n #define frac_clear(A) FRAC_GENERIC_64_128(clear, A)(A)\n \n+static bool frac64_div(FloatParts64 *a, FloatParts64 *b)\n+{\n+ uint64_t n1, n0, r, q;\n+ bool ret;\n+\n+ /*\n+ * We want a 2*N / N-bit division to produce exactly an N-bit\n+ * result, so that we do not lose any precision and so that we\n+ * do not have to renormalize afterward. If A.frac < B.frac,\n+ * then division would produce an (N-1)-bit result; shift A left\n+ * by one to produce the an N-bit result, and return true to\n+ * decrement the exponent to match.\n+ *\n+ * The udiv_qrnnd algorithm that we're using requires normalization,\n+ * i.e. the msb of the denominator must be set, which is already true.\n+ */\n+ ret = a->frac < b->frac;\n+ if (ret) {\n+ n0 = a->frac;\n+ n1 = 0;\n+ } else {\n+ n0 = a->frac >> 1;\n+ n1 = a->frac << 63;\n+ }\n+ q = udiv_qrnnd(&r, n0, n1, b->frac);\n+\n+ /* Set lsb if there is a remainder, to set inexact. */\n+ a->frac = q | (r != 0);\n+\n+ return ret;\n+}\n+\n+static bool frac128_div(FloatParts128 *a, FloatParts128 *b)\n+{\n+ uint64_t q0, q1, a0, a1, b0, b1;\n+ uint64_t r0, r1, r2, r3, t0, t1, t2, t3;\n+ bool ret = false;\n+\n+ a0 = a->frac_hi, a1 = a->frac_lo;\n+ b0 = b->frac_hi, b1 = b->frac_lo;\n+\n+ ret = lt128(a0, a1, b0, b1);\n+ if (!ret) {\n+ a1 = shr_double(a0, a1, 1);\n+ a0 = a0 >> 1;\n+ }\n+\n+ /* Use 128/64 -> 64 division as estimate for 192/128 -> 128 division. */\n+ q0 = estimateDiv128To64(a0, a1, b0);\n+\n+ /*\n+ * Estimate is high because B1 was not included (unless B1 == 0).\n+ * Reduce quotient and increase remainder until remainder is non-negative.\n+ * This loop will execute 0 to 2 times.\n+ */\n+ mul128By64To192(b0, b1, q0, &t0, &t1, &t2);\n+ sub192(a0, a1, 0, t0, t1, t2, &r0, &r1, &r2);\n+ while (r0 != 0) {\n+ q0--;\n+ add192(r0, r1, r2, 0, b0, b1, &r0, &r1, &r2);\n+ }\n+\n+ /* Repeat using the remainder, producing a second word of quotient. */\n+ q1 = estimateDiv128To64(r1, r2, b0);\n+ mul128By64To192(b0, b1, q1, &t1, &t2, &t3);\n+ sub192(r1, r2, 0, t1, t2, t3, &r1, &r2, &r3);\n+ while (r1 != 0) {\n+ q1--;\n+ add192(r1, r2, r3, 0, b0, b1, &r1, &r2, &r3);\n+ }\n+\n+ /* Any remainder indicates inexact; set sticky bit. */\n+ q1 |= (r2 | r3) != 0;\n+\n+ a->frac_hi = q0;\n+ a->frac_lo = q1;\n+ return ret;\n+}\n+\n+#define frac_div(A, B) FRAC_GENERIC_64_128(div, A)(A, B)\n+\n static bool frac64_eqz(FloatParts64 *a)\n {\n return a->frac == 0;\n@@ -1820,110 +1909,42 @@ float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c,\n }\n \n /*\n- * Returns the result of dividing the floating-point value `a' by the\n- * corresponding value `b'. The operation is performed according to\n- * the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\n+ * Division\n */\n \n-static FloatParts64 div_floats(FloatParts64 a, FloatParts64 b, float_status *s)\n-{\n- bool sign = a.sign ^ b.sign;\n-\n- if (a.cls == float_class_normal && b.cls == float_class_normal) {\n- uint64_t n0, n1, q, r;\n- int exp = a.exp - b.exp;\n-\n- /*\n- * We want a 2*N / N-bit division to produce exactly an N-bit\n- * result, so that we do not lose any precision and so that we\n- * do not have to renormalize afterward. If A.frac < B.frac,\n- * then division would produce an (N-1)-bit result; shift A left\n- * by one to produce the an N-bit result, and decrement the\n- * exponent to match.\n- *\n- * The udiv_qrnnd algorithm that we're using requires normalization,\n- * i.e. the msb of the denominator must be set, which is already true.\n- */\n- if (a.frac < b.frac) {\n- exp -= 1;\n- shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT + 1, &n1, &n0);\n- } else {\n- shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT, &n1, &n0);\n- }\n- q = udiv_qrnnd(&r, n1, n0, b.frac);\n-\n- /* Set lsb if there is a remainder, to set inexact. */\n- a.frac = q | (r != 0);\n- a.sign = sign;\n- a.exp = exp;\n- return a;\n- }\n- /* handle all the NaN cases */\n- if (is_nan(a.cls) || is_nan(b.cls)) {\n- return *parts_pick_nan(&a, &b, s);\n- }\n- /* 0/0 or Inf/Inf */\n- if (a.cls == b.cls\n- &&\n- (a.cls == float_class_inf || a.cls == float_class_zero)) {\n- float_raise(float_flag_invalid, s);\n- parts_default_nan(&a, s);\n- return a;\n- }\n- /* Inf / x or 0 / x */\n- if (a.cls == float_class_inf || a.cls == float_class_zero) {\n- a.sign = sign;\n- return a;\n- }\n- /* Div 0 => Inf */\n- if (b.cls == float_class_zero) {\n- float_raise(float_flag_divbyzero, s);\n- a.cls = float_class_inf;\n- a.sign = sign;\n- return a;\n- }\n- /* Div by Inf */\n- if (b.cls == float_class_inf) {\n- a.cls = float_class_zero;\n- a.sign = sign;\n- return a;\n- }\n- g_assert_not_reached();\n-}\n-\n float16 float16_div(float16 a, float16 b, float_status *status)\n {\n- FloatParts64 pa, pb, pr;\n+ FloatParts64 pa, pb, *pr;\n \n float16_unpack_canonical(&pa, a, status);\n float16_unpack_canonical(&pb, b, status);\n- pr = div_floats(pa, pb, status);\n+ pr = parts_div(&pa, &pb, status);\n \n- return float16_round_pack_canonical(&pr, status);\n+ return float16_round_pack_canonical(pr, status);\n }\n \n static float32 QEMU_SOFTFLOAT_ATTR\n soft_f32_div(float32 a, float32 b, float_status *status)\n {\n- FloatParts64 pa, pb, pr;\n+ FloatParts64 pa, pb, *pr;\n \n float32_unpack_canonical(&pa, a, status);\n float32_unpack_canonical(&pb, b, status);\n- pr = div_floats(pa, pb, status);\n+ pr = parts_div(&pa, &pb, status);\n \n- return float32_round_pack_canonical(&pr, status);\n+ return float32_round_pack_canonical(pr, status);\n }\n \n static float64 QEMU_SOFTFLOAT_ATTR\n soft_f64_div(float64 a, float64 b, float_status *status)\n {\n- FloatParts64 pa, pb, pr;\n+ FloatParts64 pa, pb, *pr;\n \n float64_unpack_canonical(&pa, a, status);\n float64_unpack_canonical(&pb, b, status);\n- pr = div_floats(pa, pb, status);\n+ pr = parts_div(&pa, &pb, status);\n \n- return float64_round_pack_canonical(&pr, status);\n+ return float64_round_pack_canonical(pr, status);\n }\n \n static float hard_f32_div(float a, float b)\n@@ -1984,20 +2005,28 @@ float64_div(float64 a, float64 b, float_status *s)\n f64_div_pre, f64_div_post);\n }\n \n-/*\n- * Returns the result of dividing the bfloat16\n- * value `a' by the corresponding value `b'.\n- */\n-\n-bfloat16 bfloat16_div(bfloat16 a, bfloat16 b, float_status *status)\n+bfloat16 QEMU_FLATTEN\n+bfloat16_div(bfloat16 a, bfloat16 b, float_status *status)\n {\n- FloatParts64 pa, pb, pr;\n+ FloatParts64 pa, pb, *pr;\n \n bfloat16_unpack_canonical(&pa, a, status);\n bfloat16_unpack_canonical(&pb, b, status);\n- pr = div_floats(pa, pb, status);\n+ pr = parts_div(&pa, &pb, status);\n \n- return bfloat16_round_pack_canonical(&pr, status);\n+ return bfloat16_round_pack_canonical(pr, status);\n+}\n+\n+float128 QEMU_FLATTEN\n+float128_div(float128 a, float128 b, float_status *status)\n+{\n+ FloatParts128 pa, pb, *pr;\n+\n+ float128_unpack_canonical(&pa, a, status);\n+ float128_unpack_canonical(&pb, b, status);\n+ pr = parts_div(&pa, &pb, status);\n+\n+ return float128_round_pack_canonical(pr, status);\n }\n \n /*\n@@ -7122,93 +7151,6 @@ float128 float128_round_to_int(float128 a, float_status *status)\n \n }\n \n-/*----------------------------------------------------------------------------\n-| Returns the result of dividing the quadruple-precision floating-point value\n-| `a' by the corresponding value `b'. The operation is performed according to\n-| the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\n-*----------------------------------------------------------------------------*/\n-\n-float128 float128_div(float128 a, float128 b, float_status *status)\n-{\n- bool aSign, bSign, zSign;\n- int32_t aExp, bExp, zExp;\n- uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;\n- uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3;\n-\n- aSig1 = extractFloat128Frac1( a );\n- aSig0 = extractFloat128Frac0( a );\n- aExp = extractFloat128Exp( a );\n- aSign = extractFloat128Sign( a );\n- bSig1 = extractFloat128Frac1( b );\n- bSig0 = extractFloat128Frac0( b );\n- bExp = extractFloat128Exp( b );\n- bSign = extractFloat128Sign( b );\n- zSign = aSign ^ bSign;\n- if ( aExp == 0x7FFF ) {\n- if (aSig0 | aSig1) {\n- return propagateFloat128NaN(a, b, status);\n- }\n- if ( bExp == 0x7FFF ) {\n- if (bSig0 | bSig1) {\n- return propagateFloat128NaN(a, b, status);\n- }\n- goto invalid;\n- }\n- return packFloat128( zSign, 0x7FFF, 0, 0 );\n- }\n- if ( bExp == 0x7FFF ) {\n- if (bSig0 | bSig1) {\n- return propagateFloat128NaN(a, b, status);\n- }\n- return packFloat128( zSign, 0, 0, 0 );\n- }\n- if ( bExp == 0 ) {\n- if ( ( bSig0 | bSig1 ) == 0 ) {\n- if ( ( aExp | aSig0 | aSig1 ) == 0 ) {\n- invalid:\n- float_raise(float_flag_invalid, status);\n- return float128_default_nan(status);\n- }\n- float_raise(float_flag_divbyzero, status);\n- return packFloat128( zSign, 0x7FFF, 0, 0 );\n- }\n- normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );\n- }\n- if ( aExp == 0 ) {\n- if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );\n- normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\n- }\n- zExp = aExp - bExp + 0x3FFD;\n- shortShift128Left(\n- aSig0 | UINT64_C(0x0001000000000000), aSig1, 15, &aSig0, &aSig1 );\n- shortShift128Left(\n- bSig0 | UINT64_C(0x0001000000000000), bSig1, 15, &bSig0, &bSig1 );\n- if ( le128( bSig0, bSig1, aSig0, aSig1 ) ) {\n- shift128Right( aSig0, aSig1, 1, &aSig0, &aSig1 );\n- ++zExp;\n- }\n- zSig0 = estimateDiv128To64( aSig0, aSig1, bSig0 );\n- mul128By64To192( bSig0, bSig1, zSig0, &term0, &term1, &term2 );\n- sub192( aSig0, aSig1, 0, term0, term1, term2, &rem0, &rem1, &rem2 );\n- while ( (int64_t) rem0 < 0 ) {\n- --zSig0;\n- add192( rem0, rem1, rem2, 0, bSig0, bSig1, &rem0, &rem1, &rem2 );\n- }\n- zSig1 = estimateDiv128To64( rem1, rem2, bSig0 );\n- if ( ( zSig1 & 0x3FFF ) <= 4 ) {\n- mul128By64To192( bSig0, bSig1, zSig1, &term1, &term2, &term3 );\n- sub192( rem1, rem2, 0, term1, term2, term3, &rem1, &rem2, &rem3 );\n- while ( (int64_t) rem1 < 0 ) {\n- --zSig1;\n- add192( rem1, rem2, rem3, 0, bSig0, bSig1, &rem1, &rem2, &rem3 );\n- }\n- zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );\n- }\n- shift128ExtraRightJamming( zSig0, zSig1, 0, 15, &zSig0, &zSig1, &zSig2 );\n- return roundAndPackFloat128(zSign, zExp, zSig0, zSig1, zSig2, status);\n-\n-}\n-\n /*----------------------------------------------------------------------------\n | Returns the remainder of the quadruple-precision floating-point value `a'\n | with respect to the corresponding value `b'. The operation is performed\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex a203811299..f8165d92f9 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -539,3 +539,58 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,\n parts_default_nan(a, s);\n return a;\n }\n+\n+/*\n+ * Returns the result of dividing the floating-point value `a' by the\n+ * corresponding value `b'. The operation is performed according to\n+ * the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\n+ */\n+static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b,\n+ float_status *s)\n+{\n+ int ab_mask = float_cmask(a->cls) | float_cmask(b->cls);\n+ bool sign = a->sign ^ b->sign;\n+\n+ if (likely(ab_mask == float_cmask_normal)) {\n+ a->sign = sign;\n+ a->exp -= b->exp + frac_div(a, b);\n+ return a;\n+ }\n+\n+ /* 0/0 or Inf/Inf => NaN */\n+ if (unlikely(ab_mask == float_cmask_zero) ||\n+ unlikely(ab_mask == float_cmask_inf)) {\n+ float_raise(float_flag_invalid, s);\n+ parts_default_nan(a, s);\n+ return a;\n+ }\n+\n+ /* All the NaN cases */\n+ if (unlikely(ab_mask & float_cmask_anynan)) {\n+ return parts_pick_nan(a, b, s);\n+ }\n+\n+ a->sign = sign;\n+\n+ /* Inf / X */\n+ if (a->cls == float_class_inf) {\n+ return a;\n+ }\n+\n+ /* 0 / X */\n+ if (a->cls == float_class_zero) {\n+ return a;\n+ }\n+\n+ /* X / Inf */\n+ if (b->cls == float_class_inf) {\n+ a->cls = float_class_zero;\n+ return a;\n+ }\n+\n+ /* X / 0 => Inf */\n+ g_assert(b->cls == float_class_zero);\n+ float_raise(float_flag_divbyzero, s);\n+ a->cls = float_class_inf;\n+ return a;\n+}\n", "prefixes": [ "42/72" ] }