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GET /api/patches/1475746/?format=api
{ "id": 1475746, "url": "http://patchwork.ozlabs.org/api/patches/1475746/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-42-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-42-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:47:31", "name": "[41/72] softfloat: Introduce sh[lr]_double primitives", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6d0958aa6657d84472ee132d675c73e1b0c01bf5", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-42-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475746/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475746/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Jk9Rb53g;\n\tdkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4FcWLd4zFXz9sWp\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 8 May 2021 12:22:49 +1000 (AEST)", "from localhost ([::1]:47872 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1lfCcB-0005Tb-ML\n\tfor incoming@patchwork.ozlabs.org; Fri, 07 May 2021 22:22:47 -0400", "from eggs.gnu.org ([2001:470:142:3::10]:41410)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1lfC7y-0002ct-6P\n for qemu-devel@nongnu.org; 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helo=mail-pl1-x630.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Have x86_64 assembly for them, with a fallback.\nThis avoids shuffling values through %cl in the x86 case.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n include/fpu/softfloat-macros.h | 36 ++++++++++++\n fpu/softfloat.c | 102 +++++++++++++++++++++++++--------\n 2 files changed, 115 insertions(+), 23 deletions(-)", "diff": "diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h\nindex 672c1db555..ec4e27a595 100644\n--- a/include/fpu/softfloat-macros.h\n+++ b/include/fpu/softfloat-macros.h\n@@ -85,6 +85,42 @@ this code that are retained.\n #include \"fpu/softfloat-types.h\"\n #include \"qemu/host-utils.h\"\n \n+/**\n+ * shl_double: double-word merging left shift\n+ * @l: left or most-significant word\n+ * @r: right or least-significant word\n+ * @c: shift count\n+ *\n+ * Shift @l left by @c bits, shifting in bits from @r.\n+ */\n+static inline uint64_t shl_double(uint64_t l, uint64_t r, int c)\n+{\n+#if defined(__x86_64__)\n+ asm(\"shld %b2, %1, %0\" : \"+r\"(l) : \"r\"(r), \"ci\"(c));\n+ return l;\n+#else\n+ return c ? (l << c) | (r >> (64 - c)) : l;\n+#endif\n+}\n+\n+/**\n+ * shr_double: double-word merging right shift\n+ * @l: left or most-significant word\n+ * @r: right or least-significant word\n+ * @c: shift count\n+ *\n+ * Shift @r right by @c bits, shifting in bits from @l.\n+ */\n+static inline uint64_t shr_double(uint64_t l, uint64_t r, int c)\n+{\n+#if defined(__x86_64__)\n+ asm(\"shrd %b2, %1, %0\" : \"+r\"(r) : \"r\"(l), \"ci\"(c));\n+ return r;\n+#else\n+ return c ? (r >> c) | (l << (64 - c)) : r;\n+#endif\n+}\n+\n /*----------------------------------------------------------------------------\n | Shifts `a' right by the number of bits given in `count'. If any nonzero\n | bits are shifted off, they are ``jammed'' into the least significant bit of\ndiff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex a9ee8498ae..a42c297828 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -956,15 +956,12 @@ static int frac128_normalize(FloatParts128 *a)\n {\n if (a->frac_hi) {\n int shl = clz64(a->frac_hi);\n- if (shl) {\n- int shr = 64 - shl;\n- a->frac_hi = (a->frac_hi << shl) | (a->frac_lo >> shr);\n- a->frac_lo = (a->frac_lo << shl);\n- }\n+ a->frac_hi = shl_double(a->frac_hi, a->frac_lo, shl);\n+ a->frac_lo <<= shl;\n return shl;\n } else if (a->frac_lo) {\n int shl = clz64(a->frac_lo);\n- a->frac_hi = (a->frac_lo << shl);\n+ a->frac_hi = a->frac_lo << shl;\n a->frac_lo = 0;\n return shl + 64;\n }\n@@ -975,7 +972,7 @@ static int frac256_normalize(FloatParts256 *a)\n {\n uint64_t a0 = a->frac_hi, a1 = a->frac_hm;\n uint64_t a2 = a->frac_lm, a3 = a->frac_lo;\n- int ret, shl, shr;\n+ int ret, shl;\n \n if (likely(a0)) {\n shl = clz64(a0);\n@@ -1005,11 +1002,10 @@ static int frac256_normalize(FloatParts256 *a)\n ret += shl;\n }\n \n- shr = -shl & 63;\n- a0 = (a0 << shl) | (a1 >> shr);\n- a1 = (a1 << shl) | (a2 >> shr);\n- a2 = (a2 << shl) | (a3 >> shr);\n- a3 = (a3 << shl);\n+ a0 = shl_double(a0, a1, shl);\n+ a1 = shl_double(a1, a2, shl);\n+ a2 = shl_double(a2, a3, shl);\n+ a3 <<= shl;\n \n done:\n a->frac_hi = a0;\n@@ -1028,7 +1024,20 @@ static void frac64_shl(FloatParts64 *a, int c)\n \n static void frac128_shl(FloatParts128 *a, int c)\n {\n- shift128Left(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo);\n+ uint64_t a0 = a->frac_hi, a1 = a->frac_lo;\n+\n+ if (c & 64) {\n+ a0 = a1, a1 = 0;\n+ }\n+\n+ c &= 63;\n+ if (c) {\n+ a0 = shl_double(a0, a1, c);\n+ a1 = a1 << c;\n+ }\n+\n+ a->frac_hi = a0;\n+ a->frac_lo = a1;\n }\n \n #define frac_shl(A, C) FRAC_GENERIC_64_128(shl, A)(A, C)\n@@ -1040,19 +1049,68 @@ static void frac64_shr(FloatParts64 *a, int c)\n \n static void frac128_shr(FloatParts128 *a, int c)\n {\n- shift128Right(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo);\n+ uint64_t a0 = a->frac_hi, a1 = a->frac_lo;\n+\n+ if (c & 64) {\n+ a1 = a0, a0 = 0;\n+ }\n+\n+ c &= 63;\n+ if (c) {\n+ a1 = shr_double(a0, a1, c);\n+ a0 = a0 >> c;\n+ }\n+\n+ a->frac_hi = a0;\n+ a->frac_lo = a1;\n }\n \n #define frac_shr(A, C) FRAC_GENERIC_64_128(shr, A)(A, C)\n \n static void frac64_shrjam(FloatParts64 *a, int c)\n {\n- shift64RightJamming(a->frac, c, &a->frac);\n+ uint64_t a0 = a->frac;\n+\n+ if (likely(c != 0)) {\n+ if (likely(c < 64)) {\n+ a0 = (a0 >> c) | (shr_double(a0, 0, c) != 0);\n+ } else {\n+ a0 = a0 != 0;\n+ }\n+ a->frac = a0;\n+ }\n }\n \n static void frac128_shrjam(FloatParts128 *a, int c)\n {\n- shift128RightJamming(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo);\n+ uint64_t a0 = a->frac_hi, a1 = a->frac_lo;\n+ uint64_t sticky = 0;\n+\n+ if (unlikely(c == 0)) {\n+ return;\n+ } else if (likely(c < 64)) {\n+ /* nothing */\n+ } else if (likely(c < 128)) {\n+ sticky = a1;\n+ a1 = a0;\n+ a0 = 0;\n+ c &= 63;\n+ if (c == 0) {\n+ goto done;\n+ }\n+ } else {\n+ sticky = a0 | a1;\n+ a0 = a1 = 0;\n+ goto done;\n+ }\n+\n+ sticky |= shr_double(a1, 0, c);\n+ a1 = shr_double(a0, a1, c);\n+ a0 = a0 >> c;\n+\n+ done:\n+ a->frac_lo = a1 | (sticky != 0);\n+ a->frac_hi = a0;\n }\n \n static void frac256_shrjam(FloatParts256 *a, int c)\n@@ -1060,7 +1118,6 @@ static void frac256_shrjam(FloatParts256 *a, int c)\n uint64_t a0 = a->frac_hi, a1 = a->frac_hm;\n uint64_t a2 = a->frac_lm, a3 = a->frac_lo;\n uint64_t sticky = 0;\n- int invc;\n \n if (unlikely(c == 0)) {\n return;\n@@ -1085,12 +1142,11 @@ static void frac256_shrjam(FloatParts256 *a, int c)\n goto done;\n }\n \n- invc = -c & 63;\n- sticky |= a3 << invc;\n- a3 = (a3 >> c) | (a2 << invc);\n- a2 = (a2 >> c) | (a1 << invc);\n- a1 = (a1 >> c) | (a0 << invc);\n- a0 = (a0 >> c);\n+ sticky |= shr_double(a3, 0, c);\n+ a3 = shr_double(a2, a3, c);\n+ a2 = shr_double(a1, a2, c);\n+ a1 = shr_double(a0, a1, c);\n+ a0 = a0 >> c;\n \n done:\n a->frac_lo = a3 | (sticky != 0);\n", "prefixes": [ "41/72" ] }