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GET /api/patches/1475745/?format=api
{ "id": 1475745, "url": "http://patchwork.ozlabs.org/api/patches/1475745/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-35-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-35-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:47:24", "name": "[34/72] softfloat: Move addsub_floats to softfloat-parts.c.inc", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fbc0f3edee3558a5036f26b8fda223747de09dfe", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-35-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475745/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475745/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pg1-x530.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "In preparation for implementing multiple sizes. Rename to parts_addsub,\nsplit out parts_add/sub_normal for future reuse with muladd.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat.c | 253 ++++++++++++++-----------------\n fpu/softfloat-parts-addsub.c.inc | 62 ++++++++\n fpu/softfloat-parts.c.inc | 81 ++++++++++\n 3 files changed, 255 insertions(+), 141 deletions(-)\n create mode 100644 fpu/softfloat-parts-addsub.c.inc", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex e9d644385d..22dc6da5ef 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -748,6 +748,26 @@ static void parts128_uncanon(FloatParts128 *p, float_status *status,\n #define parts_uncanon(A, S, F) \\\n PARTS_GENERIC_64_128(uncanon, A)(A, S, F)\n \n+static void parts64_add_normal(FloatParts64 *a, FloatParts64 *b);\n+static void parts128_add_normal(FloatParts128 *a, FloatParts128 *b);\n+\n+#define parts_add_normal(A, B) \\\n+ PARTS_GENERIC_64_128(add_normal, A)(A, B)\n+\n+static bool parts64_sub_normal(FloatParts64 *a, FloatParts64 *b);\n+static bool parts128_sub_normal(FloatParts128 *a, FloatParts128 *b);\n+\n+#define parts_sub_normal(A, B) \\\n+ PARTS_GENERIC_64_128(sub_normal, A)(A, B)\n+\n+static FloatParts64 *parts64_addsub(FloatParts64 *a, FloatParts64 *b,\n+ float_status *s, bool subtract);\n+static FloatParts128 *parts128_addsub(FloatParts128 *a, FloatParts128 *b,\n+ float_status *s, bool subtract);\n+\n+#define parts_addsub(A, B, S, Z) \\\n+ PARTS_GENERIC_64_128(addsub, A)(A, B, S, Z)\n+\n /*\n * Helper functions for softfloat-parts.c.inc, per-size operations.\n */\n@@ -755,6 +775,21 @@ static void parts128_uncanon(FloatParts128 *p, float_status *status,\n #define FRAC_GENERIC_64_128(NAME, P) \\\n QEMU_GENERIC(P, (FloatParts128 *, frac128_##NAME), frac64_##NAME)\n \n+static bool frac64_add(FloatParts64 *r, FloatParts64 *a, FloatParts64 *b)\n+{\n+ return uadd64_overflow(a->frac, b->frac, &r->frac);\n+}\n+\n+static bool frac128_add(FloatParts128 *r, FloatParts128 *a, FloatParts128 *b)\n+{\n+ bool c = 0;\n+ r->frac_lo = uadd64_carry(a->frac_lo, b->frac_lo, &c);\n+ r->frac_hi = uadd64_carry(a->frac_hi, b->frac_hi, &c);\n+ return c;\n+}\n+\n+#define frac_add(R, A, B) FRAC_GENERIC_64_128(add, R)(R, A, B)\n+\n static bool frac64_addi(FloatParts64 *r, FloatParts64 *a, uint64_t c)\n {\n return uadd64_overflow(a->frac, c, &r->frac);\n@@ -823,6 +858,20 @@ static bool frac128_eqz(FloatParts128 *a)\n \n #define frac_eqz(A) FRAC_GENERIC_64_128(eqz, A)(A)\n \n+static void frac64_neg(FloatParts64 *a)\n+{\n+ a->frac = -a->frac;\n+}\n+\n+static void frac128_neg(FloatParts128 *a)\n+{\n+ bool c = 0;\n+ a->frac_lo = usub64_borrow(0, a->frac_lo, &c);\n+ a->frac_hi = usub64_borrow(0, a->frac_hi, &c);\n+}\n+\n+#define frac_neg(A) FRAC_GENERIC_64_128(neg, A)(A)\n+\n static int frac64_normalize(FloatParts64 *a)\n {\n if (a->frac) {\n@@ -890,18 +939,36 @@ static void frac128_shrjam(FloatParts128 *a, int c)\n \n #define frac_shrjam(A, C) FRAC_GENERIC_64_128(shrjam, A)(A, C)\n \n-#define partsN(NAME) parts64_##NAME\n-#define FloatPartsN FloatParts64\n+static bool frac64_sub(FloatParts64 *r, FloatParts64 *a, FloatParts64 *b)\n+{\n+ return usub64_overflow(a->frac, b->frac, &r->frac);\n+}\n \n+static bool frac128_sub(FloatParts128 *r, FloatParts128 *a, FloatParts128 *b)\n+{\n+ bool c = 0;\n+ r->frac_lo = usub64_borrow(a->frac_lo, b->frac_lo, &c);\n+ r->frac_hi = usub64_borrow(a->frac_hi, b->frac_hi, &c);\n+ return c;\n+}\n+\n+#define frac_sub(R, A, B) FRAC_GENERIC_64_128(sub, R)(R, A, B)\n+\n+#define partsN(NAME) glue(glue(glue(parts,N),_),NAME)\n+#define FloatPartsN glue(FloatParts,N)\n+\n+#define N 64\n+\n+#include \"softfloat-parts-addsub.c.inc\"\n #include \"softfloat-parts.c.inc\"\n \n-#undef partsN\n-#undef FloatPartsN\n-#define partsN(NAME) parts128_##NAME\n-#define FloatPartsN FloatParts128\n+#undef N\n+#define N 128\n \n+#include \"softfloat-parts-addsub.c.inc\"\n #include \"softfloat-parts.c.inc\"\n \n+#undef N\n #undef partsN\n #undef FloatPartsN\n \n@@ -979,165 +1046,73 @@ static float64 float64_round_pack_canonical(FloatParts64 *p,\n }\n \n /*\n- * Returns the result of adding or subtracting the values of the\n- * floating-point values `a' and `b'. The operation is performed\n- * according to the IEC/IEEE Standard for Binary Floating-Point\n- * Arithmetic.\n+ * Addition and subtraction\n */\n \n-static FloatParts64 addsub_floats(FloatParts64 a, FloatParts64 b, bool subtract,\n- float_status *s)\n+static float16 QEMU_FLATTEN\n+float16_addsub(float16 a, float16 b, float_status *status, bool subtract)\n {\n- bool a_sign = a.sign;\n- bool b_sign = b.sign ^ subtract;\n-\n- if (a_sign != b_sign) {\n- /* Subtraction */\n-\n- if (a.cls == float_class_normal && b.cls == float_class_normal) {\n- if (a.exp > b.exp || (a.exp == b.exp && a.frac >= b.frac)) {\n- shift64RightJamming(b.frac, a.exp - b.exp, &b.frac);\n- a.frac = a.frac - b.frac;\n- } else {\n- shift64RightJamming(a.frac, b.exp - a.exp, &a.frac);\n- a.frac = b.frac - a.frac;\n- a.exp = b.exp;\n- a_sign ^= 1;\n- }\n-\n- if (a.frac == 0) {\n- a.cls = float_class_zero;\n- a.sign = s->float_rounding_mode == float_round_down;\n- } else {\n- int shift = clz64(a.frac);\n- a.frac = a.frac << shift;\n- a.exp = a.exp - shift;\n- a.sign = a_sign;\n- }\n- return a;\n- }\n- if (is_nan(a.cls) || is_nan(b.cls)) {\n- return *parts_pick_nan(&a, &b, s);\n- }\n- if (a.cls == float_class_inf) {\n- if (b.cls == float_class_inf) {\n- float_raise(float_flag_invalid, s);\n- parts_default_nan(&a, s);\n- }\n- return a;\n- }\n- if (a.cls == float_class_zero && b.cls == float_class_zero) {\n- a.sign = s->float_rounding_mode == float_round_down;\n- return a;\n- }\n- if (a.cls == float_class_zero || b.cls == float_class_inf) {\n- b.sign = a_sign ^ 1;\n- return b;\n- }\n- if (b.cls == float_class_zero) {\n- return a;\n- }\n- } else {\n- /* Addition */\n- if (a.cls == float_class_normal && b.cls == float_class_normal) {\n- if (a.exp > b.exp) {\n- shift64RightJamming(b.frac, a.exp - b.exp, &b.frac);\n- } else if (a.exp < b.exp) {\n- shift64RightJamming(a.frac, b.exp - a.exp, &a.frac);\n- a.exp = b.exp;\n- }\n-\n- if (uadd64_overflow(a.frac, b.frac, &a.frac)) {\n- shift64RightJamming(a.frac, 1, &a.frac);\n- a.frac |= DECOMPOSED_IMPLICIT_BIT;\n- a.exp += 1;\n- }\n- return a;\n- }\n- if (is_nan(a.cls) || is_nan(b.cls)) {\n- return *parts_pick_nan(&a, &b, s);\n- }\n- if (a.cls == float_class_inf || b.cls == float_class_zero) {\n- return a;\n- }\n- if (b.cls == float_class_inf || a.cls == float_class_zero) {\n- b.sign = b_sign;\n- return b;\n- }\n- }\n- g_assert_not_reached();\n-}\n-\n-/*\n- * Returns the result of adding or subtracting the floating-point\n- * values `a' and `b'. The operation is performed according to the\n- * IEC/IEEE Standard for Binary Floating-Point Arithmetic.\n- */\n-\n-float16 QEMU_FLATTEN float16_add(float16 a, float16 b, float_status *status)\n-{\n- FloatParts64 pa, pb, pr;\n+ FloatParts64 pa, pb, *pr;\n \n float16_unpack_canonical(&pa, a, status);\n float16_unpack_canonical(&pb, b, status);\n- pr = addsub_floats(pa, pb, false, status);\n+ pr = parts_addsub(&pa, &pb, status, subtract);\n \n- return float16_round_pack_canonical(&pr, status);\n+ return float16_round_pack_canonical(pr, status);\n }\n \n-float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *status)\n+float16 float16_add(float16 a, float16 b, float_status *status)\n {\n- FloatParts64 pa, pb, pr;\n+ return float16_addsub(a, b, status, false);\n+}\n \n- float16_unpack_canonical(&pa, a, status);\n- float16_unpack_canonical(&pb, b, status);\n- pr = addsub_floats(pa, pb, true, status);\n-\n- return float16_round_pack_canonical(&pr, status);\n+float16 float16_sub(float16 a, float16 b, float_status *status)\n+{\n+ return float16_addsub(a, b, status, true);\n }\n \n static float32 QEMU_SOFTFLOAT_ATTR\n-soft_f32_addsub(float32 a, float32 b, bool subtract, float_status *status)\n+soft_f32_addsub(float32 a, float32 b, float_status *status, bool subtract)\n {\n- FloatParts64 pa, pb, pr;\n+ FloatParts64 pa, pb, *pr;\n \n float32_unpack_canonical(&pa, a, status);\n float32_unpack_canonical(&pb, b, status);\n- pr = addsub_floats(pa, pb, subtract, status);\n+ pr = parts_addsub(&pa, &pb, status, subtract);\n \n- return float32_round_pack_canonical(&pr, status);\n+ return float32_round_pack_canonical(pr, status);\n }\n \n-static inline float32 soft_f32_add(float32 a, float32 b, float_status *status)\n+static float32 soft_f32_add(float32 a, float32 b, float_status *status)\n {\n- return soft_f32_addsub(a, b, false, status);\n+ return soft_f32_addsub(a, b, status, false);\n }\n \n-static inline float32 soft_f32_sub(float32 a, float32 b, float_status *status)\n+static float32 soft_f32_sub(float32 a, float32 b, float_status *status)\n {\n- return soft_f32_addsub(a, b, true, status);\n+ return soft_f32_addsub(a, b, status, true);\n }\n \n static float64 QEMU_SOFTFLOAT_ATTR\n-soft_f64_addsub(float64 a, float64 b, bool subtract, float_status *status)\n+soft_f64_addsub(float64 a, float64 b, float_status *status, bool subtract)\n {\n- FloatParts64 pa, pb, pr;\n+ FloatParts64 pa, pb, *pr;\n \n float64_unpack_canonical(&pa, a, status);\n float64_unpack_canonical(&pb, b, status);\n- pr = addsub_floats(pa, pb, subtract, status);\n+ pr = parts_addsub(&pa, &pb, status, subtract);\n \n- return float64_round_pack_canonical(&pr, status);\n+ return float64_round_pack_canonical(pr, status);\n }\n \n-static inline float64 soft_f64_add(float64 a, float64 b, float_status *status)\n+static float64 soft_f64_add(float64 a, float64 b, float_status *status)\n {\n- return soft_f64_addsub(a, b, false, status);\n+ return soft_f64_addsub(a, b, status, false);\n }\n \n-static inline float64 soft_f64_sub(float64 a, float64 b, float_status *status)\n+static float64 soft_f64_sub(float64 a, float64 b, float_status *status)\n {\n- return soft_f64_addsub(a, b, true, status);\n+ return soft_f64_addsub(a, b, status, true);\n }\n \n static float hard_f32_add(float a, float b)\n@@ -1215,30 +1190,26 @@ float64_sub(float64 a, float64 b, float_status *s)\n return float64_addsub(a, b, s, hard_f64_sub, soft_f64_sub);\n }\n \n-/*\n- * Returns the result of adding or subtracting the bfloat16\n- * values `a' and `b'.\n- */\n-bfloat16 QEMU_FLATTEN bfloat16_add(bfloat16 a, bfloat16 b, float_status *status)\n+static bfloat16 QEMU_FLATTEN\n+bfloat16_addsub(bfloat16 a, bfloat16 b, float_status *status, bool subtract)\n {\n- FloatParts64 pa, pb, pr;\n+ FloatParts64 pa, pb, *pr;\n \n bfloat16_unpack_canonical(&pa, a, status);\n bfloat16_unpack_canonical(&pb, b, status);\n- pr = addsub_floats(pa, pb, false, status);\n+ pr = parts_addsub(&pa, &pb, status, subtract);\n \n- return bfloat16_round_pack_canonical(&pr, status);\n+ return bfloat16_round_pack_canonical(pr, status);\n }\n \n-bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat16 b, float_status *status)\n+bfloat16 bfloat16_add(bfloat16 a, bfloat16 b, float_status *status)\n {\n- FloatParts64 pa, pb, pr;\n+ return bfloat16_addsub(a, b, status, false);\n+}\n \n- bfloat16_unpack_canonical(&pa, a, status);\n- bfloat16_unpack_canonical(&pb, b, status);\n- pr = addsub_floats(pa, pb, true, status);\n-\n- return bfloat16_round_pack_canonical(&pr, status);\n+bfloat16 bfloat16_sub(bfloat16 a, bfloat16 b, float_status *status)\n+{\n+ return bfloat16_addsub(a, b, status, true);\n }\n \n /*\ndiff --git a/fpu/softfloat-parts-addsub.c.inc b/fpu/softfloat-parts-addsub.c.inc\nnew file mode 100644\nindex 0000000000..ae5c1017c5\n--- /dev/null\n+++ b/fpu/softfloat-parts-addsub.c.inc\n@@ -0,0 +1,62 @@\n+/*\n+ * Floating point arithmetic implementation\n+ *\n+ * The code in this source file is derived from release 2a of the SoftFloat\n+ * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and\n+ * some later contributions) are provided under that license, as detailed below.\n+ * It has subsequently been modified by contributors to the QEMU Project,\n+ * so some portions are provided under:\n+ * the SoftFloat-2a license\n+ * the BSD license\n+ * GPL-v2-or-later\n+ *\n+ * Any future contributions to this file after December 1st 2014 will be\n+ * taken to be licensed under the Softfloat-2a license unless specifically\n+ * indicated otherwise.\n+ */\n+\n+static void partsN(add_normal)(FloatPartsN *a, FloatPartsN *b)\n+{\n+ int exp_diff = a->exp - b->exp;\n+\n+ if (exp_diff > 0) {\n+ frac_shrjam(b, exp_diff);\n+ } else if (exp_diff < 0) {\n+ frac_shrjam(a, -exp_diff);\n+ a->exp = b->exp;\n+ }\n+\n+ if (frac_add(a, a, b)) {\n+ frac_shrjam(a, 1);\n+ a->frac_hi |= DECOMPOSED_IMPLICIT_BIT;\n+ a->exp += 1;\n+ }\n+}\n+\n+static bool partsN(sub_normal)(FloatPartsN *a, FloatPartsN *b)\n+{\n+ int exp_diff = a->exp - b->exp;\n+ int shift;\n+\n+ if (exp_diff > 0) {\n+ frac_shrjam(b, exp_diff);\n+ frac_sub(a, a, b);\n+ } else if (exp_diff < 0) {\n+ a->exp = b->exp;\n+ a->sign ^= 1;\n+ frac_shrjam(a, -exp_diff);\n+ frac_sub(a, b, a);\n+ } else if (frac_sub(a, a, b)) {\n+ /* Overflow means that A was less than B. */\n+ frac_neg(a);\n+ a->sign ^= 1;\n+ }\n+\n+ shift = frac_normalize(a);\n+ if (likely(shift < N)) {\n+ a->exp -= shift;\n+\treturn true;\n+ }\n+ a->cls = float_class_zero;\n+ return false;\n+}\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex efdc724770..cfce9f6421 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -281,3 +281,84 @@ static void partsN(uncanon)(FloatPartsN *p, float_status *s,\n p->exp = exp;\n float_raise(flags, s);\n }\n+\n+/*\n+ * Returns the result of adding or subtracting the values of the\n+ * floating-point values `a' and `b'. The operation is performed\n+ * according to the IEC/IEEE Standard for Binary Floating-Point\n+ * Arithmetic.\n+ */\n+static FloatPartsN *partsN(addsub)(FloatPartsN *a, FloatPartsN *b,\n+ float_status *s, bool subtract)\n+{\n+ bool b_sign = b->sign ^ subtract;\n+ int ab_mask = float_cmask(a->cls) | float_cmask(b->cls);\n+\n+ if (a->sign != b_sign) {\n+ /* Subtraction */\n+ if (likely(ab_mask == float_cmask_normal)) {\n+ if (parts_sub_normal(a, b)) {\n+ return a;\n+ }\n+ /* Subtract was exact, fall through to set sign. */\n+ ab_mask = float_cmask_zero;\n+ }\n+\n+ if (ab_mask == float_cmask_zero) {\n+ a->sign = s->float_rounding_mode == float_round_down;\n+ return a;\n+ }\n+\n+ if (unlikely(ab_mask & float_cmask_anynan)) {\n+ goto p_nan;\n+ }\n+\n+ if (ab_mask & float_cmask_inf) {\n+ if (a->cls != float_class_inf) {\n+ /* N - Inf */\n+ goto return_b;\n+ }\n+ if (b->cls != float_class_inf) {\n+ /* Inf - N */\n+ return a;\n+ }\n+ /* Inf - Inf */\n+ float_raise(float_flag_invalid, s);\n+ parts_default_nan(a, s);\n+ return a;\n+ }\n+ } else {\n+ /* Addition */\n+ if (likely(ab_mask == float_cmask_normal)) {\n+ parts_add_normal(a, b);\n+ return a;\n+ }\n+\n+ if (ab_mask == float_cmask_zero) {\n+ return a;\n+ }\n+\n+ if (unlikely(ab_mask & float_cmask_anynan)) {\n+ goto p_nan;\n+ }\n+\n+ if (ab_mask & float_cmask_inf) {\n+ a->cls = float_class_inf;\n+ return a;\n+ }\n+ }\n+\n+ if (b->cls == float_class_zero) {\n+ g_assert(a->cls == float_class_normal);\n+ return a;\n+ }\n+\n+ g_assert(a->cls == float_class_zero);\n+ g_assert(b->cls == float_class_normal);\n+ return_b:\n+ b->sign = b_sign;\n+ return b;\n+\n+ p_nan:\n+ return parts_pick_nan(a, b, s);\n+}\n", "prefixes": [ "34/72" ] }