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GET /api/patches/1475743/?format=api
{ "id": 1475743, "url": "http://patchwork.ozlabs.org/api/patches/1475743/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-47-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-47-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:47:36", "name": "[46/72] softfloat: Move rount_to_int_and_pack to softfloat-parts.c.inc", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c580e8819de13fca73e9cfa8f392d56eb6504ea3", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-47-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475743/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475743/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x102a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Rename to parts$N_float_to_sint. Reimplement\nfloat128_to_int{32,64}{_round_to_zero} with FloatParts128.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat.c | 365 +++++++++-----------------------------\n fpu/softfloat-parts.c.inc | 64 +++++++\n 2 files changed, 145 insertions(+), 284 deletions(-)", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex ce96ea753c..ac8e726935 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -828,6 +828,16 @@ static void parts128_round_to_int(FloatParts128 *a, FloatRoundMode r,\n #define parts_round_to_int(A, R, C, S, F) \\\n PARTS_GENERIC_64_128(round_to_int, A)(A, R, C, S, F)\n \n+static int64_t parts64_float_to_sint(FloatParts64 *p, FloatRoundMode rmode,\n+ int scale, int64_t min, int64_t max,\n+ float_status *s);\n+static int64_t parts128_float_to_sint(FloatParts128 *p, FloatRoundMode rmode,\n+ int scale, int64_t min, int64_t max,\n+ float_status *s);\n+\n+#define parts_float_to_sint(P, R, Z, MN, MX, S) \\\n+ PARTS_GENERIC_64_128(float_to_sint, P)(P, R, Z, MN, MX, S)\n+\n /*\n * Helper functions for softfloat-parts.c.inc, per-size operations.\n */\n@@ -2351,69 +2361,8 @@ float128 float128_round_to_int(float128 a, float_status *s)\n }\n \n /*\n- * Returns the result of converting the floating-point value `a' to\n- * the two's complement integer format. The conversion is performed\n- * according to the IEC/IEEE Standard for Binary Floating-Point\n- * Arithmetic---which means in particular that the conversion is\n- * rounded according to the current rounding mode. If `a' is a NaN,\n- * the largest positive integer is returned. Otherwise, if the\n- * conversion overflows, the largest integer with the same sign as `a'\n- * is returned.\n-*/\n-\n-static int64_t round_to_int_and_pack(FloatParts64 p, FloatRoundMode rmode,\n- int scale, int64_t min, int64_t max,\n- float_status *s)\n-{\n- int flags = 0;\n- uint64_t r;\n-\n- switch (p.cls) {\n- case float_class_snan:\n- case float_class_qnan:\n- flags = float_flag_invalid;\n- r = max;\n- break;\n-\n- case float_class_inf:\n- flags = float_flag_invalid;\n- r = p.sign ? min : max;\n- break;\n-\n- case float_class_zero:\n- return 0;\n-\n- case float_class_normal:\n- /* TODO: 62 = N - 2, frac_size for rounding */\n- if (parts_round_to_int_normal(&p, rmode, scale, 62)) {\n- flags = float_flag_inexact;\n- }\n-\n- if (p.exp <= DECOMPOSED_BINARY_POINT) {\n- r = p.frac >> (DECOMPOSED_BINARY_POINT - p.exp);\n- } else {\n- r = UINT64_MAX;\n- }\n- if (p.sign) {\n- if (r <= -(uint64_t)min) {\n- r = -r;\n- } else {\n- flags = float_flag_invalid;\n- r = min;\n- }\n- } else if (r > max) {\n- flags = float_flag_invalid;\n- r = max;\n- }\n- break;\n-\n- default:\n- g_assert_not_reached();\n- }\n-\n- float_raise(flags, s);\n- return r;\n-}\n+ * Floating-point to signed integer conversions\n+ */\n \n int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale,\n float_status *s)\n@@ -2421,7 +2370,7 @@ int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale,\n FloatParts64 p;\n \n float16_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT8_MIN, INT8_MAX, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT8_MIN, INT8_MAX, s);\n }\n \n int16_t float16_to_int16_scalbn(float16 a, FloatRoundMode rmode, int scale,\n@@ -2430,7 +2379,7 @@ int16_t float16_to_int16_scalbn(float16 a, FloatRoundMode rmode, int scale,\n FloatParts64 p;\n \n float16_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT16_MIN, INT16_MAX, s);\n }\n \n int32_t float16_to_int32_scalbn(float16 a, FloatRoundMode rmode, int scale,\n@@ -2439,7 +2388,7 @@ int32_t float16_to_int32_scalbn(float16 a, FloatRoundMode rmode, int scale,\n FloatParts64 p;\n \n float16_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s);\n }\n \n int64_t float16_to_int64_scalbn(float16 a, FloatRoundMode rmode, int scale,\n@@ -2448,7 +2397,7 @@ int64_t float16_to_int64_scalbn(float16 a, FloatRoundMode rmode, int scale,\n FloatParts64 p;\n \n float16_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s);\n }\n \n int16_t float32_to_int16_scalbn(float32 a, FloatRoundMode rmode, int scale,\n@@ -2457,7 +2406,7 @@ int16_t float32_to_int16_scalbn(float32 a, FloatRoundMode rmode, int scale,\n FloatParts64 p;\n \n float32_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT16_MIN, INT16_MAX, s);\n }\n \n int32_t float32_to_int32_scalbn(float32 a, FloatRoundMode rmode, int scale,\n@@ -2466,7 +2415,7 @@ int32_t float32_to_int32_scalbn(float32 a, FloatRoundMode rmode, int scale,\n FloatParts64 p;\n \n float32_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s);\n }\n \n int64_t float32_to_int64_scalbn(float32 a, FloatRoundMode rmode, int scale,\n@@ -2475,7 +2424,7 @@ int64_t float32_to_int64_scalbn(float32 a, FloatRoundMode rmode, int scale,\n FloatParts64 p;\n \n float32_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s);\n }\n \n int16_t float64_to_int16_scalbn(float64 a, FloatRoundMode rmode, int scale,\n@@ -2484,7 +2433,7 @@ int16_t float64_to_int16_scalbn(float64 a, FloatRoundMode rmode, int scale,\n FloatParts64 p;\n \n float64_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT16_MIN, INT16_MAX, s);\n }\n \n int32_t float64_to_int32_scalbn(float64 a, FloatRoundMode rmode, int scale,\n@@ -2493,7 +2442,7 @@ int32_t float64_to_int32_scalbn(float64 a, FloatRoundMode rmode, int scale,\n FloatParts64 p;\n \n float64_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s);\n }\n \n int64_t float64_to_int64_scalbn(float64 a, FloatRoundMode rmode, int scale,\n@@ -2502,7 +2451,52 @@ int64_t float64_to_int64_scalbn(float64 a, FloatRoundMode rmode, int scale,\n FloatParts64 p;\n \n float64_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s);\n+}\n+\n+int16_t bfloat16_to_int16_scalbn(bfloat16 a, FloatRoundMode rmode, int scale,\n+ float_status *s)\n+{\n+ FloatParts64 p;\n+\n+ bfloat16_unpack_canonical(&p, a, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT16_MIN, INT16_MAX, s);\n+}\n+\n+int32_t bfloat16_to_int32_scalbn(bfloat16 a, FloatRoundMode rmode, int scale,\n+ float_status *s)\n+{\n+ FloatParts64 p;\n+\n+ bfloat16_unpack_canonical(&p, a, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s);\n+}\n+\n+int64_t bfloat16_to_int64_scalbn(bfloat16 a, FloatRoundMode rmode, int scale,\n+ float_status *s)\n+{\n+ FloatParts64 p;\n+\n+ bfloat16_unpack_canonical(&p, a, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s);\n+}\n+\n+static int32_t float128_to_int32_scalbn(float128 a, FloatRoundMode rmode,\n+ int scale, float_status *s)\n+{\n+ FloatParts128 p;\n+\n+ float128_unpack_canonical(&p, a, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s);\n+}\n+\n+static int64_t float128_to_int64_scalbn(float128 a, FloatRoundMode rmode,\n+ int scale, float_status *s)\n+{\n+ FloatParts128 p;\n+\n+ float128_unpack_canonical(&p, a, s);\n+ return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s);\n }\n \n int8_t float16_to_int8(float16 a, float_status *s)\n@@ -2555,6 +2549,16 @@ int64_t float64_to_int64(float64 a, float_status *s)\n return float64_to_int64_scalbn(a, s->float_rounding_mode, 0, s);\n }\n \n+int32_t float128_to_int32(float128 a, float_status *s)\n+{\n+ return float128_to_int32_scalbn(a, s->float_rounding_mode, 0, s);\n+}\n+\n+int64_t float128_to_int64(float128 a, float_status *s)\n+{\n+ return float128_to_int64_scalbn(a, s->float_rounding_mode, 0, s);\n+}\n+\n int16_t float16_to_int16_round_to_zero(float16 a, float_status *s)\n {\n return float16_to_int16_scalbn(a, float_round_to_zero, 0, s);\n@@ -2600,36 +2604,14 @@ int64_t float64_to_int64_round_to_zero(float64 a, float_status *s)\n return float64_to_int64_scalbn(a, float_round_to_zero, 0, s);\n }\n \n-/*\n- * Returns the result of converting the floating-point value `a' to\n- * the two's complement integer format.\n- */\n-\n-int16_t bfloat16_to_int16_scalbn(bfloat16 a, FloatRoundMode rmode, int scale,\n- float_status *s)\n+int32_t float128_to_int32_round_to_zero(float128 a, float_status *s)\n {\n- FloatParts64 p;\n-\n- bfloat16_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s);\n+ return float128_to_int32_scalbn(a, float_round_to_zero, 0, s);\n }\n \n-int32_t bfloat16_to_int32_scalbn(bfloat16 a, FloatRoundMode rmode, int scale,\n- float_status *s)\n+int64_t float128_to_int64_round_to_zero(float128 a, float_status *s)\n {\n- FloatParts64 p;\n-\n- bfloat16_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s);\n-}\n-\n-int64_t bfloat16_to_int64_scalbn(bfloat16 a, FloatRoundMode rmode, int scale,\n- float_status *s)\n-{\n- FloatParts64 p;\n-\n- bfloat16_unpack_canonical(&p, a, s);\n- return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s);\n+ return float128_to_int64_scalbn(a, float_round_to_zero, 0, s);\n }\n \n int16_t bfloat16_to_int16(bfloat16 a, float_status *s)\n@@ -6553,191 +6535,6 @@ floatx80 floatx80_sqrt(floatx80 a, float_status *status)\n 0, zExp, zSig0, zSig1, status);\n }\n \n-/*----------------------------------------------------------------------------\n-| Returns the result of converting the quadruple-precision floating-point\n-| value `a' to the 32-bit two's complement integer format. The conversion\n-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\n-| Arithmetic---which means in particular that the conversion is rounded\n-| according to the current rounding mode. If `a' is a NaN, the largest\n-| positive integer is returned. Otherwise, if the conversion overflows, the\n-| largest integer with the same sign as `a' is returned.\n-*----------------------------------------------------------------------------*/\n-\n-int32_t float128_to_int32(float128 a, float_status *status)\n-{\n- bool aSign;\n- int32_t aExp, shiftCount;\n- uint64_t aSig0, aSig1;\n-\n- aSig1 = extractFloat128Frac1( a );\n- aSig0 = extractFloat128Frac0( a );\n- aExp = extractFloat128Exp( a );\n- aSign = extractFloat128Sign( a );\n- if ( ( aExp == 0x7FFF ) && ( aSig0 | aSig1 ) ) aSign = 0;\n- if ( aExp ) aSig0 |= UINT64_C(0x0001000000000000);\n- aSig0 |= ( aSig1 != 0 );\n- shiftCount = 0x4028 - aExp;\n- if ( 0 < shiftCount ) shift64RightJamming( aSig0, shiftCount, &aSig0 );\n- return roundAndPackInt32(aSign, aSig0, status);\n-\n-}\n-\n-/*----------------------------------------------------------------------------\n-| Returns the result of converting the quadruple-precision floating-point\n-| value `a' to the 32-bit two's complement integer format. The conversion\n-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\n-| Arithmetic, except that the conversion is always rounded toward zero. If\n-| `a' is a NaN, the largest positive integer is returned. Otherwise, if the\n-| conversion overflows, the largest integer with the same sign as `a' is\n-| returned.\n-*----------------------------------------------------------------------------*/\n-\n-int32_t float128_to_int32_round_to_zero(float128 a, float_status *status)\n-{\n- bool aSign;\n- int32_t aExp, shiftCount;\n- uint64_t aSig0, aSig1, savedASig;\n- int32_t z;\n-\n- aSig1 = extractFloat128Frac1( a );\n- aSig0 = extractFloat128Frac0( a );\n- aExp = extractFloat128Exp( a );\n- aSign = extractFloat128Sign( a );\n- aSig0 |= ( aSig1 != 0 );\n- if ( 0x401E < aExp ) {\n- if ( ( aExp == 0x7FFF ) && aSig0 ) aSign = 0;\n- goto invalid;\n- }\n- else if ( aExp < 0x3FFF ) {\n- if (aExp || aSig0) {\n- float_raise(float_flag_inexact, status);\n- }\n- return 0;\n- }\n- aSig0 |= UINT64_C(0x0001000000000000);\n- shiftCount = 0x402F - aExp;\n- savedASig = aSig0;\n- aSig0 >>= shiftCount;\n- z = aSig0;\n- if ( aSign ) z = - z;\n- if ( ( z < 0 ) ^ aSign ) {\n- invalid:\n- float_raise(float_flag_invalid, status);\n- return aSign ? INT32_MIN : INT32_MAX;\n- }\n- if ( ( aSig0<<shiftCount ) != savedASig ) {\n- float_raise(float_flag_inexact, status);\n- }\n- return z;\n-\n-}\n-\n-/*----------------------------------------------------------------------------\n-| Returns the result of converting the quadruple-precision floating-point\n-| value `a' to the 64-bit two's complement integer format. The conversion\n-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\n-| Arithmetic---which means in particular that the conversion is rounded\n-| according to the current rounding mode. If `a' is a NaN, the largest\n-| positive integer is returned. Otherwise, if the conversion overflows, the\n-| largest integer with the same sign as `a' is returned.\n-*----------------------------------------------------------------------------*/\n-\n-int64_t float128_to_int64(float128 a, float_status *status)\n-{\n- bool aSign;\n- int32_t aExp, shiftCount;\n- uint64_t aSig0, aSig1;\n-\n- aSig1 = extractFloat128Frac1( a );\n- aSig0 = extractFloat128Frac0( a );\n- aExp = extractFloat128Exp( a );\n- aSign = extractFloat128Sign( a );\n- if ( aExp ) aSig0 |= UINT64_C(0x0001000000000000);\n- shiftCount = 0x402F - aExp;\n- if ( shiftCount <= 0 ) {\n- if ( 0x403E < aExp ) {\n- float_raise(float_flag_invalid, status);\n- if ( ! aSign\n- || ( ( aExp == 0x7FFF )\n- && ( aSig1 || ( aSig0 != UINT64_C(0x0001000000000000) ) )\n- )\n- ) {\n- return INT64_MAX;\n- }\n- return INT64_MIN;\n- }\n- shortShift128Left( aSig0, aSig1, - shiftCount, &aSig0, &aSig1 );\n- }\n- else {\n- shift64ExtraRightJamming( aSig0, aSig1, shiftCount, &aSig0, &aSig1 );\n- }\n- return roundAndPackInt64(aSign, aSig0, aSig1, status);\n-\n-}\n-\n-/*----------------------------------------------------------------------------\n-| Returns the result of converting the quadruple-precision floating-point\n-| value `a' to the 64-bit two's complement integer format. The conversion\n-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\n-| Arithmetic, except that the conversion is always rounded toward zero.\n-| If `a' is a NaN, the largest positive integer is returned. Otherwise, if\n-| the conversion overflows, the largest integer with the same sign as `a' is\n-| returned.\n-*----------------------------------------------------------------------------*/\n-\n-int64_t float128_to_int64_round_to_zero(float128 a, float_status *status)\n-{\n- bool aSign;\n- int32_t aExp, shiftCount;\n- uint64_t aSig0, aSig1;\n- int64_t z;\n-\n- aSig1 = extractFloat128Frac1( a );\n- aSig0 = extractFloat128Frac0( a );\n- aExp = extractFloat128Exp( a );\n- aSign = extractFloat128Sign( a );\n- if ( aExp ) aSig0 |= UINT64_C(0x0001000000000000);\n- shiftCount = aExp - 0x402F;\n- if ( 0 < shiftCount ) {\n- if ( 0x403E <= aExp ) {\n- aSig0 &= UINT64_C(0x0000FFFFFFFFFFFF);\n- if ( ( a.high == UINT64_C(0xC03E000000000000) )\n- && ( aSig1 < UINT64_C(0x0002000000000000) ) ) {\n- if (aSig1) {\n- float_raise(float_flag_inexact, status);\n- }\n- }\n- else {\n- float_raise(float_flag_invalid, status);\n- if ( ! aSign || ( ( aExp == 0x7FFF ) && ( aSig0 | aSig1 ) ) ) {\n- return INT64_MAX;\n- }\n- }\n- return INT64_MIN;\n- }\n- z = ( aSig0<<shiftCount ) | ( aSig1>>( ( - shiftCount ) & 63 ) );\n- if ( (uint64_t) ( aSig1<<shiftCount ) ) {\n- float_raise(float_flag_inexact, status);\n- }\n- }\n- else {\n- if ( aExp < 0x3FFF ) {\n- if ( aExp | aSig0 | aSig1 ) {\n- float_raise(float_flag_inexact, status);\n- }\n- return 0;\n- }\n- z = aSig0>>( - shiftCount );\n- if ( aSig1\n- || ( shiftCount && (uint64_t) ( aSig0<<( shiftCount & 63 ) ) ) ) {\n- float_raise(float_flag_inexact, status);\n- }\n- }\n- if ( aSign ) z = - z;\n- return z;\n-\n-}\n-\n /*----------------------------------------------------------------------------\n | Returns the result of converting the quadruple-precision floating-point value\n | `a' to the 64-bit unsigned integer format. The conversion is\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex b2c4624d8c..a897a5a743 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -751,3 +751,67 @@ static void partsN(round_to_int)(FloatPartsN *a, FloatRoundMode rmode,\n g_assert_not_reached();\n }\n }\n+\n+/*\n+ * Returns the result of converting the floating-point value `a' to\n+ * the two's complement integer format. The conversion is performed\n+ * according to the IEC/IEEE Standard for Binary Floating-Point\n+ * Arithmetic---which means in particular that the conversion is\n+ * rounded according to the current rounding mode. If `a' is a NaN,\n+ * the largest positive integer is returned. Otherwise, if the\n+ * conversion overflows, the largest integer with the same sign as `a'\n+ * is returned.\n+*/\n+static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode,\n+ int scale, int64_t min, int64_t max,\n+ float_status *s)\n+{\n+ int flags = 0;\n+ uint64_t r;\n+\n+ switch (p->cls) {\n+ case float_class_snan:\n+ case float_class_qnan:\n+ flags = float_flag_invalid;\n+ r = max;\n+ break;\n+\n+ case float_class_inf:\n+ flags = float_flag_invalid;\n+ r = p->sign ? min : max;\n+ break;\n+\n+ case float_class_zero:\n+ return 0;\n+\n+ case float_class_normal:\n+ /* TODO: N - 2 is frac_size for rounding; could use input fmt. */\n+ if (parts_round_to_int_normal(p, rmode, scale, N - 2)) {\n+ flags = float_flag_inexact;\n+ }\n+\n+ if (p->exp <= DECOMPOSED_BINARY_POINT) {\n+ r = p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp);\n+ } else {\n+ r = UINT64_MAX;\n+ }\n+ if (p->sign) {\n+ if (r <= -(uint64_t)min) {\n+ r = -r;\n+ } else {\n+ flags = float_flag_invalid;\n+ r = min;\n+ }\n+ } else if (r > max) {\n+ flags = float_flag_invalid;\n+ r = max;\n+ }\n+ break;\n+\n+ default:\n+ g_assert_not_reached();\n+ }\n+\n+ float_raise(flags, s);\n+ return r;\n+}\n", "prefixes": [ "46/72" ] }