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GET /api/patches/1475735/?format=api
{ "id": 1475735, "url": "http://patchwork.ozlabs.org/api/patches/1475735/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-37-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-37-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:47:26", "name": "[36/72] softfloat: Move mul_floats to softfloat-parts.c.inc", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e682f34d0db71c159be6cad4ef9f024825ee2e7c", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-37-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475735/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475735/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x102c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Rename to parts$N_mul.\nReimplement float128_mul with FloatParts128.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat.c | 206 ++++++++++++++------------------------\n fpu/softfloat-parts.c.inc | 51 ++++++++++\n 2 files changed, 128 insertions(+), 129 deletions(-)", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex f48e6b1f64..4f498c11e5 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -532,6 +532,16 @@ typedef struct {\n uint64_t frac_lo;\n } FloatParts128;\n \n+typedef struct {\n+ FloatClass cls;\n+ bool sign;\n+ int32_t exp;\n+ uint64_t frac_hi;\n+ uint64_t frac_hm; /* high-middle */\n+ uint64_t frac_lm; /* low-middle */\n+ uint64_t frac_lo;\n+} FloatParts256;\n+\n /* These apply to the most significant word of each FloatPartsN. */\n #define DECOMPOSED_BINARY_POINT 63\n #define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT)\n@@ -768,6 +778,14 @@ static FloatParts128 *parts128_addsub(FloatParts128 *a, FloatParts128 *b,\n #define parts_addsub(A, B, S, Z) \\\n PARTS_GENERIC_64_128(addsub, A)(A, B, S, Z)\n \n+static FloatParts64 *parts64_mul(FloatParts64 *a, FloatParts64 *b,\n+ float_status *s);\n+static FloatParts128 *parts128_mul(FloatParts128 *a, FloatParts128 *b,\n+ float_status *s);\n+\n+#define parts_mul(A, B, S) \\\n+ PARTS_GENERIC_64_128(mul, A)(A, B, S)\n+\n /*\n * Helper functions for softfloat-parts.c.inc, per-size operations.\n */\n@@ -858,6 +876,19 @@ static bool frac128_eqz(FloatParts128 *a)\n \n #define frac_eqz(A) FRAC_GENERIC_64_128(eqz, A)(A)\n \n+static void frac64_mulw(FloatParts128 *r, FloatParts64 *a, FloatParts64 *b)\n+{\n+ mulu64(&r->frac_lo, &r->frac_hi, a->frac, b->frac);\n+}\n+\n+static void frac128_mulw(FloatParts256 *r, FloatParts128 *a, FloatParts128 *b)\n+{\n+ mul128To256(a->frac_hi, a->frac_lo, b->frac_hi, b->frac_lo,\n+ &r->frac_hi, &r->frac_hm, &r->frac_lm, &r->frac_lo);\n+}\n+\n+#define frac_mulw(R, A, B) FRAC_GENERIC_64_128(mulw, A)(R, A, B)\n+\n static void frac64_neg(FloatParts64 *a)\n {\n a->frac = -a->frac;\n@@ -954,23 +985,42 @@ static bool frac128_sub(FloatParts128 *r, FloatParts128 *a, FloatParts128 *b)\n \n #define frac_sub(R, A, B) FRAC_GENERIC_64_128(sub, R)(R, A, B)\n \n+static void frac64_truncjam(FloatParts64 *r, FloatParts128 *a)\n+{\n+ r->frac = a->frac_hi | (a->frac_lo != 0);\n+}\n+\n+static void frac128_truncjam(FloatParts128 *r, FloatParts256 *a)\n+{\n+ r->frac_hi = a->frac_hi;\n+ r->frac_lo = a->frac_hm | ((a->frac_lm | a->frac_lo) != 0);\n+}\n+\n+#define frac_truncjam(R, A) FRAC_GENERIC_64_128(truncjam, R)(R, A)\n+\n #define partsN(NAME) glue(glue(glue(parts,N),_),NAME)\n #define FloatPartsN glue(FloatParts,N)\n+#define FloatPartsW glue(FloatParts,W)\n \n #define N 64\n+#define W 128\n \n #include \"softfloat-parts-addsub.c.inc\"\n #include \"softfloat-parts.c.inc\"\n \n #undef N\n+#undef W\n #define N 128\n+#define W 256\n \n #include \"softfloat-parts-addsub.c.inc\"\n #include \"softfloat-parts.c.inc\"\n \n #undef N\n+#undef W\n #undef partsN\n #undef FloatPartsN\n+#undef FloatPartsW\n \n /*\n * Pack/unpack routines with a specific FloatFmt.\n@@ -1249,89 +1299,42 @@ float128 float128_sub(float128 a, float128 b, float_status *status)\n }\n \n /*\n- * Returns the result of multiplying the floating-point values `a' and\n- * `b'. The operation is performed according to the IEC/IEEE Standard\n- * for Binary Floating-Point Arithmetic.\n+ * Multiplication\n */\n \n-static FloatParts64 mul_floats(FloatParts64 a, FloatParts64 b, float_status *s)\n-{\n- bool sign = a.sign ^ b.sign;\n-\n- if (a.cls == float_class_normal && b.cls == float_class_normal) {\n- uint64_t hi, lo;\n- int exp = a.exp + b.exp;\n-\n- mul64To128(a.frac, b.frac, &hi, &lo);\n- if (hi & DECOMPOSED_IMPLICIT_BIT) {\n- exp += 1;\n- } else {\n- hi <<= 1;\n- }\n- hi |= (lo != 0);\n-\n- /* Re-use a */\n- a.exp = exp;\n- a.sign = sign;\n- a.frac = hi;\n- return a;\n- }\n- /* handle all the NaN cases */\n- if (is_nan(a.cls) || is_nan(b.cls)) {\n- return *parts_pick_nan(&a, &b, s);\n- }\n- /* Inf * Zero == NaN */\n- if ((a.cls == float_class_inf && b.cls == float_class_zero) ||\n- (a.cls == float_class_zero && b.cls == float_class_inf)) {\n- float_raise(float_flag_invalid, s);\n- parts_default_nan(&a, s);\n- return a;\n- }\n- /* Multiply by 0 or Inf */\n- if (a.cls == float_class_inf || a.cls == float_class_zero) {\n- a.sign = sign;\n- return a;\n- }\n- if (b.cls == float_class_inf || b.cls == float_class_zero) {\n- b.sign = sign;\n- return b;\n- }\n- g_assert_not_reached();\n-}\n-\n float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *status)\n {\n- FloatParts64 pa, pb, pr;\n+ FloatParts64 pa, pb, *pr;\n \n float16_unpack_canonical(&pa, a, status);\n float16_unpack_canonical(&pb, b, status);\n- pr = mul_floats(pa, pb, status);\n+ pr = parts_mul(&pa, &pb, status);\n \n- return float16_round_pack_canonical(&pr, status);\n+ return float16_round_pack_canonical(pr, status);\n }\n \n static float32 QEMU_SOFTFLOAT_ATTR\n soft_f32_mul(float32 a, float32 b, float_status *status)\n {\n- FloatParts64 pa, pb, pr;\n+ FloatParts64 pa, pb, *pr;\n \n float32_unpack_canonical(&pa, a, status);\n float32_unpack_canonical(&pb, b, status);\n- pr = mul_floats(pa, pb, status);\n+ pr = parts_mul(&pa, &pb, status);\n \n- return float32_round_pack_canonical(&pr, status);\n+ return float32_round_pack_canonical(pr, status);\n }\n \n static float64 QEMU_SOFTFLOAT_ATTR\n soft_f64_mul(float64 a, float64 b, float_status *status)\n {\n- FloatParts64 pa, pb, pr;\n+ FloatParts64 pa, pb, *pr;\n \n float64_unpack_canonical(&pa, a, status);\n float64_unpack_canonical(&pb, b, status);\n- pr = mul_floats(pa, pb, status);\n+ pr = parts_mul(&pa, &pb, status);\n \n- return float64_round_pack_canonical(&pr, status);\n+ return float64_round_pack_canonical(pr, status);\n }\n \n static float hard_f32_mul(float a, float b)\n@@ -1358,20 +1361,28 @@ float64_mul(float64 a, float64 b, float_status *s)\n f64_is_zon2, f64_addsubmul_post);\n }\n \n-/*\n- * Returns the result of multiplying the bfloat16\n- * values `a' and `b'.\n- */\n-\n-bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status)\n+bfloat16 QEMU_FLATTEN\n+bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status)\n {\n- FloatParts64 pa, pb, pr;\n+ FloatParts64 pa, pb, *pr;\n \n bfloat16_unpack_canonical(&pa, a, status);\n bfloat16_unpack_canonical(&pb, b, status);\n- pr = mul_floats(pa, pb, status);\n+ pr = parts_mul(&pa, &pb, status);\n \n- return bfloat16_round_pack_canonical(&pr, status);\n+ return bfloat16_round_pack_canonical(pr, status);\n+}\n+\n+float128 QEMU_FLATTEN\n+float128_mul(float128 a, float128 b, float_status *status)\n+{\n+ FloatParts128 pa, pb, *pr;\n+\n+ float128_unpack_canonical(&pa, a, status);\n+ float128_unpack_canonical(&pb, b, status);\n+ pr = parts_mul(&pa, &pb, status);\n+\n+ return float128_round_pack_canonical(pr, status);\n }\n \n /*\n@@ -7067,69 +7078,6 @@ float128 float128_round_to_int(float128 a, float_status *status)\n \n }\n \n-/*----------------------------------------------------------------------------\n-| Returns the result of multiplying the quadruple-precision floating-point\n-| values `a' and `b'. The operation is performed according to the IEC/IEEE\n-| Standard for Binary Floating-Point Arithmetic.\n-*----------------------------------------------------------------------------*/\n-\n-float128 float128_mul(float128 a, float128 b, float_status *status)\n-{\n- bool aSign, bSign, zSign;\n- int32_t aExp, bExp, zExp;\n- uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2, zSig3;\n-\n- aSig1 = extractFloat128Frac1( a );\n- aSig0 = extractFloat128Frac0( a );\n- aExp = extractFloat128Exp( a );\n- aSign = extractFloat128Sign( a );\n- bSig1 = extractFloat128Frac1( b );\n- bSig0 = extractFloat128Frac0( b );\n- bExp = extractFloat128Exp( b );\n- bSign = extractFloat128Sign( b );\n- zSign = aSign ^ bSign;\n- if ( aExp == 0x7FFF ) {\n- if ( ( aSig0 | aSig1 )\n- || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) {\n- return propagateFloat128NaN(a, b, status);\n- }\n- if ( ( bExp | bSig0 | bSig1 ) == 0 ) goto invalid;\n- return packFloat128( zSign, 0x7FFF, 0, 0 );\n- }\n- if ( bExp == 0x7FFF ) {\n- if (bSig0 | bSig1) {\n- return propagateFloat128NaN(a, b, status);\n- }\n- if ( ( aExp | aSig0 | aSig1 ) == 0 ) {\n- invalid:\n- float_raise(float_flag_invalid, status);\n- return float128_default_nan(status);\n- }\n- return packFloat128( zSign, 0x7FFF, 0, 0 );\n- }\n- if ( aExp == 0 ) {\n- if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );\n- normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\n- }\n- if ( bExp == 0 ) {\n- if ( ( bSig0 | bSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );\n- normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );\n- }\n- zExp = aExp + bExp - 0x4000;\n- aSig0 |= UINT64_C(0x0001000000000000);\n- shortShift128Left( bSig0, bSig1, 16, &bSig0, &bSig1 );\n- mul128To256( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1, &zSig2, &zSig3 );\n- add128( zSig0, zSig1, aSig0, aSig1, &zSig0, &zSig1 );\n- zSig2 |= ( zSig3 != 0 );\n- if (UINT64_C( 0x0002000000000000) <= zSig0 ) {\n- shift128ExtraRightJamming(\n- zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 );\n- ++zExp;\n- }\n- return roundAndPackFloat128(zSign, zExp, zSig0, zSig1, zSig2, status);\n-\n-}\n-\n /*----------------------------------------------------------------------------\n | Returns the result of dividing the quadruple-precision floating-point value\n | `a' by the corresponding value `b'. The operation is performed according to\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex cfce9f6421..9a67ab2bea 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -362,3 +362,54 @@ static FloatPartsN *partsN(addsub)(FloatPartsN *a, FloatPartsN *b,\n p_nan:\n return parts_pick_nan(a, b, s);\n }\n+\n+/*\n+ * Returns the result of multiplying the floating-point values `a' and\n+ * `b'. The operation is performed according to the IEC/IEEE Standard\n+ * for Binary Floating-Point Arithmetic.\n+ */\n+static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b,\n+ float_status *s)\n+{\n+ int ab_mask = float_cmask(a->cls) | float_cmask(b->cls);\n+ bool sign = a->sign ^ b->sign;\n+\n+ if (likely(ab_mask == float_cmask_normal)) {\n+ FloatPartsW tmp;\n+\n+ frac_mulw(&tmp, a, b);\n+ frac_truncjam(a, &tmp);\n+\n+ a->exp += b->exp + 1;\n+ if (!(a->frac_hi & DECOMPOSED_IMPLICIT_BIT)) {\n+ frac_add(a, a, a);\n+ a->exp -= 1;\n+ }\n+\n+ a->sign = sign;\n+ return a;\n+ }\n+\n+ /* Inf * Zero == NaN */\n+ if (unlikely(ab_mask == float_cmask_infzero)) {\n+ float_raise(float_flag_invalid, s);\n+ parts_default_nan(a, s);\n+ return a;\n+ }\n+\n+ if (unlikely(ab_mask & float_cmask_anynan)) {\n+ return parts_pick_nan(a, b, s);\n+ }\n+\n+ /* Multiply by 0 or Inf */\n+ if (ab_mask & float_cmask_inf) {\n+ a->cls = float_class_inf;\n+ a->sign = sign;\n+ return a;\n+ }\n+\n+ g_assert(ab_mask & float_cmask_zero);\n+ a->cls = float_class_zero;\n+ a->sign = sign;\n+ return a;\n+}\n", "prefixes": [ "36/72" ] }