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GET /api/patches/1475732/?format=api
{ "id": 1475732, "url": "http://patchwork.ozlabs.org/api/patches/1475732/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-27-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-27-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:47:16", "name": "[26/72] softfloat: Convert float128_silence_nan to parts", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b101fc4d1a9d36aa1c42a9f1e29849f0ec1d06da", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-27-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475732/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475732/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pf1-x433.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "This is the minimal change that also introduces float128_params,\nfloat128_unpack_raw, and float128_pack_raw without running into\nunused symbol Werrors.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat.c | 96 +++++++++++++++++++++++++++++-----\n fpu/softfloat-specialize.c.inc | 25 +++------\n 2 files changed, 89 insertions(+), 32 deletions(-)", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 2d6f61ee7a..073b80d502 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -500,14 +500,12 @@ static inline __attribute__((unused)) bool is_qnan(FloatClass c)\n }\n \n /*\n- * Structure holding all of the decomposed parts of a float. The\n- * exponent is unbiased and the fraction is normalized. All\n- * calculations are done with a 64 bit fraction and then rounded as\n- * appropriate for the final format.\n+ * Structure holding all of the decomposed parts of a float.\n+ * The exponent is unbiased and the fraction is normalized.\n *\n- * Thanks to the packed FloatClass a decent compiler should be able to\n- * fit the whole structure into registers and avoid using the stack\n- * for parameter passing.\n+ * The fraction words are stored in big-endian word ordering,\n+ * so that truncation from a larger format to a smaller format\n+ * can be done simply by ignoring subsequent elements.\n */\n \n typedef struct {\n@@ -526,6 +524,15 @@ typedef struct {\n };\n } FloatParts64;\n \n+typedef struct {\n+ FloatClass cls;\n+ bool sign;\n+ int32_t exp;\n+ uint64_t frac_hi;\n+ uint64_t frac_lo;\n+} FloatParts128;\n+\n+/* These apply to the most significant word of each FloatPartsN. */\n #define DECOMPOSED_BINARY_POINT 63\n #define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT)\n \n@@ -561,11 +568,11 @@ typedef struct {\n .exp_bias = ((1 << E) - 1) >> 1, \\\n .exp_max = (1 << E) - 1, \\\n .frac_size = F, \\\n- .frac_shift = DECOMPOSED_BINARY_POINT - F, \\\n- .frac_lsb = 1ull << (DECOMPOSED_BINARY_POINT - F), \\\n- .frac_lsbm1 = 1ull << ((DECOMPOSED_BINARY_POINT - F) - 1), \\\n- .round_mask = (1ull << (DECOMPOSED_BINARY_POINT - F)) - 1, \\\n- .roundeven_mask = (2ull << (DECOMPOSED_BINARY_POINT - F)) - 1\n+ .frac_shift = (-F - 1) & 63, \\\n+ .frac_lsb = 1ull << ((-F - 1) & 63), \\\n+ .frac_lsbm1 = 1ull << ((-F - 2) & 63), \\\n+ .round_mask = (1ull << ((-F - 1) & 63)) - 1, \\\n+ .roundeven_mask = (2ull << ((-F - 1) & 63)) - 1\n \n static const FloatFmt float16_params = {\n FLOAT_PARAMS(5, 10)\n@@ -588,6 +595,10 @@ static const FloatFmt float64_params = {\n FLOAT_PARAMS(11, 52)\n };\n \n+static const FloatFmt float128_params = {\n+ FLOAT_PARAMS(15, 112)\n+};\n+\n /* Unpack a float to parts, but do not canonicalize. */\n static void unpack_raw64(FloatParts64 *r, const FloatFmt *fmt, uint64_t raw)\n {\n@@ -622,6 +633,20 @@ static inline void float64_unpack_raw(FloatParts64 *p, float64 f)\n unpack_raw64(p, &float64_params, f);\n }\n \n+static void float128_unpack_raw(FloatParts128 *p, float128 f)\n+{\n+ const int f_size = float128_params.frac_size - 64;\n+ const int e_size = float128_params.exp_size;\n+\n+ *p = (FloatParts128) {\n+ .cls = float_class_unclassified,\n+ .sign = extract64(f.high, f_size + e_size, 1),\n+ .exp = extract64(f.high, f_size, e_size),\n+ .frac_hi = extract64(f.high, 0, f_size),\n+ .frac_lo = f.low,\n+ };\n+}\n+\n /* Pack a float from parts, but do not canonicalize. */\n static uint64_t pack_raw64(const FloatParts64 *p, const FloatFmt *fmt)\n {\n@@ -655,6 +680,18 @@ static inline float64 float64_pack_raw(const FloatParts64 *p)\n return make_float64(pack_raw64(p, &float64_params));\n }\n \n+static float128 float128_pack_raw(const FloatParts128 *p)\n+{\n+ const int f_size = float128_params.frac_size - 64;\n+ const int e_size = float128_params.exp_size;\n+ uint64_t hi;\n+\n+ hi = (uint64_t)p->sign << (f_size + e_size);\n+ hi = deposit64(hi, f_size, e_size, p->exp);\n+ hi = deposit64(hi, 0, f_size, p->frac_hi);\n+ return make_float128(hi, p->frac_lo);\n+}\n+\n /*----------------------------------------------------------------------------\n | Functions and definitions to determine: (1) whether tininess for underflow\n | is detected before or after rounding by default, (2) what (if anything)\n@@ -665,8 +702,30 @@ static inline float64 float64_pack_raw(const FloatParts64 *p)\n *----------------------------------------------------------------------------*/\n #include \"softfloat-specialize.c.inc\"\n \n+#define PARTS_GENERIC_64_128(NAME, P) \\\n+ QEMU_GENERIC(P, (FloatParts128 *, parts128_##NAME), parts64_##NAME)\n+\n #define parts_default_nan parts64_default_nan\n-#define parts_silence_nan parts64_silence_nan\n+#define parts_silence_nan(P, S) PARTS_GENERIC_64_128(silence_nan, P)(P, S)\n+\n+\n+/*\n+ * Helper functions for softfloat-parts.c.inc, per-size operations.\n+ */\n+\n+static void frac128_shl(FloatParts128 *a, int c)\n+{\n+ shift128Left(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo);\n+}\n+\n+#define frac_shl(A, C) frac128_shl(A, C)\n+\n+static void frac128_shr(FloatParts128 *a, int c)\n+{\n+ shift128Right(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo);\n+}\n+\n+#define frac_shr(A, C) frac128_shr(A, C)\n \n /* Canonicalize EXP and FRAC, setting CLS. */\n static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *parm,\n@@ -3850,6 +3909,17 @@ bfloat16 bfloat16_silence_nan(bfloat16 a, float_status *status)\n return bfloat16_pack_raw(&p);\n }\n \n+float128 float128_silence_nan(float128 a, float_status *status)\n+{\n+ FloatParts128 p;\n+\n+ float128_unpack_raw(&p, a);\n+ frac_shl(&p, float128_params.frac_shift);\n+ parts_silence_nan(&p, status);\n+ frac_shr(&p, float128_params.frac_shift);\n+ return float128_pack_raw(&p);\n+}\n+\n /*----------------------------------------------------------------------------\n | If `a' is denormal and we are in flush-to-zero mode then set the\n | input-denormal exception and return zero. Otherwise just return the value.\ndiff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc\nindex 2a1bc66633..d892016f0f 100644\n--- a/fpu/softfloat-specialize.c.inc\n+++ b/fpu/softfloat-specialize.c.inc\n@@ -198,6 +198,12 @@ static void parts64_silence_nan(FloatParts64 *p, float_status *status)\n p->cls = float_class_qnan;\n }\n \n+static void parts128_silence_nan(FloatParts128 *p, float_status *status)\n+{\n+ p->frac_hi = parts_silence_nan_frac(p->frac_hi, status);\n+ p->cls = float_class_qnan;\n+}\n+\n /*----------------------------------------------------------------------------\n | The pattern for a default generated extended double-precision NaN.\n *----------------------------------------------------------------------------*/\n@@ -1057,25 +1063,6 @@ bool float128_is_signaling_nan(float128 a, float_status *status)\n }\n }\n \n-/*----------------------------------------------------------------------------\n-| Returns a quiet NaN from a signalling NaN for the quadruple-precision\n-| floating point value `a'.\n-*----------------------------------------------------------------------------*/\n-\n-float128 float128_silence_nan(float128 a, float_status *status)\n-{\n- if (no_signaling_nans(status)) {\n- g_assert_not_reached();\n- } else {\n- if (snan_bit_is_one(status)) {\n- return float128_default_nan(status);\n- } else {\n- a.high |= UINT64_C(0x0000800000000000);\n- return a;\n- }\n- }\n-}\n-\n /*----------------------------------------------------------------------------\n | Returns the result of converting the quadruple-precision floating-point NaN\n | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid\n", "prefixes": [ "26/72" ] }