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GET /api/patches/1475726/?format=api
{ "id": 1475726, "url": "http://patchwork.ozlabs.org/api/patches/1475726/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-33-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-33-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:47:22", "name": "[32/72] softfloat: Move round_canonical to softfloat-parts.c.inc", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0210d4928df2f48e0d984a3bfe9cb34e49a6b5f6", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-33-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475726/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475726/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=NGpOakjV0VOj6azWVGKzsBGpzQYOaN2R/8eKbyrZbMU=;\n b=czqD0PycV2Zr9w+Dq14CTUTIBlCnfQTXQh1jVUcvWX8Jprvx2yETzOFe/JnoGSxsmJ\n 8IzIWNUBxlPTj7evVB6ZPMKZLZoSugdzHnqr/3UTRbO/pln5VsJZjqTxjcWORKlf3Fus\n Sw1wqOYR0iIruj5fp0VEVLfIkIyz1XxotvDk6xkHewAfWNXkxPPN+YqRSVINbl7fNmf5\n g/k3pClN+O+DCb5Of5a+iIGsVpsYClISpC3tdg9KIXOKgVa7GwOshnpmDMHGZO2rym4Y\n mKiCxY5JIAwkCW8hDdnXcQdi7QQSDS1d1SdHsh3WmF2yPnToV/2e1tuWek+MV07D1O+Z\n ba9Q==", "X-Gm-Message-State": "AOAM530AVUiGjQ4DbnF/xUF8EbdpoaSCbz+3/ojfpxAJUkj2u8pyQe43\n xrgH02BoI8anF6gx4mY7gPYIU5ybXrvSHw==", "X-Google-Smtp-Source": "\n ABdhPJy79x5Ck4KQBUi4NCsimPpQL9jOLFJY2suXjkmqCiHxWtYUyAylUuXxkgkAiaqIHy8syQr+WA==", "X-Received": "by 2002:a17:902:4d:b029:ec:94df:c9aa with SMTP id\n 71-20020a170902004db02900ec94dfc9aamr13263991pla.7.1620438504470;\n Fri, 07 May 2021 18:48:24 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PATCH 32/72] softfloat: Move round_canonical to\n softfloat-parts.c.inc", "Date": "Fri, 7 May 2021 18:47:22 -0700", "Message-Id": "<20210508014802.892561-33-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210508014802.892561-1-richard.henderson@linaro.org>", "References": "<20210508014802.892561-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::1032;\n envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "At the same time, convert to pointers, renaming to parts$N_uncanon,\nand define a macro for parts_uncanon using QEMU_GENERIC.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat.c | 201 +++++++++-----------------------------\n fpu/softfloat-parts.c.inc | 148 ++++++++++++++++++++++++++++\n 2 files changed, 193 insertions(+), 156 deletions(-)", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex bad4b54cd2..e9d644385d 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -740,6 +740,14 @@ static void parts128_canonicalize(FloatParts128 *p, float_status *status,\n #define parts_canonicalize(A, S, F) \\\n PARTS_GENERIC_64_128(canonicalize, A)(A, S, F)\n \n+static void parts64_uncanon(FloatParts64 *p, float_status *status,\n+ const FloatFmt *fmt);\n+static void parts128_uncanon(FloatParts128 *p, float_status *status,\n+ const FloatFmt *fmt);\n+\n+#define parts_uncanon(A, S, F) \\\n+ PARTS_GENERIC_64_128(uncanon, A)(A, S, F)\n+\n /*\n * Helper functions for softfloat-parts.c.inc, per-size operations.\n */\n@@ -747,6 +755,31 @@ static void parts128_canonicalize(FloatParts128 *p, float_status *status,\n #define FRAC_GENERIC_64_128(NAME, P) \\\n QEMU_GENERIC(P, (FloatParts128 *, frac128_##NAME), frac64_##NAME)\n \n+static bool frac64_addi(FloatParts64 *r, FloatParts64 *a, uint64_t c)\n+{\n+ return uadd64_overflow(a->frac, c, &r->frac);\n+}\n+\n+static bool frac128_addi(FloatParts128 *r, FloatParts128 *a, uint64_t c)\n+{\n+ c = uadd64_overflow(a->frac_lo, c, &r->frac_lo);\n+ return uadd64_overflow(a->frac_hi, c, &r->frac_hi);\n+}\n+\n+#define frac_addi(R, A, C) FRAC_GENERIC_64_128(addi, R)(R, A, C)\n+\n+static void frac64_allones(FloatParts64 *a)\n+{\n+ a->frac = -1;\n+}\n+\n+static void frac128_allones(FloatParts128 *a)\n+{\n+ a->frac_hi = a->frac_lo = -1;\n+}\n+\n+#define frac_allones(A) FRAC_GENERIC_64_128(allones, A)(A)\n+\n static int frac64_cmp(FloatParts64 *a, FloatParts64 *b)\n {\n return a->frac == b->frac ? 0 : a->frac < b->frac ? -1 : 1;\n@@ -845,161 +878,17 @@ static void frac128_shr(FloatParts128 *a, int c)\n \n #define frac_shr(A, C) FRAC_GENERIC_64_128(shr, A)(A, C)\n \n-\n-/* Round and uncanonicalize a floating-point number by parts. There\n- * are FRAC_SHIFT bits that may require rounding at the bottom of the\n- * fraction; these bits will be removed. The exponent will be biased\n- * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0].\n- */\n-\n-static FloatParts64 round_canonical(FloatParts64 p, float_status *s,\n- const FloatFmt *parm)\n+static void frac64_shrjam(FloatParts64 *a, int c)\n {\n- const uint64_t frac_lsb = parm->frac_lsb;\n- const uint64_t frac_lsbm1 = parm->frac_lsbm1;\n- const uint64_t round_mask = parm->round_mask;\n- const uint64_t roundeven_mask = parm->roundeven_mask;\n- const int exp_max = parm->exp_max;\n- const int frac_shift = parm->frac_shift;\n- uint64_t frac, inc;\n- int exp, flags = 0;\n- bool overflow_norm;\n-\n- frac = p.frac;\n- exp = p.exp;\n-\n- switch (p.cls) {\n- case float_class_normal:\n- switch (s->float_rounding_mode) {\n- case float_round_nearest_even:\n- overflow_norm = false;\n- inc = ((frac & roundeven_mask) != frac_lsbm1 ? frac_lsbm1 : 0);\n- break;\n- case float_round_ties_away:\n- overflow_norm = false;\n- inc = frac_lsbm1;\n- break;\n- case float_round_to_zero:\n- overflow_norm = true;\n- inc = 0;\n- break;\n- case float_round_up:\n- inc = p.sign ? 0 : round_mask;\n- overflow_norm = p.sign;\n- break;\n- case float_round_down:\n- inc = p.sign ? round_mask : 0;\n- overflow_norm = !p.sign;\n- break;\n- case float_round_to_odd:\n- overflow_norm = true;\n- inc = frac & frac_lsb ? 0 : round_mask;\n- break;\n- default:\n- g_assert_not_reached();\n- }\n-\n- exp += parm->exp_bias;\n- if (likely(exp > 0)) {\n- if (frac & round_mask) {\n- flags |= float_flag_inexact;\n- if (uadd64_overflow(frac, inc, &frac)) {\n- frac = (frac >> 1) | DECOMPOSED_IMPLICIT_BIT;\n- exp++;\n- }\n- }\n- frac >>= frac_shift;\n-\n- if (parm->arm_althp) {\n- /* ARM Alt HP eschews Inf and NaN for a wider exponent. */\n- if (unlikely(exp > exp_max)) {\n- /* Overflow. Return the maximum normal. */\n- flags = float_flag_invalid;\n- exp = exp_max;\n- frac = -1;\n- }\n- } else if (unlikely(exp >= exp_max)) {\n- flags |= float_flag_overflow | float_flag_inexact;\n- if (overflow_norm) {\n- exp = exp_max - 1;\n- frac = -1;\n- } else {\n- p.cls = float_class_inf;\n- goto do_inf;\n- }\n- }\n- } else if (s->flush_to_zero) {\n- flags |= float_flag_output_denormal;\n- p.cls = float_class_zero;\n- goto do_zero;\n- } else {\n- bool is_tiny = s->tininess_before_rounding || (exp < 0);\n-\n- if (!is_tiny) {\n- uint64_t discard;\n- is_tiny = !uadd64_overflow(frac, inc, &discard);\n- }\n-\n- shift64RightJamming(frac, 1 - exp, &frac);\n- if (frac & round_mask) {\n- /* Need to recompute round-to-even. */\n- switch (s->float_rounding_mode) {\n- case float_round_nearest_even:\n- inc = ((frac & roundeven_mask) != frac_lsbm1\n- ? frac_lsbm1 : 0);\n- break;\n- case float_round_to_odd:\n- inc = frac & frac_lsb ? 0 : round_mask;\n- break;\n- default:\n- break;\n- }\n- flags |= float_flag_inexact;\n- frac += inc;\n- }\n-\n- exp = (frac & DECOMPOSED_IMPLICIT_BIT ? 1 : 0);\n- frac >>= frac_shift;\n-\n- if (is_tiny && (flags & float_flag_inexact)) {\n- flags |= float_flag_underflow;\n- }\n- if (exp == 0 && frac == 0) {\n- p.cls = float_class_zero;\n- }\n- }\n- break;\n-\n- case float_class_zero:\n- do_zero:\n- exp = 0;\n- frac = 0;\n- break;\n-\n- case float_class_inf:\n- do_inf:\n- assert(!parm->arm_althp);\n- exp = exp_max;\n- frac = 0;\n- break;\n-\n- case float_class_qnan:\n- case float_class_snan:\n- assert(!parm->arm_althp);\n- exp = exp_max;\n- frac >>= parm->frac_shift;\n- break;\n-\n- default:\n- g_assert_not_reached();\n- }\n-\n- float_raise(flags, s);\n- p.exp = exp;\n- p.frac = frac;\n- return p;\n+ shift64RightJamming(a->frac, c, &a->frac);\n }\n \n+static void frac128_shrjam(FloatParts128 *a, int c)\n+{\n+ shift128RightJamming(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo);\n+}\n+\n+#define frac_shrjam(A, C) FRAC_GENERIC_64_128(shrjam, A)(A, C)\n \n #define partsN(NAME) parts64_##NAME\n #define FloatPartsN FloatParts64\n@@ -1044,7 +933,7 @@ static float16 float16a_round_pack_canonical(FloatParts64 *p,\n float_status *s,\n const FloatFmt *params)\n {\n- *p = round_canonical(*p, s, params);\n+ parts_uncanon(p, s, params);\n return float16_pack_raw(p);\n }\n \n@@ -1057,7 +946,7 @@ static float16 float16_round_pack_canonical(FloatParts64 *p,\n static bfloat16 bfloat16_round_pack_canonical(FloatParts64 *p,\n float_status *s)\n {\n- *p = round_canonical(*p, s, &bfloat16_params);\n+ parts_uncanon(p, s, &bfloat16_params);\n return bfloat16_pack_raw(p);\n }\n \n@@ -1071,7 +960,7 @@ static void float32_unpack_canonical(FloatParts64 *p, float32 f,\n static float32 float32_round_pack_canonical(FloatParts64 *p,\n float_status *s)\n {\n- *p = round_canonical(*p, s, &float32_params);\n+ parts_uncanon(p, s, &float32_params);\n return float32_pack_raw(p);\n }\n \n@@ -1085,7 +974,7 @@ static void float64_unpack_canonical(FloatParts64 *p, float64 f,\n static float64 float64_round_pack_canonical(FloatParts64 *p,\n float_status *s)\n {\n- *p = round_canonical(*p, s, &float64_params);\n+ parts_uncanon(p, s, &float64_params);\n return float64_pack_raw(p);\n }\n \ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex 25bf99bd0f..efdc724770 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -133,3 +133,151 @@ static void partsN(canonicalize)(FloatPartsN *p, float_status *status,\n ? float_class_snan : float_class_qnan);\n }\n }\n+\n+/*\n+ * Round and uncanonicalize a floating-point number by parts. There\n+ * are FRAC_SHIFT bits that may require rounding at the bottom of the\n+ * fraction; these bits will be removed. The exponent will be biased\n+ * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0].\n+ */\n+static void partsN(uncanon)(FloatPartsN *p, float_status *s,\n+ const FloatFmt *fmt)\n+{\n+ const int exp_max = fmt->exp_max;\n+ const int frac_shift = fmt->frac_shift;\n+ const uint64_t frac_lsb = fmt->frac_lsb;\n+ const uint64_t frac_lsbm1 = fmt->frac_lsbm1;\n+ const uint64_t round_mask = fmt->round_mask;\n+ const uint64_t roundeven_mask = fmt->roundeven_mask;\n+ uint64_t inc;\n+ bool overflow_norm;\n+ int exp, flags = 0;\n+\n+ if (unlikely(p->cls != float_class_normal)) {\n+ switch (p->cls) {\n+ case float_class_zero:\n+ p->exp = 0;\n+ frac_clear(p);\n+ return;\n+ case float_class_inf:\n+ g_assert(!fmt->arm_althp);\n+ p->exp = fmt->exp_max;\n+ frac_clear(p);\n+ return;\n+ case float_class_qnan:\n+ case float_class_snan:\n+ g_assert(!fmt->arm_althp);\n+ p->exp = fmt->exp_max;\n+ frac_shr(p, fmt->frac_shift);\n+ return;\n+ default:\n+ break;\n+ }\n+ g_assert_not_reached();\n+ }\n+\n+ switch (s->float_rounding_mode) {\n+ case float_round_nearest_even:\n+ overflow_norm = false;\n+ inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1 ? frac_lsbm1 : 0);\n+ break;\n+ case float_round_ties_away:\n+ overflow_norm = false;\n+ inc = frac_lsbm1;\n+ break;\n+ case float_round_to_zero:\n+ overflow_norm = true;\n+ inc = 0;\n+ break;\n+ case float_round_up:\n+ inc = p->sign ? 0 : round_mask;\n+ overflow_norm = p->sign;\n+ break;\n+ case float_round_down:\n+ inc = p->sign ? round_mask : 0;\n+ overflow_norm = !p->sign;\n+ break;\n+ case float_round_to_odd:\n+ overflow_norm = true;\n+ inc = p->frac_lo & frac_lsb ? 0 : round_mask;\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+\n+ exp = p->exp + fmt->exp_bias;\n+ if (likely(exp > 0)) {\n+ if (p->frac_lo & round_mask) {\n+ flags |= float_flag_inexact;\n+ if (frac_addi(p, p, inc)) {\n+ frac_shr(p, 1);\n+ p->frac_hi |= DECOMPOSED_IMPLICIT_BIT;\n+ exp++;\n+ }\n+ }\n+ frac_shr(p, frac_shift);\n+\n+ if (fmt->arm_althp) {\n+ /* ARM Alt HP eschews Inf and NaN for a wider exponent. */\n+ if (unlikely(exp > exp_max)) {\n+ /* Overflow. Return the maximum normal. */\n+ flags = float_flag_invalid;\n+ exp = exp_max;\n+ frac_allones(p);\n+ }\n+ } else if (unlikely(exp >= exp_max)) {\n+ flags |= float_flag_overflow | float_flag_inexact;\n+ if (overflow_norm) {\n+ exp = exp_max - 1;\n+ frac_allones(p);\n+ } else {\n+ p->cls = float_class_inf;\n+ exp = exp_max;\n+ frac_clear(p);\n+ }\n+ }\n+ } else if (s->flush_to_zero) {\n+ flags |= float_flag_output_denormal;\n+ p->cls = float_class_zero;\n+ exp = 0;\n+ frac_clear(p);\n+ } else {\n+ bool is_tiny = s->tininess_before_rounding || exp < 0;\n+\n+ if (!is_tiny) {\n+ FloatPartsN discard;\n+ is_tiny = !frac_addi(&discard, p, inc);\n+ }\n+\n+ frac_shrjam(p, 1 - exp);\n+\n+ if (p->frac_lo & round_mask) {\n+ /* Need to recompute round-to-even/round-to-odd. */\n+ switch (s->float_rounding_mode) {\n+ case float_round_nearest_even:\n+ inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1\n+ ? frac_lsbm1 : 0);\n+ break;\n+ case float_round_to_odd:\n+ inc = p->frac_lo & frac_lsb ? 0 : round_mask;\n+ break;\n+ default:\n+ break;\n+ }\n+ flags |= float_flag_inexact;\n+ frac_addi(p, p, inc);\n+ }\n+\n+ exp = (p->frac_hi & DECOMPOSED_IMPLICIT_BIT) != 0;\n+ frac_shr(p, frac_shift);\n+\n+ if (is_tiny && (flags & float_flag_inexact)) {\n+ flags |= float_flag_underflow;\n+ }\n+ if (exp == 0 && frac_eqz(p)) {\n+ p->cls = float_class_zero;\n+ }\n+ }\n+ p->exp = exp;\n+ float_raise(flags, s);\n+}\n", "prefixes": [ "32/72" ] }