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GET /api/patches/1475717/?format=api
{ "id": 1475717, "url": "http://patchwork.ozlabs.org/api/patches/1475717/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-18-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-18-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:47:07", "name": "[17/72] softfloat: Use pointers with parts_default_nan", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "018b1a129a003aade2c156eea573eb696a6f4bda", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-18-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475717/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475717/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pf1-x429.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "At the same time, rename to parts64_default_nan and define\na macro for parts_default_nan using QEMU_GENERIC.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat.c | 47 +++++++++++++++++++++++-----------\n fpu/softfloat-specialize.c.inc | 4 +--\n 2 files changed, 34 insertions(+), 17 deletions(-)", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 398a068b58..c7f95961cf 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -650,6 +650,8 @@ static inline float64 float64_pack_raw(FloatParts64 p)\n *----------------------------------------------------------------------------*/\n #include \"softfloat-specialize.c.inc\"\n \n+#define parts_default_nan parts64_default_nan\n+\n /* Canonicalize EXP and FRAC, setting CLS. */\n static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *parm,\n float_status *status)\n@@ -848,7 +850,8 @@ static FloatParts64 return_nan(FloatParts64 a, float_status *s)\n } else if (!s->default_nan_mode) {\n return a;\n }\n- return parts_default_nan(s);\n+ parts_default_nan(&a, s);\n+ return a;\n }\n \n static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status *s)\n@@ -858,7 +861,7 @@ static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status *s)\n }\n \n if (s->default_nan_mode) {\n- return parts_default_nan(s);\n+ parts_default_nan(&a, s);\n } else {\n if (pickNaN(a.cls, b.cls,\n a.frac > b.frac ||\n@@ -900,7 +903,8 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatParts64\n a = c;\n break;\n case 3:\n- return parts_default_nan(s);\n+ parts_default_nan(&a, s);\n+ break;\n default:\n g_assert_not_reached();\n }\n@@ -1011,7 +1015,7 @@ static FloatParts64 addsub_floats(FloatParts64 a, FloatParts64 b, bool subtract,\n if (a.cls == float_class_inf) {\n if (b.cls == float_class_inf) {\n float_raise(float_flag_invalid, s);\n- return parts_default_nan(s);\n+ parts_default_nan(&a, s);\n }\n return a;\n }\n@@ -1254,7 +1258,8 @@ static FloatParts64 mul_floats(FloatParts64 a, FloatParts64 b, float_status *s)\n if ((a.cls == float_class_inf && b.cls == float_class_zero) ||\n (a.cls == float_class_zero && b.cls == float_class_inf)) {\n float_raise(float_flag_invalid, s);\n- return parts_default_nan(s);\n+ parts_default_nan(&a, s);\n+ return a;\n }\n /* Multiply by 0 or Inf */\n if (a.cls == float_class_inf || a.cls == float_class_zero) {\n@@ -1372,7 +1377,8 @@ static FloatParts64 muladd_floats(FloatParts64 a, FloatParts64 b, FloatParts64 c\n \n if (inf_zero) {\n float_raise(float_flag_invalid, s);\n- return parts_default_nan(s);\n+ parts_default_nan(&a, s);\n+ return a;\n }\n \n if (flags & float_muladd_negate_c) {\n@@ -1396,11 +1402,11 @@ static FloatParts64 muladd_floats(FloatParts64 a, FloatParts64 b, FloatParts64 c\n if (c.cls == float_class_inf) {\n if (p_class == float_class_inf && p_sign != c.sign) {\n float_raise(float_flag_invalid, s);\n- return parts_default_nan(s);\n+ parts_default_nan(&c, s);\n } else {\n c.sign ^= sign_flip;\n- return c;\n }\n+ return c;\n }\n \n if (p_class == float_class_inf) {\n@@ -1764,7 +1770,8 @@ static FloatParts64 div_floats(FloatParts64 a, FloatParts64 b, float_status *s)\n &&\n (a.cls == float_class_inf || a.cls == float_class_zero)) {\n float_raise(float_flag_invalid, s);\n- return parts_default_nan(s);\n+ parts_default_nan(&a, s);\n+ return a;\n }\n /* Inf / x or 0 / x */\n if (a.cls == float_class_inf || a.cls == float_class_zero) {\n@@ -3438,7 +3445,8 @@ static FloatParts64 sqrt_float(FloatParts64 a, float_status *s, const FloatFmt *\n }\n if (a.sign) {\n float_raise(float_flag_invalid, s);\n- return parts_default_nan(s);\n+ parts_default_nan(&a, s);\n+ return a;\n }\n if (a.cls == float_class_inf) {\n return a; /* sqrt(+inf) = +inf */\n@@ -3573,30 +3581,37 @@ bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status)\n \n float16 float16_default_nan(float_status *status)\n {\n- FloatParts64 p = parts_default_nan(status);\n+ FloatParts64 p;\n+\n+ parts_default_nan(&p, status);\n p.frac >>= float16_params.frac_shift;\n return float16_pack_raw(p);\n }\n \n float32 float32_default_nan(float_status *status)\n {\n- FloatParts64 p = parts_default_nan(status);\n+ FloatParts64 p;\n+\n+ parts_default_nan(&p, status);\n p.frac >>= float32_params.frac_shift;\n return float32_pack_raw(p);\n }\n \n float64 float64_default_nan(float_status *status)\n {\n- FloatParts64 p = parts_default_nan(status);\n+ FloatParts64 p;\n+\n+ parts_default_nan(&p, status);\n p.frac >>= float64_params.frac_shift;\n return float64_pack_raw(p);\n }\n \n float128 float128_default_nan(float_status *status)\n {\n- FloatParts64 p = parts_default_nan(status);\n+ FloatParts64 p;\n float128 r;\n \n+ parts_default_nan(&p, status);\n /* Extrapolate from the choices made by parts_default_nan to fill\n * in the quad-floating format. If the low bit is set, assume we\n * want to set all non-snan bits.\n@@ -3611,7 +3626,9 @@ float128 float128_default_nan(float_status *status)\n \n bfloat16 bfloat16_default_nan(float_status *status)\n {\n- FloatParts64 p = parts_default_nan(status);\n+ FloatParts64 p;\n+\n+ parts_default_nan(&p, status);\n p.frac >>= bfloat16_params.frac_shift;\n return bfloat16_pack_raw(p);\n }\ndiff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc\nindex 52fc76d800..085ddea62b 100644\n--- a/fpu/softfloat-specialize.c.inc\n+++ b/fpu/softfloat-specialize.c.inc\n@@ -129,7 +129,7 @@ static bool parts_is_snan_frac(uint64_t frac, float_status *status)\n | The pattern for a default generated deconstructed floating-point NaN.\n *----------------------------------------------------------------------------*/\n \n-static FloatParts64 parts_default_nan(float_status *status)\n+static void parts64_default_nan(FloatParts64 *p, float_status *status)\n {\n bool sign = 0;\n uint64_t frac;\n@@ -164,7 +164,7 @@ static FloatParts64 parts_default_nan(float_status *status)\n }\n #endif\n \n- return (FloatParts64) {\n+ *p = (FloatParts64) {\n .cls = float_class_qnan,\n .sign = sign,\n .exp = INT_MAX,\n", "prefixes": [ "17/72" ] }