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GET /api/patches/1475711/?format=api
{ "id": 1475711, "url": "http://patchwork.ozlabs.org/api/patches/1475711/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-6-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-6-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:46:55", "name": "[05/72] tests/fp: add quad support to the benchmark utility", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8287ce4871cf0bfed74196ac61857d286a364f9b", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-6-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475711/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475711/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=g4+K3m2LZd6+POKVjFNctLT1gVSINE33R4eVJ09cL3Y=;\n b=oFLk7Gvgilmo6U1K85xJu+ieCcS4ptzSTsbs3GBYzV9lq3l9t2BKbhNBlxrmU3K+6h\n MykhfZBWjrGo0Uolxx3TDX1zM9XbQTu/AEZ0CleUUAFoyv84OOsNlQqRFj4dl6Km1C7E\n Nw8vGNeCzyVz+l23QEXNyCNI+CEHLpmKMdyfv9Gy6w9oO/hWFZPbPAkEjBmJVhmkBiND\n JLFO8oW1Az6Q0KvtrGXMx+zqucKxLnbMn9hu2dFLtpjr0cFxzKCdd3hTuriHStFgbzxc\n eLwxBm41820CGTObJbw9OLqEAjv2uR0tTMXjlCtq6vJ0xhfTMIopDnEDeTh/9vujitFG\n FT0Q==", "X-Gm-Message-State": "AOAM530kmG4xeOhQW57x6R8KvICN4UPEfqwENbhGf7p0hV6r/kBIEqci\n w1Jm4pSJn2kQhlbb46k/+ZwbhE7DEY85Nw==", "X-Google-Smtp-Source": "\n ABdhPJwsxCmKxyit7vaHjTKILNlH2kOhIrpgVM35bdwqEMbQUq9LI/EchzCT0IjYfS8mDbeh5bKsvQ==", "X-Received": "by 2002:a05:6a00:170c:b029:225:8851:5b3c with SMTP id\n h12-20020a056a00170cb029022588515b3cmr13295117pfc.0.1620438487242;\n Fri, 07 May 2021 18:48:07 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PATCH 05/72] tests/fp: add quad support to the benchmark utility", "Date": "Fri, 7 May 2021 18:46:55 -0700", "Message-Id": "<20210508014802.892561-6-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210508014802.892561-1-richard.henderson@linaro.org>", "References": "<20210508014802.892561-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::431;\n envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Alex Bennée <alex.bennee@linaro.org>\n\nCurrently this only support softfloat calculations because working out\nif the hardware supports 128 bit floats needs configure magic. The 3\nop muladd operation is currently unimplemented so commented out for\nnow.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-Id: <20201020163738.27700-8-alex.bennee@linaro.org>\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n tests/fp/fp-bench.c | 88 ++++++++++++++++++++++++++++++++++++++++++---\n 1 file changed, 83 insertions(+), 5 deletions(-)", "diff": "diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c\nindex 4ba5e1d2d4..d319993280 100644\n--- a/tests/fp/fp-bench.c\n+++ b/tests/fp/fp-bench.c\n@@ -14,6 +14,7 @@\n #include <math.h>\n #include <fenv.h>\n #include \"qemu/timer.h\"\n+#include \"qemu/int128.h\"\n #include \"fpu/softfloat.h\"\n \n /* amortize the computation of random inputs */\n@@ -50,8 +51,10 @@ static const char * const op_names[] = {\n enum precision {\n PREC_SINGLE,\n PREC_DOUBLE,\n+ PREC_QUAD,\n PREC_FLOAT32,\n PREC_FLOAT64,\n+ PREC_FLOAT128,\n PREC_MAX_NR,\n };\n \n@@ -89,6 +92,7 @@ union fp {\n double d;\n float32 f32;\n float64 f64;\n+ float128 f128;\n uint64_t u64;\n };\n \n@@ -113,6 +117,10 @@ struct op_desc {\n static uint64_t random_ops[MAX_OPERANDS] = {\n SEED_A, SEED_B, SEED_C,\n };\n+\n+static float128 random_quad_ops[MAX_OPERANDS] = {\n+ {SEED_A, SEED_B}, {SEED_B, SEED_C}, {SEED_C, SEED_A},\n+};\n static float_status soft_status;\n static enum precision precision;\n static enum op operation;\n@@ -141,25 +149,45 @@ static void update_random_ops(int n_ops, enum precision prec)\n int i;\n \n for (i = 0; i < n_ops; i++) {\n- uint64_t r = random_ops[i];\n \n switch (prec) {\n case PREC_SINGLE:\n case PREC_FLOAT32:\n+ {\n+ uint64_t r = random_ops[i];\n do {\n r = xorshift64star(r);\n } while (!float32_is_normal(r));\n+ random_ops[i] = r;\n break;\n+ }\n case PREC_DOUBLE:\n case PREC_FLOAT64:\n+ {\n+ uint64_t r = random_ops[i];\n do {\n r = xorshift64star(r);\n } while (!float64_is_normal(r));\n+ random_ops[i] = r;\n break;\n+ }\n+ case PREC_QUAD:\n+ case PREC_FLOAT128:\n+ {\n+ float128 r = random_quad_ops[i];\n+ uint64_t hi = r.high;\n+ uint64_t lo = r.low;\n+ do {\n+ hi = xorshift64star(hi);\n+ lo = xorshift64star(lo);\n+ r = make_float128(hi, lo);\n+ } while (!float128_is_normal(r));\n+ random_quad_ops[i] = r;\n+ break;\n+ }\n default:\n g_assert_not_reached();\n }\n- random_ops[i] = r;\n }\n }\n \n@@ -184,6 +212,13 @@ static void fill_random(union fp *ops, int n_ops, enum precision prec,\n ops[i].f64 = float64_chs(ops[i].f64);\n }\n break;\n+ case PREC_QUAD:\n+ case PREC_FLOAT128:\n+ ops[i].f128 = random_quad_ops[i];\n+ if (no_neg && float128_is_neg(ops[i].f128)) {\n+ ops[i].f128 = float128_chs(ops[i].f128);\n+ }\n+ break;\n default:\n g_assert_not_reached();\n }\n@@ -345,6 +380,41 @@ static void bench(enum precision prec, enum op op, int n_ops, bool no_neg)\n }\n }\n break;\n+ case PREC_FLOAT128:\n+ fill_random(ops, n_ops, prec, no_neg);\n+ t0 = get_clock();\n+ for (i = 0; i < OPS_PER_ITER; i++) {\n+ float128 a = ops[0].f128;\n+ float128 b = ops[1].f128;\n+ /* float128 c = ops[2].f128; */\n+\n+ switch (op) {\n+ case OP_ADD:\n+ res.f128 = float128_add(a, b, &soft_status);\n+ break;\n+ case OP_SUB:\n+ res.f128 = float128_sub(a, b, &soft_status);\n+ break;\n+ case OP_MUL:\n+ res.f128 = float128_mul(a, b, &soft_status);\n+ break;\n+ case OP_DIV:\n+ res.f128 = float128_div(a, b, &soft_status);\n+ break;\n+ /* case OP_FMA: */\n+ /* res.f128 = float128_muladd(a, b, c, 0, &soft_status); */\n+ /* break; */\n+ case OP_SQRT:\n+ res.f128 = float128_sqrt(a, &soft_status);\n+ break;\n+ case OP_CMP:\n+ res.u64 = float128_compare_quiet(a, b, &soft_status);\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+ }\n+ break;\n default:\n g_assert_not_reached();\n }\n@@ -369,7 +439,8 @@ static void bench(enum precision prec, enum op op, int n_ops, bool no_neg)\n GEN_BENCH(bench_ ## opname ## _float, float, PREC_SINGLE, op, n_ops) \\\n GEN_BENCH(bench_ ## opname ## _double, double, PREC_DOUBLE, op, n_ops) \\\n GEN_BENCH(bench_ ## opname ## _float32, float32, PREC_FLOAT32, op, n_ops) \\\n- GEN_BENCH(bench_ ## opname ## _float64, float64, PREC_FLOAT64, op, n_ops)\n+ GEN_BENCH(bench_ ## opname ## _float64, float64, PREC_FLOAT64, op, n_ops) \\\n+ GEN_BENCH(bench_ ## opname ## _float128, float128, PREC_FLOAT128, op, n_ops)\n \n GEN_BENCH_ALL_TYPES(add, OP_ADD, 2)\n GEN_BENCH_ALL_TYPES(sub, OP_SUB, 2)\n@@ -383,7 +454,8 @@ GEN_BENCH_ALL_TYPES(cmp, OP_CMP, 2)\n GEN_BENCH_NO_NEG(bench_ ## name ## _float, float, PREC_SINGLE, op, n) \\\n GEN_BENCH_NO_NEG(bench_ ## name ## _double, double, PREC_DOUBLE, op, n) \\\n GEN_BENCH_NO_NEG(bench_ ## name ## _float32, float32, PREC_FLOAT32, op, n) \\\n- GEN_BENCH_NO_NEG(bench_ ## name ## _float64, float64, PREC_FLOAT64, op, n)\n+ GEN_BENCH_NO_NEG(bench_ ## name ## _float64, float64, PREC_FLOAT64, op, n) \\\n+ GEN_BENCH_NO_NEG(bench_ ## name ## _float128, float128, PREC_FLOAT128, op, n)\n \n GEN_BENCH_ALL_TYPES_NO_NEG(sqrt, OP_SQRT, 1)\n #undef GEN_BENCH_ALL_TYPES_NO_NEG\n@@ -397,6 +469,7 @@ GEN_BENCH_ALL_TYPES_NO_NEG(sqrt, OP_SQRT, 1)\n [PREC_DOUBLE] = bench_ ## opname ## _double, \\\n [PREC_FLOAT32] = bench_ ## opname ## _float32, \\\n [PREC_FLOAT64] = bench_ ## opname ## _float64, \\\n+ [PREC_FLOAT128] = bench_ ## opname ## _float128, \\\n }\n \n static const bench_func_t bench_funcs[OP_MAX_NR][PREC_MAX_NR] = {\n@@ -445,7 +518,7 @@ static void usage_complete(int argc, char *argv[])\n fprintf(stderr, \" -h = show this help message.\\n\");\n fprintf(stderr, \" -o = floating point operation (%s). Default: %s\\n\",\n op_list, op_names[0]);\n- fprintf(stderr, \" -p = floating point precision (single, double). \"\n+ fprintf(stderr, \" -p = floating point precision (single, double, quad[soft only]). \"\n \"Default: single\\n\");\n fprintf(stderr, \" -r = rounding mode (even, zero, down, up, tieaway). \"\n \"Default: even\\n\");\n@@ -565,6 +638,8 @@ static void parse_args(int argc, char *argv[])\n precision = PREC_SINGLE;\n } else if (!strcmp(optarg, \"double\")) {\n precision = PREC_DOUBLE;\n+ } else if (!strcmp(optarg, \"quad\")) {\n+ precision = PREC_QUAD;\n } else {\n fprintf(stderr, \"Unsupported precision '%s'\\n\", optarg);\n exit(EXIT_FAILURE);\n@@ -608,6 +683,9 @@ static void parse_args(int argc, char *argv[])\n case PREC_DOUBLE:\n precision = PREC_FLOAT64;\n break;\n+ case PREC_QUAD:\n+ precision = PREC_FLOAT128;\n+ break;\n default:\n g_assert_not_reached();\n }\n", "prefixes": [ "05/72" ] }