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GET /api/patches/1475703/?format=api
{ "id": 1475703, "url": "http://patchwork.ozlabs.org/api/patches/1475703/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-9-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210508014802.892561-9-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2021-05-08T01:46:58", "name": "[08/72] softfloat: Use float_raise in more places", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bf6d163fc4ac2cc093dd74d72d45294492bc4b6a", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210508014802.892561-9-richard.henderson@linaro.org/mbox/", "series": [ { "id": 242770, "url": "http://patchwork.ozlabs.org/api/series/242770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=242770", "date": "2021-05-08T01:46:53", "name": "Convert floatx80 and float128 to FloatParts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/242770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1475703/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1475703/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=SE0+KI5V;\n\tdkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4FcVfk6vQpz9sV5\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 8 May 2021 11:51:42 +1000 (AEST)", "from localhost ([::1]:51732 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1lfC84-0001PO-Sf\n\tfor incoming@patchwork.ozlabs.org; Fri, 07 May 2021 21:51:40 -0400", "from eggs.gnu.org ([2001:470:142:3::10]:40554)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1lfC4k-00047b-DN\n for qemu-devel@nongnu.org; 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helo=mail-pg1-x533.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, david@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "We have been somewhat inconsistent about when to use\nfloat_raise and when to or in the bit by hand.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat.c | 87 +++++++++++++++++++++++++------------------------\n 1 file changed, 44 insertions(+), 43 deletions(-)", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex cd777743f1..93fe785809 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -132,7 +132,7 @@ this code that are retained.\n if (unlikely(soft_t ## _is_denormal(*a))) { \\\n *a = soft_t ## _set_sign(soft_t ## _zero, \\\n soft_t ## _is_neg(*a)); \\\n- s->float_exception_flags |= float_flag_input_denormal; \\\n+ float_raise(float_flag_input_denormal, s); \\\n } \\\n }\n \n@@ -360,7 +360,7 @@ float32_gen2(float32 xa, float32 xb, float_status *s,\n \n ur.h = hard(ua.h, ub.h);\n if (unlikely(f32_is_inf(ur))) {\n- s->float_exception_flags |= float_flag_overflow;\n+ float_raise(float_flag_overflow, s);\n } else if (unlikely(fabsf(ur.h) <= FLT_MIN) && post(ua, ub)) {\n goto soft;\n }\n@@ -391,7 +391,7 @@ float64_gen2(float64 xa, float64 xb, float_status *s,\n \n ur.h = hard(ua.h, ub.h);\n if (unlikely(f64_is_inf(ur))) {\n- s->float_exception_flags |= float_flag_overflow;\n+ float_raise(float_flag_overflow, s);\n } else if (unlikely(fabs(ur.h) <= DBL_MIN) && post(ua, ub)) {\n goto soft;\n }\n@@ -880,7 +880,7 @@ static FloatParts return_nan(FloatParts a, float_status *s)\n {\n switch (a.cls) {\n case float_class_snan:\n- s->float_exception_flags |= float_flag_invalid;\n+ float_raise(float_flag_invalid, s);\n a = parts_silence_nan(a, s);\n /* fall through */\n case float_class_qnan:\n@@ -898,7 +898,7 @@ static FloatParts return_nan(FloatParts a, float_status *s)\n static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s)\n {\n if (is_snan(a.cls) || is_snan(b.cls)) {\n- s->float_exception_flags |= float_flag_invalid;\n+ float_raise(float_flag_invalid, s);\n }\n \n if (s->default_nan_mode) {\n@@ -922,7 +922,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c,\n int which;\n \n if (is_snan(a.cls) || is_snan(b.cls) || is_snan(c.cls)) {\n- s->float_exception_flags |= float_flag_invalid;\n+ float_raise(float_flag_invalid, s);\n }\n \n which = pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s);\n@@ -1241,7 +1241,7 @@ static FloatParts mul_floats(FloatParts a, FloatParts b, float_status *s)\n /* Inf * Zero == NaN */\n if ((a.cls == float_class_inf && b.cls == float_class_zero) ||\n (a.cls == float_class_zero && b.cls == float_class_inf)) {\n- s->float_exception_flags |= float_flag_invalid;\n+ float_raise(float_flag_invalid, s);\n return parts_default_nan(s);\n }\n /* Multiply by 0 or Inf */\n@@ -1356,6 +1356,7 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c,\n }\n \n if (inf_zero) {\n+ float_raise(float_flag_invalid, s);\n s->float_exception_flags |= float_flag_invalid;\n return parts_default_nan(s);\n }\n@@ -1380,7 +1381,7 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c,\n \n if (c.cls == float_class_inf) {\n if (p_class == float_class_inf && p_sign != c.sign) {\n- s->float_exception_flags |= float_flag_invalid;\n+ float_raise(float_flag_invalid, s);\n return parts_default_nan(s);\n } else {\n a.cls = float_class_inf;\n@@ -1598,7 +1599,7 @@ float32_muladd(float32 xa, float32 xb, float32 xc, int flags, float_status *s)\n ur.h = fmaf(ua.h, ub.h, uc.h);\n \n if (unlikely(f32_is_inf(ur))) {\n- s->float_exception_flags |= float_flag_overflow;\n+ float_raise(float_flag_overflow, s);\n } else if (unlikely(fabsf(ur.h) <= FLT_MIN)) {\n ua = ua_orig;\n uc = uc_orig;\n@@ -1669,7 +1670,7 @@ float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s)\n ur.h = fma(ua.h, ub.h, uc.h);\n \n if (unlikely(f64_is_inf(ur))) {\n- s->float_exception_flags |= float_flag_overflow;\n+ float_raise(float_flag_overflow, s);\n } else if (unlikely(fabs(ur.h) <= FLT_MIN)) {\n ua = ua_orig;\n uc = uc_orig;\n@@ -1749,7 +1750,7 @@ static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s)\n if (a.cls == b.cls\n &&\n (a.cls == float_class_inf || a.cls == float_class_zero)) {\n- s->float_exception_flags |= float_flag_invalid;\n+ float_raise(float_flag_invalid, s);\n return parts_default_nan(s);\n }\n /* Inf / x or 0 / x */\n@@ -1759,7 +1760,7 @@ static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s)\n }\n /* Div 0 => Inf */\n if (b.cls == float_class_zero) {\n- s->float_exception_flags |= float_flag_divbyzero;\n+ float_raise(float_flag_divbyzero, s);\n a.cls = float_class_inf;\n a.sign = sign;\n return a;\n@@ -1895,7 +1896,7 @@ static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf,\n /* There is no NaN in the destination format. Raise Invalid\n * and return a zero with the sign of the input NaN.\n */\n- s->float_exception_flags |= float_flag_invalid;\n+ float_raise(float_flag_invalid, s);\n a.cls = float_class_zero;\n a.frac = 0;\n a.exp = 0;\n@@ -1905,7 +1906,7 @@ static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf,\n /* There is no Inf in the destination format. Raise Invalid\n * and return the maximum normal with the correct sign.\n */\n- s->float_exception_flags |= float_flag_invalid;\n+ float_raise(float_flag_invalid, s);\n a.cls = float_class_normal;\n a.exp = dstf->exp_max;\n a.frac = ((1ull << dstf->frac_size) - 1) << dstf->frac_shift;\n@@ -1916,7 +1917,7 @@ static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf,\n }\n } else if (is_nan(a.cls)) {\n if (is_snan(a.cls)) {\n- s->float_exception_flags |= float_flag_invalid;\n+ float_raise(float_flag_invalid, s);\n a = parts_silence_nan(a, s);\n }\n if (s->default_nan_mode) {\n@@ -2048,7 +2049,7 @@ static FloatParts round_to_int(FloatParts a, FloatRoundMode rmode,\n if (a.exp < 0) {\n bool one;\n /* all fractional */\n- s->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, s);\n switch (rmode) {\n case float_round_nearest_even:\n one = a.exp == -1 && a.frac > DECOMPOSED_IMPLICIT_BIT;\n@@ -2109,7 +2110,7 @@ static FloatParts round_to_int(FloatParts a, FloatRoundMode rmode,\n }\n \n if (a.frac & rnd_mask) {\n- s->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, s);\n if (uadd64_overflow(a.frac, inc, &a.frac)) {\n a.frac >>= 1;\n a.frac |= DECOMPOSED_IMPLICIT_BIT;\n@@ -3188,7 +3189,7 @@ static FloatRelation compare_floats(FloatParts a, FloatParts b, bool is_quiet,\n if (!is_quiet ||\n a.cls == float_class_snan ||\n b.cls == float_class_snan) {\n- s->float_exception_flags |= float_flag_invalid;\n+ float_raise(float_flag_invalid, s);\n }\n return float_relation_unordered;\n }\n@@ -3429,7 +3430,7 @@ static FloatParts sqrt_float(FloatParts a, float_status *s, const FloatFmt *p)\n return a; /* sqrt(+-0) = +-0 */\n }\n if (a.sign) {\n- s->float_exception_flags |= float_flag_invalid;\n+ float_raise(float_flag_invalid, s);\n return parts_default_nan(s);\n }\n if (a.cls == float_class_inf) {\n@@ -3760,7 +3761,7 @@ static int32_t roundAndPackInt32(bool zSign, uint64_t absZ,\n return zSign ? INT32_MIN : INT32_MAX;\n }\n if (roundBits) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n return z;\n \n@@ -3822,7 +3823,7 @@ static int64_t roundAndPackInt64(bool zSign, uint64_t absZ0, uint64_t absZ1,\n return zSign ? INT64_MIN : INT64_MAX;\n }\n if (absZ1) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n return z;\n \n@@ -3883,7 +3884,7 @@ static int64_t roundAndPackUint64(bool zSign, uint64_t absZ0,\n }\n \n if (absZ1) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n return absZ0;\n }\n@@ -3994,7 +3995,7 @@ static float32 roundAndPackFloat32(bool zSign, int zExp, uint32_t zSig,\n }\n }\n if (roundBits) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n zSig = ( zSig + roundIncrement )>>7;\n if (!(roundBits ^ 0x40) && roundNearestEven) {\n@@ -4150,7 +4151,7 @@ static float64 roundAndPackFloat64(bool zSign, int zExp, uint64_t zSig,\n }\n }\n if (roundBits) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n zSig = ( zSig + roundIncrement )>>10;\n if (!(roundBits ^ 0x200) && roundNearestEven) {\n@@ -4284,7 +4285,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign,\n float_raise(float_flag_underflow, status);\n }\n if (roundBits) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n zSig0 += roundIncrement;\n if ( (int64_t) zSig0 < 0 ) zExp = 1;\n@@ -4297,7 +4298,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign,\n }\n }\n if (roundBits) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n zSig0 += roundIncrement;\n if ( zSig0 < roundIncrement ) {\n@@ -4360,7 +4361,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign,\n float_raise(float_flag_underflow, status);\n }\n if (zSig1) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n switch (roundingMode) {\n case float_round_nearest_even:\n@@ -4390,7 +4391,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign,\n }\n }\n if (zSig1) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n if ( increment ) {\n ++zSig0;\n@@ -4667,7 +4668,7 @@ static float128 roundAndPackFloat128(bool zSign, int32_t zExp,\n }\n }\n if (zSig2) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n if ( increment ) {\n add128( zSig0, zSig1, 0, 1, &zSig0, &zSig1 );\n@@ -5405,7 +5406,7 @@ int32_t floatx80_to_int32_round_to_zero(floatx80 a, float_status *status)\n }\n else if ( aExp < 0x3FFF ) {\n if (aExp || aSig) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n return 0;\n }\n@@ -5420,7 +5421,7 @@ int32_t floatx80_to_int32_round_to_zero(floatx80 a, float_status *status)\n return aSign ? (int32_t) 0x80000000 : 0x7FFFFFFF;\n }\n if ( ( aSig<<shiftCount ) != savedASig ) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n return z;\n \n@@ -5504,13 +5505,13 @@ int64_t floatx80_to_int64_round_to_zero(floatx80 a, float_status *status)\n }\n else if ( aExp < 0x3FFF ) {\n if (aExp | aSig) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n return 0;\n }\n z = aSig>>( - shiftCount );\n if ( (uint64_t) ( aSig<<( shiftCount & 63 ) ) ) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n if ( aSign ) z = - z;\n return z;\n@@ -5661,7 +5662,7 @@ floatx80 floatx80_round_to_int(floatx80 a, float_status *status)\n && ( (uint64_t) ( extractFloatx80Frac( a ) ) == 0 ) ) {\n return a;\n }\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n aSign = extractFloatx80Sign( a );\n switch (status->float_rounding_mode) {\n case float_round_nearest_even:\n@@ -5728,7 +5729,7 @@ floatx80 floatx80_round_to_int(floatx80 a, float_status *status)\n z.low = UINT64_C(0x8000000000000000);\n }\n if (z.low != a.low) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n return z;\n \n@@ -6364,7 +6365,7 @@ int32_t float128_to_int32_round_to_zero(float128 a, float_status *status)\n }\n else if ( aExp < 0x3FFF ) {\n if (aExp || aSig0) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n return 0;\n }\n@@ -6380,7 +6381,7 @@ int32_t float128_to_int32_round_to_zero(float128 a, float_status *status)\n return aSign ? INT32_MIN : INT32_MAX;\n }\n if ( ( aSig0<<shiftCount ) != savedASig ) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n return z;\n \n@@ -6458,7 +6459,7 @@ int64_t float128_to_int64_round_to_zero(float128 a, float_status *status)\n if ( ( a.high == UINT64_C(0xC03E000000000000) )\n && ( aSig1 < UINT64_C(0x0002000000000000) ) ) {\n if (aSig1) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n }\n else {\n@@ -6471,20 +6472,20 @@ int64_t float128_to_int64_round_to_zero(float128 a, float_status *status)\n }\n z = ( aSig0<<shiftCount ) | ( aSig1>>( ( - shiftCount ) & 63 ) );\n if ( (uint64_t) ( aSig1<<shiftCount ) ) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n }\n else {\n if ( aExp < 0x3FFF ) {\n if ( aExp | aSig0 | aSig1 ) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n return 0;\n }\n z = aSig0>>( - shiftCount );\n if ( aSig1\n || ( shiftCount && (uint64_t) ( aSig0<<( shiftCount & 63 ) ) ) ) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n }\n if ( aSign ) z = - z;\n@@ -6793,7 +6794,7 @@ float128 float128_round_to_int(float128 a, float_status *status)\n else {\n if ( aExp < 0x3FFF ) {\n if ( ( ( (uint64_t) ( a.high<<1 ) ) | a.low ) == 0 ) return a;\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n aSign = extractFloat128Sign( a );\n switch (status->float_rounding_mode) {\n case float_round_nearest_even:\n@@ -6867,7 +6868,7 @@ float128 float128_round_to_int(float128 a, float_status *status)\n z.high &= ~ roundBitsMask;\n }\n if ( ( z.low != a.low ) || ( z.high != a.high ) ) {\n- status->float_exception_flags |= float_flag_inexact;\n+ float_raise(float_flag_inexact, status);\n }\n return z;\n \n", "prefixes": [ "08/72" ] }