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GET /api/patches/1469664/?format=api
{ "id": 1469664, "url": "http://patchwork.ozlabs.org/api/patches/1469664/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20210423162748.1952-4-d-gerlach@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210423162748.1952-4-d-gerlach@ti.com>", "list_archive_url": null, "date": "2021-04-23T16:27:34", "name": "[03/17] arm: mach-k3: am642: Unlock all applicable control MMR registers", "commit_ref": "b4a8c3b242aced38ee7aa1cce664f0108fc3242c", "pull_url": null, "state": "accepted", "archived": false, "hash": "d154013231118fac7d5f33bb3f6b6faa0aa3d0bd", "submitter": { "id": 61863, "url": "http://patchwork.ozlabs.org/api/people/61863/?format=api", "name": "Dave Gerlach", "email": "d-gerlach@ti.com" }, "delegate": { "id": 19261, "url": "http://patchwork.ozlabs.org/api/users/19261/?format=api", "username": "lokeshvutla", "first_name": "Lokesh", "last_name": "Vutla", "email": "lokeshvutla@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20210423162748.1952-4-d-gerlach@ti.com/mbox/", "series": [ { "id": 240546, "url": "http://patchwork.ozlabs.org/api/series/240546/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=240546", "date": "2021-04-23T16:27:34", "name": "arm: mach-k3: Initial Support for Texas Instruments AM642 Platform", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/240546/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1469664/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1469664/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Sat, 24 Apr 2021 02:28:13 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id AEAA682CDB;\n\tFri, 23 Apr 2021 18:27:59 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id A4BCD82CDE; Fri, 23 Apr 2021 18:27:56 +0200 (CEST)", "from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id A386782CC8\n for <u-boot@lists.denx.de>; Fri, 23 Apr 2021 18:27:50 +0200 (CEST)", "from lelv0265.itg.ti.com ([10.180.67.224])\n by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 13NGRmVn050059;\n Fri, 23 Apr 2021 11:27:48 -0500", "from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30])\n by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 13NGRmJo117972\n (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL);\n Fri, 23 Apr 2021 11:27:48 -0500", "from DLEE114.ent.ti.com (157.170.170.25) by DLEE100.ent.ti.com\n (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 23\n Apr 2021 11:27:48 -0500", "from fllv0039.itg.ti.com (10.64.41.19) by DLEE114.ent.ti.com\n (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via\n Frontend Transport; Fri, 23 Apr 2021 11:27:48 -0500", "from localhost (ileax41-snat.itg.ti.com [10.172.224.153])\n by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 13NGRmPg086148;\n Fri, 23 Apr 2021 11:27:48 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H4,\n RCVD_IN_MSPIKE_WL,SPF_HELO_NONE autolearn=ham autolearn_force=no\n version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com;\n s=ti-com-17Q1; t=1619195268;\n bh=RSz4IVr6qFkffoM/a27exVjjS9reP3ypwfAHo6NYl4U=;\n h=From:To:CC:Subject:Date:In-Reply-To:References;\n b=rf1O7n1X/KoK+YtSav0yI6LAGLx8n7mL8bTS4K8vrt7OeOmXDDSwytgn4HYmLIMXg\n hEX3F4ugWh1O9dls6V14GD2HhF24jHQ+EfGYJjKBZMssnGvVC3FFqhZr97JwJk9/46\n gvg7mmHBW0dBKz5W458D9VOAaAZCWzXQEodFuzqg=", "From": "Dave Gerlach <d-gerlach@ti.com>", "To": "<u-boot@lists.denx.de>, Lokesh Vutla <lokeshvutla@ti.com>, Tom Rini\n <trini@konsulko.com>", "CC": "Praneeth Bajjuri <praneeth@ti.com>, Dave Gerlach <d-gerlach@ti.com>,\n Keerthy J <j-keerthy@ti.com>, Suman Anna <s-anna@ti.com>", "Subject": "[PATCH 03/17] arm: mach-k3: am642: Unlock all applicable control MMR\n registers", "Date": "Fri, 23 Apr 2021 11:27:34 -0500", "Message-ID": "<20210423162748.1952-4-d-gerlach@ti.com>", "X-Mailer": "git-send-email 2.28.0", "In-Reply-To": "<20210423162748.1952-1-d-gerlach@ti.com>", "References": "<20210423162748.1952-1-d-gerlach@ti.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.4 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "To access various control MMR functionality the registers need to\nbe unlocked. Do that for all control MMR regions in the MAIN domain.\n\nSigned-off-by: Dave Gerlach <d-gerlach@ti.com>\n---\n arch/arm/mach-k3/am642_init.c | 16 ++++++++++++++++\n arch/arm/mach-k3/include/mach/am64_hardware.h | 10 ++++++----\n 2 files changed, 22 insertions(+), 4 deletions(-)", "diff": "diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c\nindex e63275ccc68f..5ab2904c5e0c 100644\n--- a/arch/arm/mach-k3/am642_init.c\n+++ b/arch/arm/mach-k3/am642_init.c\n@@ -15,12 +15,28 @@\n \n #if defined(CONFIG_SPL_BUILD)\n \n+static void ctrl_mmr_unlock(void)\n+{\n+\t/* Unlock all PADCFG_MMR1 module registers */\n+\tmmr_unlock(PADCFG_MMR1_BASE, 1);\n+\n+\t/* Unlock all CTRL_MMR0 module registers */\n+\tmmr_unlock(CTRL_MMR0_BASE, 0);\n+\tmmr_unlock(CTRL_MMR0_BASE, 1);\n+\tmmr_unlock(CTRL_MMR0_BASE, 2);\n+\tmmr_unlock(CTRL_MMR0_BASE, 3);\n+\tmmr_unlock(CTRL_MMR0_BASE, 5);\n+\tmmr_unlock(CTRL_MMR0_BASE, 6);\n+}\n+\n void board_init_f(ulong dummy)\n {\n #if defined(CONFIG_CPU_V7R)\n \tsetup_k3_mpu_regions();\n #endif\n \n+\tctrl_mmr_unlock();\n+\n \t/* Init DM early */\n \tspl_early_init();\n \ndiff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h\nindex 8136585bde6f..ec5387025b98 100644\n--- a/arch/arm/mach-k3/include/mach/am64_hardware.h\n+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h\n@@ -12,6 +12,8 @@\n #define CTRL_MMR0_BASE\t\t\t\t\t0x43000000\n #define CTRLMMR_MAIN_DEVSTAT\t\t\t\t(CTRL_MMR0_BASE + 0x30)\n \n+#define PADCFG_MMR1_BASE\t\t\t\t0xf0000\n+\n #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK\t\t0x00000078\n #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT\t\t3\n \n@@ -29,14 +31,14 @@\n #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK\t\t0x04\n \n /*\n- * The CTRL_MMR memory space is divided into several equally-spaced\n- * partitions, so defining the partition size allows us to determine\n- * register addresses common to those partitions.\n+ * The CTRL_MMR and PADCFG_MMR memory space is divided into several\n+ * equally-spaced partitions, so defining the partition size allows us to\n+ * determine register addresses common to those partitions.\n */\n #define CTRL_MMR0_PARTITION_SIZE\t\t\t0x4000\n \n /*\n- * CTRL_MMR lock/kick-mechanism shared register definitions.\n+ * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions.\n */\n #define CTRLMMR_LOCK_KICK0\t\t\t\t0x01008\n #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL\t\t\t0x68ef3490\n", "prefixes": [ "03/17" ] }