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GET /api/patches/1463185/?format=api
{ "id": 1463185, "url": "http://patchwork.ozlabs.org/api/patches/1463185/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20210407064335.525254-1-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210407064335.525254-1-sr@denx.de>", "list_archive_url": null, "date": "2021-04-07T06:43:35", "name": "[v2,49/50] mips: octeon: Add Octeon PCIe host controller driver", "commit_ref": null, "pull_url": null, "state": "awaiting-upstream", "archived": false, "hash": "52d12edf14fdf478acd6f9de25f049ae2e4524c6", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20210407064335.525254-1-sr@denx.de/mbox/", "series": [ { "id": 237786, "url": "http://patchwork.ozlabs.org/api/series/237786/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=237786", "date": "2021-04-07T06:43:35", "name": null, "version": 2, "mbox": "http://patchwork.ozlabs.org/series/237786/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1463185/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1463185/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=PXmuTAgz;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4FFZc75f87z9sWY\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 7 Apr 2021 16:43:51 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 3E79A8039D;\n\tWed, 7 Apr 2021 08:43:48 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 9C0CC80433; Wed, 7 Apr 2021 08:43:46 +0200 (CEST)", "from mout-u-107.mailbox.org (mout-u-107.mailbox.org\n [IPv6:2001:67c:2050:1::465:107])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 6766E801FC\n for <u-boot@lists.denx.de>; Wed, 7 Apr 2021 08:43:43 +0200 (CEST)", "from smtp2.mailbox.org (smtp2.mailbox.org\n [IPv6:2001:67c:2050:105:465:1:2:0])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4FFZbz1FzFzQjbM;\n Wed, 7 Apr 2021 08:43:43 +0200 (CEST)", "from smtp2.mailbox.org ([80.241.60.241])\n by spamfilter04.heinlein-hosting.de (spamfilter04.heinlein-hosting.de\n [80.241.56.122]) (amavisd-new, port 10030)\n with ESMTP id BSy2VenlJ79d; Wed, 7 Apr 2021 08:43:36 +0200 (CEST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1617777828;\n\tbh=o979egc6739Iss6GmEQb0odtq0P8le3e5z6NU56+kOc=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=PXmuTAgzmgQtGaIK215/077Lneyr01lEvWpKrCI/BnOQkCEwllVvYAMjLv/3DK3dw\n\t Y2jJTFQcwp5Gk6SiBEPpCQmtHaMzVoa0aZpHbr0wMlPDFNnCprDs2vxGGKy2vW6lYg\n\t EzlbcuZsJfiQs51BMg1pZRUG8ZxkvIF/yEoLINsesgPTNZENnx57Db1zItf2yJ/QR0\n\t Qf2j4Lhcl2hf6AC6Y6gt+6A+d3RYBhhB5f9s0llH1OWKvaDjwqZBQXRN3eqUTISI7Q\n\t Mit2C6HcNJIsElMO920f5CxnF6scuUXr+Trj8BRXiHQcJsUu7iDU0LlN7lPGaVA7sH\n\t qYfDzUHbro3Rg==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE\n autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "Aaron Williams <awilliams@marvell.com>,\n Chandrakala Chavva <cchavva@marvell.com>,\n Daniel Schwierzeck <daniel.schwierzeck@gmail.com>", "Subject": "[PATCH v2 49/50] mips: octeon: Add Octeon PCIe host controller driver", "Date": "Wed, 7 Apr 2021 08:43:35 +0200", "Message-Id": "<20210407064335.525254-1-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-50-sr@denx.de>", "References": "<20201211160612.1498780-50-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.04 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "1A6251801", "X-Rspamd-UID": "caa76a", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.4 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "This patch adds the PCIe host controller driver for MIPS Octeon II/III.\nThe driver mainly consist of the PCI config functions, as all of the\ncomplex serdes related port / lane setup, is done in the serdes / pcie\ncode available in the \"arch/mips/mach-octeon\" directory.\n\nSigned-off-by: Stefan Roese <sr@denx.de>\nCc: Aaron Williams <awilliams@marvell.com>\nCc: Chandrakala Chavva <cchavva@marvell.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n---\nI'm sending only this patch from the serdes / QLM series with the PCIe\nsupport, as it's the only one that has some changes. To not \"pollute\"\nthe list with this huge series without need. Please let me know if I\nshould post the complete series again to the list or provide a gitlab\nbranch.\n\nv2:\n- Rebased on top of latest master\n- Changed priv_auto_alloc_size to priv_auto\n\n drivers/pci/Kconfig | 6 ++\n drivers/pci/Makefile | 1 +\n drivers/pci/pcie_octeon.c | 159 ++++++++++++++++++++++++++++++++++++++\n 3 files changed, 166 insertions(+)\n create mode 100644 drivers/pci/pcie_octeon.c", "diff": "diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig\nindex ba41787f64dc..0b2daeac23b6 100644\n--- a/drivers/pci/Kconfig\n+++ b/drivers/pci/Kconfig\n@@ -158,6 +158,12 @@ config PCI_OCTEONTX\n \t These controllers provide PCI configuration access to all on-board\n \t peripherals so it should only be disabled for testing purposes\n \n+config PCIE_OCTEON\n+\tbool \"MIPS Octeon PCIe support\"\n+\tdepends on ARCH_OCTEON\n+\thelp\n+\t Enable support for the MIPS Octeon SoC family PCIe controllers.\n+\n config PCI_XILINX\n \tbool \"Xilinx AXI Bridge for PCI Express\"\n \tdepends on DM_PCI\ndiff --git a/drivers/pci/Makefile b/drivers/pci/Makefile\nindex 5ed94bc95c27..dc04d1c7d675 100644\n--- a/drivers/pci/Makefile\n+++ b/drivers/pci/Makefile\n@@ -51,3 +51,4 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o\n obj-$(CONFIG_PCIE_DW_ROCKCHIP) += pcie_dw_rockchip.o\n obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o\n obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o\n+obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o\ndiff --git a/drivers/pci/pcie_octeon.c b/drivers/pci/pcie_octeon.c\nnew file mode 100644\nindex 000000000000..3b28bd81439f\n--- /dev/null\n+++ b/drivers/pci/pcie_octeon.c\n@@ -0,0 +1,159 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>\n+ */\n+\n+#include <dm.h>\n+#include <errno.h>\n+#include <fdtdec.h>\n+#include <log.h>\n+#include <pci.h>\n+#include <linux/delay.h>\n+\n+#include <mach/octeon-model.h>\n+#include <mach/octeon_pci.h>\n+#include <mach/cvmx-regs.h>\n+#include <mach/cvmx-pcie.h>\n+#include <mach/cvmx-pemx-defs.h>\n+\n+struct octeon_pcie {\n+\tvoid *base;\n+\tint first_busno;\n+\tu32 port;\n+\tstruct udevice *dev;\n+\tint pcie_port;\n+};\n+\n+static bool octeon_bdf_invalid(pci_dev_t bdf, int first_busno)\n+{\n+\t/*\n+\t * In PCIe only a single device (0) can exist on the local bus.\n+\t * Beyound the local bus, there might be a switch and everything\n+\t * is possible.\n+\t */\n+\tif ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+static int pcie_octeon_write_config(struct udevice *bus, pci_dev_t bdf,\n+\t\t\t\t uint offset, ulong value,\n+\t\t\t\t enum pci_size_t size)\n+{\n+\tstruct octeon_pcie *pcie = dev_get_priv(bus);\n+\tstruct pci_controller *hose = dev_get_uclass_priv(bus);\n+\tint busno;\n+\tint port;\n+\n+\tdebug(\"PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) \",\n+\t PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));\n+\tdebug(\"(addr,size,val)=(0x%04x, %d, 0x%08lx)\\n\", offset, size, value);\n+\n+\tport = pcie->pcie_port;\n+\tbusno = PCI_BUS(bdf) - hose->first_busno + 1;\n+\n+\tswitch (size) {\n+\tcase PCI_SIZE_8:\n+\t\tcvmx_pcie_config_write8(port, busno, PCI_DEV(bdf),\n+\t\t\t\t\tPCI_FUNC(bdf), offset, value);\n+\t\tbreak;\n+\tcase PCI_SIZE_16:\n+\t\tcvmx_pcie_config_write16(port, busno, PCI_DEV(bdf),\n+\t\t\t\t\t PCI_FUNC(bdf), offset, value);\n+\t\tbreak;\n+\tcase PCI_SIZE_32:\n+\t\tcvmx_pcie_config_write32(port, busno, PCI_DEV(bdf),\n+\t\t\t\t\t PCI_FUNC(bdf), offset, value);\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"Invalid size\\n\");\n+\t};\n+\n+\treturn 0;\n+}\n+\n+static int pcie_octeon_read_config(const struct udevice *bus, pci_dev_t bdf,\n+\t\t\t\t uint offset, ulong *valuep,\n+\t\t\t\t enum pci_size_t size)\n+{\n+\tstruct octeon_pcie *pcie = dev_get_priv(bus);\n+\tstruct pci_controller *hose = dev_get_uclass_priv(bus);\n+\tint busno;\n+\tint port;\n+\n+\tport = pcie->pcie_port;\n+\tbusno = PCI_BUS(bdf) - hose->first_busno + 1;\n+\tif (octeon_bdf_invalid(bdf, pcie->first_busno)) {\n+\t\t*valuep = pci_get_ff(size);\n+\t\treturn 0;\n+\t}\n+\n+\tswitch (size) {\n+\tcase PCI_SIZE_8:\n+\t\t*valuep = cvmx_pcie_config_read8(port, busno, PCI_DEV(bdf),\n+\t\t\t\t\t\t PCI_FUNC(bdf), offset);\n+\t\tbreak;\n+\tcase PCI_SIZE_16:\n+\t\t*valuep = cvmx_pcie_config_read16(port, busno, PCI_DEV(bdf),\n+\t\t\t\t\t\t PCI_FUNC(bdf), offset);\n+\t\tbreak;\n+\tcase PCI_SIZE_32:\n+\t\t*valuep = cvmx_pcie_config_read32(port, busno, PCI_DEV(bdf),\n+\t\t\t\t\t\t PCI_FUNC(bdf), offset);\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"Invalid size\\n\");\n+\t};\n+\n+\tdebug(\"%02x.%02x.%02x: u%d %x -> %lx\\n\",\n+\t PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, *valuep);\n+\n+\treturn 0;\n+}\n+\n+static int pcie_octeon_probe(struct udevice *dev)\n+{\n+\tstruct octeon_pcie *pcie = dev_get_priv(dev);\n+\tint node = cvmx_get_node_num();\n+\tint pcie_port;\n+\tint ret = 0;\n+\n+\t/* Get port number, lane number and memory target / attr */\n+\tif (ofnode_read_u32(dev_ofnode(dev), \"marvell,pcie-port\",\n+\t\t\t &pcie->port)) {\n+\t\tret = -ENODEV;\n+\t\tgoto err;\n+\t}\n+\n+\tpcie->first_busno = dev_seq(dev);\n+\tpcie_port = ((node << 4) | pcie->port);\n+\tret = cvmx_pcie_rc_initialize(pcie_port);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+\n+err:\n+\treturn ret;\n+}\n+\n+static const struct dm_pci_ops pcie_octeon_ops = {\n+\t.read_config = pcie_octeon_read_config,\n+\t.write_config = pcie_octeon_write_config,\n+};\n+\n+static const struct udevice_id pcie_octeon_ids[] = {\n+\t{ .compatible = \"marvell,pcie-host-octeon\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(pcie_octeon) = {\n+\t.name\t\t= \"pcie_octeon\",\n+\t.id\t\t= UCLASS_PCI,\n+\t.of_match\t= pcie_octeon_ids,\n+\t.ops\t\t= &pcie_octeon_ops,\n+\t.probe\t\t= pcie_octeon_probe,\n+\t.priv_auto\t= sizeof(struct octeon_pcie),\n+\t.flags\t\t= DM_FLAG_PRE_RELOC,\n+};\n", "prefixes": [ "v2", "49/50" ] }