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GET /api/patches/1447406/?format=api
{ "id": 1447406, "url": "http://patchwork.ozlabs.org/api/patches/1447406/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-20-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210304144651.310037-20-alistair.francis@wdc.com>", "list_archive_url": null, "date": "2021-03-04T14:46:51", "name": "[PULL,v2,19/19] hw/riscv: virt: Map high mmio for PCIe", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a67c347b8fe97f8123c0ba490990b109cf4026b9", "submitter": { "id": 74007, "url": "http://patchwork.ozlabs.org/api/people/74007/?format=api", "name": "Alistair Francis", "email": "alistair.francis@wdc.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-20-alistair.francis@wdc.com/mbox/", "series": [ { "id": 232161, "url": "http://patchwork.ozlabs.org/api/series/232161/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=232161", "date": "2021-03-04T14:46:33", "name": "[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/232161/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1447406/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1447406/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 04 Mar 2021 09:49:01 -0500", "from esa1.hgst.iphmx.com ([68.232.141.245]:44460)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1)\n (envelope-from <prvs=690dc056c=alistair.francis@wdc.com>)\n id 1lHpHf-0007uj-SG\n for qemu-devel@nongnu.org; Thu, 04 Mar 2021 09:49:01 -0500", "from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com)\n ([199.255.45.15])\n by ob1.hgst.iphmx.com with ESMTP; 04 Mar 2021 22:48:29 +0800", "from uls-op-cesaip01.wdc.com ([10.248.3.36])\n by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 04 Mar 2021 06:29:43 -0800", "from cnf008142.ad.shared (HELO alistair-risc6-laptop.hgst.com)\n ([10.86.48.109])\n by uls-op-cesaip01.wdc.com with ESMTP; 04 Mar 2021 06:48:29 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=simple/simple;\n d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com;\n t=1614869339; x=1646405339;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=n6WS1GlABXHpI2iXwDvsYBIR1AHLWWW3XNQqiPNgbXE=;\n b=l/qI3/aEO7UwZglmi81jrMT+wP3ODhcnrwUgVqHSpwdTyL/3BP5ozuS0\n 3t2gFo8frKswZcUfl9Rn3xhqPcLeHgYDv5f7JLaoPiXsujCDKA9Oq8f+k\n zcuXh8UApV6KqOrTjoM5g+4WZAXvXxHFcFsZ7zGmgnOgc03aW0h6ioGf2\n kODqWJH89GUJGh2BELPthZsuxAT2ho82N44co7lxkKkwgVXuQbp3ojMpL\n EBN/OICFTD9ifiHwG2OhzfiTUmudWqbykFkbbaPNcct9/QBiTBBopRNAp\n fdTf8KJM+cqGc3Q4UM+tUlXNxAUp6MK+NQjJrvICTUDSPpTMvMDxBAGKf A==;", "IronPort-SDR": [ "\n PxUINhAyPDi/pQ4D5CrIS8sJT1/YEj2Ey9COLRIedA/LjsSxN7p6UxyozZyZ6Ba4AURVWe2/S6\n 8p7/x3aMgr9ZANMzYYYJWoOJELbKVCZNHc2hZ0v2RSQXQAG9v6nbsoKVtqj4x7j9D3a2M7GPrl\n 2iLDn/DGIKObSMqdXMgrN0T6RGpiicZb+2xDMFI8tIwuDmFdg7quK7U06bvOqd0tbrJNzgsRdD\n zVc5O8T47JIv0SqvykdUMmlqoD55ddi/p09bMz9wbtrdt0Kmi2rbuHn+h6cFFH28Li8YSS42DZ\n k+s=", "\n 95nts3/wTYXvZf84A7HaEvHma6LUNYBHdz+aj+2ha9894j7VHV4Rki8xyJDFMAP+wMqwiBqvCe\n EuOX9sRBP7k3XJvNypFcV+t+kj8ORlVB5tXJFi4cesfZSIvujY6WvAfHzjdGoHH7IFIBRabojt\n QvUfQpQdXShAFfiri3bk59N5TusMdVXXgeh5EV+FXfsg2sY11IRBBqBfh4b9Y4lp985ZmJP5Rm\n C0injhnUkQdlrTkhyuSXgB7zwXCgmuTgL2iWkpzzRTAxbXMDm3nz20Wcg8UZWVmybPeTGqM/px\n /8vJ8s5StHYHb2MKTejY+jmI", "\n KfCtSX7Zn11P3rbripi0KmJT6lZl+iP+mFhOzH/dgf5tKycrRr1Xyt5kvIfbMDk1S/k/DTMYth\n xFfqxe4cPO90JR0vCHkGR0pYmLyy5JdXc944XUKp7PfKV1Y6cAdK4NzDs9l270GZNj+qmL5V40\n KLtDohi6gNj6CkmvthqdsfUBl7TuSy/agWFqutb83yQH0CF6oDWQxDD2IBXJGxpgqF0HSqbfOt\n 4pGDgvDN2dmWb0J4mpwAuRPQpmPk/VgBw7TOfOPpyMv47S9x7nt9pAgLLBgwFrFhdxJM7WhDiP\n YF8=" ], "X-IronPort-AV": "E=Sophos;i=\"5.81,222,1610380800\"; d=\"scan'208\";a=\"271984435\"", "WDCIronportException": "Internal", "From": "Alistair Francis <alistair.francis@wdc.com>", "To": "peter.maydell@linaro.org", "Subject": "[PULL v2 19/19] hw/riscv: virt: Map high mmio for PCIe", "Date": "Thu, 4 Mar 2021 09:46:51 -0500", "Message-Id": "<20210304144651.310037-20-alistair.francis@wdc.com>", "X-Mailer": "git-send-email 2.30.1", "In-Reply-To": "<20210304144651.310037-1-alistair.francis@wdc.com>", "References": "<20210304144651.310037-1-alistair.francis@wdc.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=68.232.141.245;\n envelope-from=prvs=690dc056c=alistair.francis@wdc.com;\n helo=esa1.hgst.iphmx.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alistair23@gmail.com, Bin Meng <bin.meng@windriver.com>,\n Alistair Francis <alistair.francis@wdc.com>, qemu-devel@nongnu.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Bin Meng <bin.meng@windriver.com>\n\nSome peripherals require 64-bit PCI address, so let's map the high\nmmio space for PCIe.\n\nFor RV32, the address is hardcoded to below 4 GiB from the highest\naccessible physical address. For RV64, the base address depends on\ntop of RAM and is aligned to its size which is using 16 GiB for now.\n\nSigned-off-by: Bin Meng <bin.meng@windriver.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nMessage-id: 20210220144807.819-5-bmeng.cn@gmail.com\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n hw/riscv/virt.c | 35 +++++++++++++++++++++++++++++++++--\n 1 file changed, 33 insertions(+), 2 deletions(-)", "diff": "diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c\nindex c4b8f455f8..4f0c2fbca0 100644\n--- a/hw/riscv/virt.c\n+++ b/hw/riscv/virt.c\n@@ -59,6 +59,15 @@ static const MemMapEntry virt_memmap[] = {\n [VIRT_DRAM] = { 0x80000000, 0x0 },\n };\n \n+/* PCIe high mmio is fixed for RV32 */\n+#define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL\n+#define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)\n+\n+/* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */\n+#define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)\n+\n+static MemMapEntry virt_high_pcie_memmap;\n+\n #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)\n \n static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,\n@@ -371,7 +380,11 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,\n 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,\n 1, FDT_PCI_RANGE_MMIO,\n 2, memmap[VIRT_PCIE_MMIO].base,\n- 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);\n+ 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,\n+ 1, FDT_PCI_RANGE_MMIO_64BIT,\n+ 2, virt_high_pcie_memmap.base,\n+ 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);\n+\n create_pcie_irq_map(fdt, name, plic_pcie_phandle);\n g_free(name);\n \n@@ -448,12 +461,14 @@ update_bootargs:\n static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,\n hwaddr ecam_base, hwaddr ecam_size,\n hwaddr mmio_base, hwaddr mmio_size,\n+ hwaddr high_mmio_base,\n+ hwaddr high_mmio_size,\n hwaddr pio_base,\n DeviceState *plic)\n {\n DeviceState *dev;\n MemoryRegion *ecam_alias, *ecam_reg;\n- MemoryRegion *mmio_alias, *mmio_reg;\n+ MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;\n qemu_irq irq;\n int i;\n \n@@ -473,6 +488,13 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,\n mmio_reg, mmio_base, mmio_size);\n memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);\n \n+ /* Map high MMIO space */\n+ high_mmio_alias = g_new0(MemoryRegion, 1);\n+ memory_region_init_alias(high_mmio_alias, OBJECT(dev), \"pcie-mmio-high\",\n+ mmio_reg, high_mmio_base, high_mmio_size);\n+ memory_region_add_subregion(get_system_memory(), high_mmio_base,\n+ high_mmio_alias);\n+\n sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);\n \n for (i = 0; i < GPEX_NUM_IRQS; i++) {\n@@ -598,6 +620,13 @@ static void virt_machine_init(MachineState *machine)\n error_report(\"Limiting RAM size to 10 GiB\");\n }\n #endif\n+ virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;\n+ virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;\n+ } else {\n+ virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;\n+ virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;\n+ virt_high_pcie_memmap.base =\n+ ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);\n }\n \n /* register system main memory (actual RAM) */\n@@ -683,6 +712,8 @@ static void virt_machine_init(MachineState *machine)\n memmap[VIRT_PCIE_ECAM].size,\n memmap[VIRT_PCIE_MMIO].base,\n memmap[VIRT_PCIE_MMIO].size,\n+ virt_high_pcie_memmap.base,\n+ virt_high_pcie_memmap.size,\n memmap[VIRT_PCIE_PIO].base,\n DEVICE(pcie_plic));\n \n", "prefixes": [ "PULL", "v2", "19/19" ] }