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GET /api/patches/1447396/?format=api
{ "id": 1447396, "url": "http://patchwork.ozlabs.org/api/patches/1447396/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-14-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210304144651.310037-14-alistair.francis@wdc.com>", "list_archive_url": null, "date": "2021-03-04T14:46:45", "name": "[PULL,v2,13/19] docs/system: riscv: Add documentation for sifive_u machine", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b0988f5689979b44bb6f5579ac5b8c9461e73fc0", "submitter": { "id": 74007, "url": "http://patchwork.ozlabs.org/api/people/74007/?format=api", "name": "Alistair Francis", "email": "alistair.francis@wdc.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-14-alistair.francis@wdc.com/mbox/", "series": [ { "id": 232161, "url": "http://patchwork.ozlabs.org/api/series/232161/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=232161", "date": "2021-03-04T14:46:33", "name": "[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/232161/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1447396/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1447396/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 04 Mar 2021 09:48:32 -0500", "from esa1.hgst.iphmx.com ([68.232.141.245]:44463)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1)\n (envelope-from <prvs=690dc056c=alistair.francis@wdc.com>)\n id 1lHpHB-0007up-9Y\n for qemu-devel@nongnu.org; Thu, 04 Mar 2021 09:48:32 -0500", "from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com)\n ([199.255.45.15])\n by ob1.hgst.iphmx.com with ESMTP; 04 Mar 2021 22:48:17 +0800", "from uls-op-cesaip01.wdc.com ([10.248.3.36])\n by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 04 Mar 2021 06:29:31 -0800", "from cnf008142.ad.shared (HELO alistair-risc6-laptop.hgst.com)\n ([10.86.48.109])\n by uls-op-cesaip01.wdc.com with ESMTP; 04 Mar 2021 06:48:16 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=simple/simple;\n d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com;\n t=1614869309; x=1646405309;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=MT3pivrNI2b4qzloLiaU6WL2dWXOV+6WGl4eZ9d0z24=;\n b=oatgMTCvpiwoJujM52onA63vuMu2CQJVNO4tZzmGWvSVk9oBe/vquaiO\n VPqe7VPNpL8TMcARtDW9P+wB66kqngfTjI1zTBpZk+FTnOeo+aAuPlyUc\n S9IEUQ1mCH/PaGkOk1UZnnSiaB4zd/pPVyLBgoprs9P6ZaX3WCNIRDqBM\n 8OiiRxuDhqx8u/T5E0XP0pW+DXmXU1BKFLYHUHPMsH+7e4+fWepGephwO\n F+xWFDQdmlhr8rV8CN0bVUL/tOalcnLHgHMUZpMc6iA2prCaT92+4UbOe\n D1PuLEsWXXNK+1nO4vSV4QyPOVxdll7Q/KZkPISDAVGc5oCfYAuI/Bh9e A==;", "IronPort-SDR": [ "\n r18RGUzfzwlhyCzFfm1oPkaGK+7rhyJTGFgT2F+28y+Wqzbo9UrkxoRYVM5G6cvyTMRvNgsJR3\n Cg62uXY37FVc3Nh+dmu9PXYEZ2nz8AW5No+CMeiwGbCIIVkxZfzQSXlL8NgBszidEbY612nOl5\n taLeAecyeU22noRbHIzLeVQSsc1riUuSyUNpgMGeGV2QF8ANOJTkXp8vSqxt3+ZBfgnFFUtJFI\n ZmdHRJ5eS31t897gPNElKdr3hTh/xROGx4qmHr/+n8d9HxzwPABQkw9Ro9D7KViKLmt3oZX9ic\n svg=", "\n +SNwXINueaOTukaUbo1xjJypdngRNPXnJR7rUcNTKCWAzs9C3+JFCLL4ITrd6V8p5t9kY7EnuD\n JhRXRodv30NhuyHMi5Xum4NAO59tutCgMZR9bB/PHx4vFFaKJXyx81JHeYYmT1k3sKgvFgmKdz\n YbueMYxcCbEkuDsls7oXCIxNGBWD0Le5KyTXLukpFoCviDj03seaEgOjkcrmr9fS2rqnM7T7hP\n a9X3s9f+14j3oQoEOmd3eDnWdZmGzfeRGHqx5sqAkdy8bhzcJSSn6fGM6R2YDSx9zxu1zERXQj\n 5WFD2AOpFxRSOmqtzKQZW355", "\n joxospLHBf+9q+r/oDvVmFXyum6iHTwZfJRVNP+tvgW+y7Lsa2z1RgQO83cZkfXiu5MZUjCAbf\n 6uQKlHJK0cfTGkSq42COF8Iw+NRVkco8VuthQ03nbZt8k0ddfLQWgnR97Hez5rHdNxILlq6/xU\n JpVThZxMXgGdvzIZLaa9det7zi+u3OIX+slkQomffNmaszvZJ39GZpWV7eQ337EER4EqZDKsc5\n fV0xzUyHqc+pxskiSc40HlLXsjP+w9/rQ8q5or1SHJx3F17ALZRNeykhjRxuQYtfUpXFg5yVY7\n YJs=" ], "X-IronPort-AV": "E=Sophos;i=\"5.81,222,1610380800\"; d=\"scan'208\";a=\"271984424\"", "WDCIronportException": "Internal", "From": "Alistair Francis <alistair.francis@wdc.com>", "To": "peter.maydell@linaro.org", "Subject": "[PULL v2 13/19] docs/system: riscv: Add documentation for sifive_u\n machine", "Date": "Thu, 4 Mar 2021 09:46:45 -0500", "Message-Id": "<20210304144651.310037-14-alistair.francis@wdc.com>", "X-Mailer": "git-send-email 2.30.1", "In-Reply-To": "<20210304144651.310037-1-alistair.francis@wdc.com>", "References": "<20210304144651.310037-1-alistair.francis@wdc.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=68.232.141.245;\n envelope-from=prvs=690dc056c=alistair.francis@wdc.com;\n helo=esa1.hgst.iphmx.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Palmer Dabbelt <palmerdabbelt@google.com>, alistair23@gmail.com,\n Bin Meng <bin.meng@windriver.com>,\n Alistair Francis <alistair.francis@wdc.com>,\n qemu-devel@nongnu.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Bin Meng <bin.meng@windriver.com>\n\nThis adds detailed documentation for RISC-V `sifive_u` machine,\nincluding the following information:\n\n- Supported devices\n- Hardware configuration information\n- Boot options\n- Machine-specific options\n- Running Linux kernel\n- Running VxWorks kernel\n- Running U-Boot, and with an alternate configuration\n\nSigned-off-by: Bin Meng <bin.meng@windriver.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>\nMessage-id: 20210126060007.12904-10-bmeng.cn@gmail.com\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n docs/system/riscv/sifive_u.rst | 336 +++++++++++++++++++++++++++++++++\n docs/system/target-riscv.rst | 10 +\n 2 files changed, 346 insertions(+)\n create mode 100644 docs/system/riscv/sifive_u.rst", "diff": "diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst\nnew file mode 100644\nindex 0000000000..98e7562848\n--- /dev/null\n+++ b/docs/system/riscv/sifive_u.rst\n@@ -0,0 +1,336 @@\n+SiFive HiFive Unleashed (``sifive_u``)\n+======================================\n+\n+SiFive HiFive Unleashed Development Board is the ultimate RISC-V development\n+board featuring the Freedom U540 multi-core RISC-V processor.\n+\n+Supported devices\n+-----------------\n+\n+The ``sifive_u`` machine supports the following devices:\n+\n+ * 1 E51 / E31 core\n+ * Up to 4 U54 / U34 cores\n+ * Core Level Interruptor (CLINT)\n+ * Platform-Level Interrupt Controller (PLIC)\n+ * Power, Reset, Clock, Interrupt (PRCI)\n+ * L2 Loosely Integrated Memory (L2-LIM)\n+ * DDR memory controller\n+ * 2 UARTs\n+ * 1 GEM Ethernet controller\n+ * 1 GPIO controller\n+ * 1 One-Time Programmable (OTP) memory with stored serial number\n+ * 1 DMA controller\n+ * 2 QSPI controllers\n+ * 1 ISSI 25WP256 flash\n+ * 1 SD card in SPI mode\n+\n+Please note the real world HiFive Unleashed board has a fixed configuration of\n+1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.\n+With QEMU, one can create a machine with 1 E51 core and up to 4 U54 cores. It\n+is also possible to create a 32-bit variant with the same peripherals except\n+that the RISC-V cores are replaced by the 32-bit ones (E31 and U34), to help\n+testing of 32-bit guest software.\n+\n+Hardware configuration information\n+----------------------------------\n+\n+The ``sifive_u`` machine automatically generates a device tree blob (\"dtb\")\n+which it passes to the guest. This provides information about the addresses,\n+interrupt lines and other configuration of the various devices in the system.\n+Guest software should discover the devices that are present in the generated\n+DTB instead of using a DTB for the real hardware, as some of the devices are\n+not modeled by QEMU and trying to access these devices may cause unexpected\n+behavior.\n+\n+Boot options\n+------------\n+\n+The ``sifive_u`` machine can start using the standard -kernel functionality\n+for loading a Linux kernel, a VxWorks kernel, a modified U-Boot bootloader\n+(S-mode) or ELF executable with the default OpenSBI firmware image as the\n+-bios. It also supports booting the unmodified U-Boot bootloader using the\n+standard -bios functionality.\n+\n+Machine-specific options\n+------------------------\n+\n+The following machine-specific options are supported:\n+\n+- serial=nnn\n+\n+ The board serial number. When not given, the default serial number 1 is used.\n+\n+ SiFive reserves the first 1 KiB of the 16 KiB OTP memory for internal use.\n+ The current usage is only used to store the serial number of the board at\n+ offset 0xfc. U-Boot reads the serial number from the OTP memory, and uses\n+ it to generate a unique MAC address to be programmed to the on-chip GEM\n+ Ethernet controller. When multiple QEMU ``sifive_u`` machines are created\n+ and connected to the same subnet, they all have the same MAC address hence\n+ it creates an unusable network. In such scenario, user should give different\n+ values to serial= when creating different ``sifive_u`` machines.\n+\n+- start-in-flash\n+\n+ When given, QEMU's ROM codes jump to QSPI memory-mapped flash directly.\n+ Otherwise QEMU will jump to DRAM or L2LIM depending on the msel= value.\n+ When not given, it defaults to direct DRAM booting.\n+\n+- msel=[6|11]\n+\n+ Mode Select (MSEL[3:0]) pins value, used to control where to boot from.\n+\n+ The FU540 SoC supports booting from several sources, which are controlled\n+ using the Mode Select pins on the chip. Typically, the boot process runs\n+ through several stages before it begins execution of user-provided programs.\n+ These stages typically include the following:\n+\n+ 1. Zeroth Stage Boot Loader (ZSBL), which is contained in an on-chip mask\n+ ROM and provided by QEMU. Note QEMU implemented ROM codes are not the\n+ same as what is programmed in the hardware. The QEMU one is a simplified\n+ version, but it provides the same functionality as the hardware.\n+ 2. First Stage Boot Loader (FSBL), which brings up PLLs and DDR memory.\n+ This is U-Boot SPL.\n+ 3. Second Stage Boot Loader (SSBL), which further initializes additional\n+ peripherals as needed. This is U-Boot proper combined with an OpenSBI\n+ fw_dynamic firmware image.\n+\n+ msel=6 means FSBL and SSBL are both on the QSPI flash. msel=11 means FSBL\n+ and SSBL are both on the SD card.\n+\n+Running Linux kernel\n+--------------------\n+\n+Linux mainline v5.10 release is tested at the time of writing. To build a\n+Linux mainline kernel that can be booted by the ``sifive_u`` machine in\n+64-bit mode, simply configure the kernel using the defconfig configuration:\n+\n+.. code-block:: bash\n+\n+ $ export ARCH=riscv\n+ $ export CROSS_COMPILE=riscv64-linux-\n+ $ make defconfig\n+ $ make\n+\n+To boot the newly built Linux kernel in QEMU with the ``sifive_u`` machine:\n+\n+.. code-block:: bash\n+\n+ $ qemu-system-riscv64 -M sifive_u -smp 5 -m 2G \\\n+ -display none -serial stdio \\\n+ -kernel arch/riscv/boot/Image \\\n+ -initrd /path/to/rootfs.ext4 \\\n+ -append \"root=/dev/ram\"\n+\n+To build a Linux mainline kernel that can be booted by the ``sifive_u`` machine\n+in 32-bit mode, use the rv32_defconfig configuration. A patch is required to\n+fix the 32-bit boot issue for Linux kernel v5.10.\n+\n+.. code-block:: bash\n+\n+ $ export ARCH=riscv\n+ $ export CROSS_COMPILE=riscv64-linux-\n+ $ curl https://patchwork.kernel.org/project/linux-riscv/patch/20201219001356.2887782-1-atish.patra@wdc.com/mbox/ > riscv.patch\n+ $ git am riscv.patch\n+ $ make rv32_defconfig\n+ $ make\n+\n+Replace ``qemu-system-riscv64`` with ``qemu-system-riscv32`` in the command\n+line above to boot the 32-bit Linux kernel. A rootfs image containing 32-bit\n+applications shall be used in order for kernel to boot to user space.\n+\n+Running VxWorks kernel\n+----------------------\n+\n+VxWorks 7 SR0650 release is tested at the time of writing. To build a 64-bit\n+VxWorks mainline kernel that can be booted by the ``sifive_u`` machine, simply\n+create a VxWorks source build project based on the sifive_generic BSP, and a\n+VxWorks image project to generate the bootable VxWorks image, by following the\n+BSP documentation instructions.\n+\n+A pre-built 64-bit VxWorks 7 image for HiFive Unleashed board is available as\n+part of the VxWorks SDK for testing as well. Instructions to download the SDK:\n+\n+.. code-block:: bash\n+\n+ $ wget https://labs.windriver.com/downloads/wrsdk-vxworks7-sifive-hifive-1.01.tar.bz2\n+ $ tar xvf wrsdk-vxworks7-sifive-hifive-1.01.tar.bz2\n+ $ ls bsps/sifive_generic_1_0_0_0/uboot/uVxWorks\n+\n+To boot the VxWorks kernel in QEMU with the ``sifive_u`` machine, use:\n+\n+.. code-block:: bash\n+\n+ $ qemu-system-riscv64 -M sifive_u -smp 5 -m 2G \\\n+ -display none -serial stdio \\\n+ -nic tap,ifname=tap0,script=no,downscript=no \\\n+ -kernel /path/to/vxWorks \\\n+ -append \"gem(0,0)host:vxWorks h=192.168.200.1 e=192.168.200.2:ffffff00 u=target pw=vxTarget f=0x01\"\n+\n+It is also possible to test 32-bit VxWorks on the ``sifive_u`` machine. Create\n+a 32-bit project to build the 32-bit VxWorks image, and use exact the same\n+command line options with ``qemu-system-riscv32``.\n+\n+Running U-Boot\n+--------------\n+\n+U-Boot mainline v2021.01 release is tested at the time of writing. To build a\n+U-Boot mainline bootloader that can be booted by the ``sifive_u`` machine, use\n+the sifive_fu540_defconfig with similar commands as described above for Linux:\n+\n+.. code-block:: bash\n+\n+ $ export CROSS_COMPILE=riscv64-linux-\n+ $ export OPENSBI=/path/to/opensbi-riscv64-generic-fw_dynamic.bin\n+ $ make sifive_fu540_defconfig\n+\n+You will get spl/u-boot-spl.bin and u-boot.itb file in the build tree.\n+\n+To start U-Boot using the ``sifive_u`` machine, prepare an SPI flash image, or\n+SD card image that is properly partitioned and populated with correct contents.\n+genimage_ can be used to generate these images.\n+\n+A sample configuration file for a 128 MiB SD card image is:\n+\n+.. code-block:: bash\n+\n+ $ cat genimage_sdcard.cfg\n+ image sdcard.img {\n+ size = 128M\n+\n+ hdimage {\n+ gpt = true\n+ }\n+\n+ partition u-boot-spl {\n+ image = \"u-boot-spl.bin\"\n+ offset = 17K\n+ partition-type-uuid = 5B193300-FC78-40CD-8002-E86C45580B47\n+ }\n+\n+ partition u-boot {\n+ image = \"u-boot.itb\"\n+ offset = 1041K\n+ partition-type-uuid = 2E54B353-1271-4842-806F-E436D6AF6985\n+ }\n+ }\n+\n+SPI flash image has slightly different partition offsets, and the size has to\n+be 32 MiB to match the ISSI 25WP256 flash on the real board:\n+\n+.. code-block:: bash\n+\n+ $ cat genimage_spi-nor.cfg\n+ image spi-nor.img {\n+ size = 32M\n+\n+ hdimage {\n+ gpt = true\n+ }\n+\n+ partition u-boot-spl {\n+ image = \"u-boot-spl.bin\"\n+ offset = 20K\n+ partition-type-uuid = 5B193300-FC78-40CD-8002-E86C45580B47\n+ }\n+\n+ partition u-boot {\n+ image = \"u-boot.itb\"\n+ offset = 1044K\n+ partition-type-uuid = 2E54B353-1271-4842-806F-E436D6AF6985\n+ }\n+ }\n+\n+Assume U-Boot binaries are put in the same directory as the config file,\n+we can generate the image by:\n+\n+.. code-block:: bash\n+\n+ $ genimage --config genimage_<boot_src>.cfg --inputpath .\n+\n+Boot U-Boot from SD card, by specifying msel=11 and pass the SD card image\n+to QEMU ``sifive_u`` machine:\n+\n+.. code-block:: bash\n+\n+ $ qemu-system-riscv64 -M sifive_u,msel=11 -smp 5 -m 8G \\\n+ -display none -serial stdio \\\n+ -bios /path/to/u-boot-spl.bin \\\n+ -drive file=/path/to/sdcard.img,if=sd\n+\n+Changing msel= value to 6, allows booting U-Boot from the SPI flash:\n+\n+.. code-block:: bash\n+\n+ $ qemu-system-riscv64 -M sifive_u,msel=6 -smp 5 -m 8G \\\n+ -display none -serial stdio \\\n+ -bios /path/to/u-boot-spl.bin \\\n+ -drive file=/path/to/spi-nor.img,if=mtd\n+\n+Note when testing U-Boot, QEMU automatically generated device tree blob is\n+not used because U-Boot itself embeds device tree blobs for U-Boot SPL and\n+U-Boot proper. Hence the number of cores and size of memory have to match\n+the real hardware, ie: 5 cores (-smp 5) and 8 GiB memory (-m 8G).\n+\n+Above use case is to run upstream U-Boot for the SiFive HiFive Unleashed\n+board on QEMU ``sifive_u`` machine out of the box. This allows users to\n+develop and test the recommended RISC-V boot flow with a real world use\n+case: ZSBL (in QEMU) loads U-Boot SPL from SD card or SPI flash to L2LIM,\n+then U-Boot SPL loads the combined payload image of OpenSBI fw_dynamic\n+firmware and U-Boot proper. However sometimes we want to have a quick test\n+of booting U-Boot on QEMU without the needs of preparing the SPI flash or\n+SD card images, an alternate way can be used, which is to create a U-Boot\n+S-mode image by modifying the configuration of U-Boot:\n+\n+.. code-block:: bash\n+\n+ $ make menuconfig\n+\n+then manually select the following configuration in U-Boot:\n+\n+ Device Tree Control > Provider of DTB for DT Control > Prior Stage bootloader DTB\n+\n+This lets U-Boot to use the QEMU generated device tree blob. During the build,\n+a build error will be seen below:\n+\n+.. code-block:: none\n+\n+ MKIMAGE u-boot.img\n+ ./tools/mkimage: Can't open arch/riscv/dts/hifive-unleashed-a00.dtb: No such file or directory\n+ ./tools/mkimage: failed to build FIT\n+ make: *** [Makefile:1440: u-boot.img] Error 1\n+\n+The above errors can be safely ignored as we don't run U-Boot SPL under QEMU\n+in this alternate configuration.\n+\n+Boot the 64-bit U-Boot S-mode image directly:\n+\n+.. code-block:: bash\n+\n+ $ qemu-system-riscv64 -M sifive_u -smp 5 -m 2G \\\n+ -display none -serial stdio \\\n+ -kernel /path/to/u-boot.bin\n+\n+It's possible to create a 32-bit U-Boot S-mode image as well.\n+\n+.. code-block:: bash\n+\n+ $ export CROSS_COMPILE=riscv64-linux-\n+ $ make sifive_fu540_defconfig\n+ $ make menuconfig\n+\n+then manually update the following configuration in U-Boot:\n+\n+ Device Tree Control > Provider of DTB for DT Control > Prior Stage bootloader DTB\n+ RISC-V architecture > Base ISA > RV32I\n+ Boot images > Text Base > 0x80400000\n+\n+Use the same command line options to boot the 32-bit U-Boot S-mode image:\n+\n+.. code-block:: bash\n+\n+ $ qemu-system-riscv32 -M sifive_u -smp 5 -m 2G \\\n+ -display none -serial stdio \\\n+ -kernel /path/to/u-boot.bin\n+\n+.. _genimage: https://github.com/pengutronix/genimage\ndiff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst\nindex 9f4b7586e5..94d99c4c82 100644\n--- a/docs/system/target-riscv.rst\n+++ b/docs/system/target-riscv.rst\n@@ -58,5 +58,15 @@ undocumented; you can get a complete list by running\n ``qemu-system-riscv64 --machine help``, or\n ``qemu-system-riscv32 --machine help``.\n \n+..\n+ This table of contents should be kept sorted alphabetically\n+ by the title text of each file, which isn't the same ordering\n+ as an alphabetical sort by filename.\n+\n+.. toctree::\n+ :maxdepth: 1\n+\n+ riscv/sifive_u\n+\n RISC-V CPU features\n -------------------\n", "prefixes": [ "PULL", "v2", "13/19" ] }