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GET /api/patches/1447395/?format=api
{ "id": 1447395, "url": "http://patchwork.ozlabs.org/api/patches/1447395/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-17-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210304144651.310037-17-alistair.francis@wdc.com>", "list_archive_url": null, "date": "2021-03-04T14:46:48", "name": "[PULL,v2,16/19] hw/riscv: Drop 'struct MemmapEntry'", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9e8169a888031890868dd95b8da3ed4c92dadf47", "submitter": { "id": 74007, "url": "http://patchwork.ozlabs.org/api/people/74007/?format=api", "name": "Alistair Francis", "email": "alistair.francis@wdc.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-17-alistair.francis@wdc.com/mbox/", "series": [ { "id": 232161, "url": "http://patchwork.ozlabs.org/api/series/232161/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=232161", "date": "2021-03-04T14:46:33", "name": "[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/232161/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1447395/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1447395/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256\n header.s=dkim.wdc.com header.b=I6Z3LB7V;\n\tdkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4DrvHK06Dyz9sSC\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 5 Mar 2021 02:02:37 +1100 (AEDT)", "from localhost ([::1]:60664 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1lHpUo-0006XO-Vf\n\tfor incoming@patchwork.ozlabs.org; Thu, 04 Mar 2021 10:02:35 -0500", "from eggs.gnu.org ([2001:470:142:3::10]:60492)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1)\n (envelope-from <prvs=690dc056c=alistair.francis@wdc.com>)\n id 1lHpHU-0002Ep-6i\n for qemu-devel@nongnu.org; Thu, 04 Mar 2021 09:48:50 -0500", "from esa1.hgst.iphmx.com ([68.232.141.245]:44463)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1)\n (envelope-from <prvs=690dc056c=alistair.francis@wdc.com>)\n id 1lHpHO-0007up-RI\n for qemu-devel@nongnu.org; Thu, 04 Mar 2021 09:48:47 -0500", "from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com)\n ([199.255.45.15])\n by ob1.hgst.iphmx.com with ESMTP; 04 Mar 2021 22:48:25 +0800", "from uls-op-cesaip01.wdc.com ([10.248.3.36])\n by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 04 Mar 2021 06:29:38 -0800", "from cnf008142.ad.shared (HELO alistair-risc6-laptop.hgst.com)\n ([10.86.48.109])\n by uls-op-cesaip01.wdc.com with ESMTP; 04 Mar 2021 06:48:25 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=simple/simple;\n d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com;\n t=1614869322; x=1646405322;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=qT5vU9bXKKNvt1fBrduvejy2fzNPFhNzbK8xQkdGGew=;\n b=I6Z3LB7V2TRO5fE+S7moLzn3W7eJAoVHdbAOGxgdbzjhGiMdxZkTtAbB\n Fg8IYJdKg5PxwGz4rKGgrvdd/G2hWsNs6dQ7F+0Hf2Iy6OBtJRIi6BeQV\n auN2eyEQvwQq/DdGciKuw/gz7OFnIuURYBjqgAZNdoXR2P4CqPb7EJlKS\n DmsaRg/duaLIbYJ7TX1h5JiTWpICXK6fcLxWKyNeZK39x+D/0D5FRbYQU\n lScjhdPNAgTWRkHfDsLe8ST9G6VZ3axIjHeU2lFCTWP8PHaNP9TNqZza8\n wwU8srltnnSq+6yIch/O9wi0zCtd1XtaOSCwETTnNxYHVIhLioAJ0+6eW w==;", "IronPort-SDR": [ "\n uKu7FkxSYmIbggRT/61vL9qimQdSvQRQ6vLftypYvrM/Ldebdt4y3JBBQIXMNrS/sx70wdYLBn\n zid+DEZUZO58WufTc9DO9xg97WY3+JJFXZxxUGvRl8gYkVad+k3bY/83UMjI2fP/QVwGB6rYgj\n Pw7Qa3fFL7ZO3sN8wQnX9HW2hlb2NBaRdKVFzBXYsleVVWVaiUt1qpBQD9f7MgNX2CCW9IsYWu\n QxcUmiW/AcAiE0aYyasMOEBbN/zuS6xiNrSbSSRsm0pZlGskM5Pvtp9Zpnqx7voZW9EwrwXiXS\n d10=", "\n RV2laO2IXE5AVRqqQl8sLD5EQTrIuhulhz1okyk3C5HjEqFh8J6y+1IUdUPEnvvTJZ6KbozQW+\n 6DVtvfco/3DiS+LIm0DbqfpWG+XP6kBSrcK9bkh7Z4hPpsmqvNEu/deWms9+UH3NTs8RnwYPlD\n 8TQ9fOniK8VfI3UYcIgDb+u1MMNKv9MPPM8eLe5HuEWRpQN4G95aiDFTqxLWq0PFNKzSMGgF1F\n OiBpndUfqTgJyazWLpgBPW+tuz+yOZwMPQr6+9q/e71GQzZ3dbBGmLdI1iiiyzES3wtnVtxc7Y\n EuDISx1kl2yYtbT9XLZmx3IV", "\n Xh8pnXvS0JJPFlAFM8riXt5B5zB8sJy1cR1AqbT6Q8xoDLABRTmo+NsWUIi9LZTR+rr9VWMJhk\n HDt0rf3s2DvDLxRsSM76Lj9XoFGmAprpdeqm5dUnex0ndyLwH0gluBIqagOQbSxAMrEFqKM9IT\n ar52Og1UEx7I15Yl86x7SWB4aNBAHBWE7gHyW1j/b1qfC2aWH64D+q8aolxWzHTWKDAw5xCPNc\n JyNHqdaYlJMLcp+Q8Sogd1rhtMK24hth9gkuZ1KjD9Umu4BpoYa/0QOkMs20yxQQrma/wdsBUG\n EVI=" ], "X-IronPort-AV": "E=Sophos;i=\"5.81,222,1610380800\"; d=\"scan'208\";a=\"271984431\"", "WDCIronportException": "Internal", "From": "Alistair Francis <alistair.francis@wdc.com>", "To": "peter.maydell@linaro.org", "Subject": "[PULL v2 16/19] hw/riscv: Drop 'struct MemmapEntry'", "Date": "Thu, 4 Mar 2021 09:46:48 -0500", "Message-Id": "<20210304144651.310037-17-alistair.francis@wdc.com>", "X-Mailer": "git-send-email 2.30.1", "In-Reply-To": "<20210304144651.310037-1-alistair.francis@wdc.com>", "References": "<20210304144651.310037-1-alistair.francis@wdc.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=68.232.141.245;\n envelope-from=prvs=690dc056c=alistair.francis@wdc.com;\n helo=esa1.hgst.iphmx.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alistair23@gmail.com, Bin Meng <bin.meng@windriver.com>,\n Alistair Francis <alistair.francis@wdc.com>, qemu-devel@nongnu.org,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Bin Meng <bin.meng@windriver.com>\n\nThere is already a MemMapEntry type defined in hwaddr.h. Let's drop\nthe RISC-V defined `struct MemmapEntry` and use the existing one.\n\nSigned-off-by: Bin Meng <bin.meng@windriver.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nMessage-id: 20210220144807.819-2-bmeng.cn@gmail.com\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n hw/riscv/microchip_pfsoc.c | 9 +++------\n hw/riscv/opentitan.c | 9 +++------\n hw/riscv/sifive_e.c | 9 +++------\n hw/riscv/sifive_u.c | 11 ++++-------\n hw/riscv/spike.c | 9 +++------\n hw/riscv/virt.c | 9 +++------\n 6 files changed, 19 insertions(+), 37 deletions(-)", "diff": "diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c\nindex e952b49e8c..266f1c3342 100644\n--- a/hw/riscv/microchip_pfsoc.c\n+++ b/hw/riscv/microchip_pfsoc.c\n@@ -86,10 +86,7 @@\n * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm\n * describes the complete IOSCB modules memory maps\n */\n-static const struct MemmapEntry {\n- hwaddr base;\n- hwaddr size;\n-} microchip_pfsoc_memmap[] = {\n+static const MemMapEntry microchip_pfsoc_memmap[] = {\n [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },\n [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },\n [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },\n@@ -182,7 +179,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)\n {\n MachineState *ms = MACHINE(qdev_get_machine());\n MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);\n- const struct MemmapEntry *memmap = microchip_pfsoc_memmap;\n+ const MemMapEntry *memmap = microchip_pfsoc_memmap;\n MemoryRegion *system_memory = get_system_memory();\n MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1);\n MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);\n@@ -451,7 +448,7 @@ type_init(microchip_pfsoc_soc_register_types)\n static void microchip_icicle_kit_machine_init(MachineState *machine)\n {\n MachineClass *mc = MACHINE_GET_CLASS(machine);\n- const struct MemmapEntry *memmap = microchip_pfsoc_memmap;\n+ const MemMapEntry *memmap = microchip_pfsoc_memmap;\n MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);\n MemoryRegion *system_memory = get_system_memory();\n MemoryRegion *mem_low = g_new(MemoryRegion, 1);\ndiff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c\nindex af3456932f..e168bffe69 100644\n--- a/hw/riscv/opentitan.c\n+++ b/hw/riscv/opentitan.c\n@@ -28,10 +28,7 @@\n #include \"qemu/units.h\"\n #include \"sysemu/sysemu.h\"\n \n-static const struct MemmapEntry {\n- hwaddr base;\n- hwaddr size;\n-} ibex_memmap[] = {\n+static const MemMapEntry ibex_memmap[] = {\n [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },\n [IBEX_DEV_RAM] = { 0x10000000, 0x10000 },\n [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },\n@@ -66,7 +63,7 @@ static const struct MemmapEntry {\n \n static void opentitan_board_init(MachineState *machine)\n {\n- const struct MemmapEntry *memmap = ibex_memmap;\n+ const MemMapEntry *memmap = ibex_memmap;\n OpenTitanState *s = g_new0(OpenTitanState, 1);\n MemoryRegion *sys_mem = get_system_memory();\n MemoryRegion *main_mem = g_new(MemoryRegion, 1);\n@@ -114,7 +111,7 @@ static void lowrisc_ibex_soc_init(Object *obj)\n \n static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)\n {\n- const struct MemmapEntry *memmap = ibex_memmap;\n+ const MemMapEntry *memmap = ibex_memmap;\n MachineState *ms = MACHINE(qdev_get_machine());\n LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);\n MemoryRegion *sys_mem = get_system_memory();\ndiff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c\nindex 59bac4cc9a..f939bcf9ea 100644\n--- a/hw/riscv/sifive_e.c\n+++ b/hw/riscv/sifive_e.c\n@@ -50,10 +50,7 @@\n #include \"sysemu/sysemu.h\"\n #include \"exec/address-spaces.h\"\n \n-static const struct MemmapEntry {\n- hwaddr base;\n- hwaddr size;\n-} sifive_e_memmap[] = {\n+static MemMapEntry sifive_e_memmap[] = {\n [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },\n [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },\n [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },\n@@ -77,7 +74,7 @@ static const struct MemmapEntry {\n \n static void sifive_e_machine_init(MachineState *machine)\n {\n- const struct MemmapEntry *memmap = sifive_e_memmap;\n+ const MemMapEntry *memmap = sifive_e_memmap;\n \n SiFiveEState *s = RISCV_E_MACHINE(machine);\n MemoryRegion *sys_mem = get_system_memory();\n@@ -187,7 +184,7 @@ static void sifive_e_soc_init(Object *obj)\n static void sifive_e_soc_realize(DeviceState *dev, Error **errp)\n {\n MachineState *ms = MACHINE(qdev_get_machine());\n- const struct MemmapEntry *memmap = sifive_e_memmap;\n+ const MemMapEntry *memmap = sifive_e_memmap;\n SiFiveESoCState *s = RISCV_E_SOC(dev);\n MemoryRegion *sys_mem = get_system_memory();\n \ndiff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c\nindex 6c1158a848..7b59942369 100644\n--- a/hw/riscv/sifive_u.c\n+++ b/hw/riscv/sifive_u.c\n@@ -63,10 +63,7 @@\n \n #include <libfdt.h>\n \n-static const struct MemmapEntry {\n- hwaddr base;\n- hwaddr size;\n-} sifive_u_memmap[] = {\n+static const MemMapEntry sifive_u_memmap[] = {\n [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },\n [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },\n [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },\n@@ -91,7 +88,7 @@ static const struct MemmapEntry {\n #define OTP_SERIAL 1\n #define GEM_REVISION 0x10070109\n \n-static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,\n+static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,\n uint64_t mem_size, const char *cmdline, bool is_32_bit)\n {\n MachineState *ms = MACHINE(qdev_get_machine());\n@@ -484,7 +481,7 @@ static void sifive_u_machine_reset(void *opaque, int n, int level)\n \n static void sifive_u_machine_init(MachineState *machine)\n {\n- const struct MemmapEntry *memmap = sifive_u_memmap;\n+ const MemMapEntry *memmap = sifive_u_memmap;\n SiFiveUState *s = RISCV_U_MACHINE(machine);\n MemoryRegion *system_memory = get_system_memory();\n MemoryRegion *main_mem = g_new(MemoryRegion, 1);\n@@ -766,7 +763,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)\n {\n MachineState *ms = MACHINE(qdev_get_machine());\n SiFiveUSoCState *s = RISCV_U_SOC(dev);\n- const struct MemmapEntry *memmap = sifive_u_memmap;\n+ const MemMapEntry *memmap = sifive_u_memmap;\n MemoryRegion *system_memory = get_system_memory();\n MemoryRegion *mask_rom = g_new(MemoryRegion, 1);\n MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);\ndiff --git a/hw/riscv/spike.c b/hw/riscv/spike.c\nindex 56986ecfe0..ed4ca9808e 100644\n--- a/hw/riscv/spike.c\n+++ b/hw/riscv/spike.c\n@@ -43,16 +43,13 @@\n #include \"sysemu/qtest.h\"\n #include \"sysemu/sysemu.h\"\n \n-static const struct MemmapEntry {\n- hwaddr base;\n- hwaddr size;\n-} spike_memmap[] = {\n+static const MemMapEntry spike_memmap[] = {\n [SPIKE_MROM] = { 0x1000, 0xf000 },\n [SPIKE_CLINT] = { 0x2000000, 0x10000 },\n [SPIKE_DRAM] = { 0x80000000, 0x0 },\n };\n \n-static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,\n+static void create_fdt(SpikeState *s, const MemMapEntry *memmap,\n uint64_t mem_size, const char *cmdline, bool is_32_bit)\n {\n void *fdt;\n@@ -179,7 +176,7 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,\n \n static void spike_board_init(MachineState *machine)\n {\n- const struct MemmapEntry *memmap = spike_memmap;\n+ const MemMapEntry *memmap = spike_memmap;\n SpikeState *s = SPIKE_MACHINE(machine);\n MemoryRegion *system_memory = get_system_memory();\n MemoryRegion *main_mem = g_new(MemoryRegion, 1);\ndiff --git a/hw/riscv/virt.c b/hw/riscv/virt.c\nindex 2299b3a6be..cfd52bc59b 100644\n--- a/hw/riscv/virt.c\n+++ b/hw/riscv/virt.c\n@@ -43,10 +43,7 @@\n #include \"hw/pci/pci.h\"\n #include \"hw/pci-host/gpex.h\"\n \n-static const struct MemmapEntry {\n- hwaddr base;\n- hwaddr size;\n-} virt_memmap[] = {\n+static const MemMapEntry virt_memmap[] = {\n [VIRT_DEBUG] = { 0x0, 0x100 },\n [VIRT_MROM] = { 0x1000, 0xf000 },\n [VIRT_TEST] = { 0x100000, 0x1000 },\n@@ -170,7 +167,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename,\n 0x1800, 0, 0, 0x7);\n }\n \n-static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,\n+static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,\n uint64_t mem_size, const char *cmdline, bool is_32_bit)\n {\n void *fdt;\n@@ -490,7 +487,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,\n \n static void virt_machine_init(MachineState *machine)\n {\n- const struct MemmapEntry *memmap = virt_memmap;\n+ const MemMapEntry *memmap = virt_memmap;\n RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);\n MemoryRegion *system_memory = get_system_memory();\n MemoryRegion *main_mem = g_new(MemoryRegion, 1);\n", "prefixes": [ "PULL", "v2", "16/19" ] }