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GET /api/patches/1444217/?format=api
{ "id": 1444217, "url": "http://patchwork.ozlabs.org/api/patches/1444217/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1614244979-48216-23-git-send-email-bmeng.cn@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1614244979-48216-23-git-send-email-bmeng.cn@gmail.com>", "list_archive_url": null, "date": "2021-02-25T09:22:43", "name": "[v3,22/38] ppc: qemu: Switch over to use DM ETH and PCI", "commit_ref": "8ee401670a53307e7e0e2754f09e0126bfaa11da", "pull_url": null, "state": "accepted", "archived": false, "hash": "b68d4de092d65ca73cd4831045ceeaa7e75935b8", "submitter": { "id": 64981, "url": "http://patchwork.ozlabs.org/api/people/64981/?format=api", "name": "Bin Meng", "email": "bmeng.cn@gmail.com" }, "delegate": { "id": 87636, "url": "http://patchwork.ozlabs.org/api/users/87636/?format=api", "username": "priyankajain", "first_name": "Priyanka", "last_name": "Jain", "email": "priyanka.jain@nxp.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1614244979-48216-23-git-send-email-bmeng.cn@gmail.com/mbox/", "series": [ { "id": 230985, "url": "http://patchwork.ozlabs.org/api/series/230985/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=230985", "date": "2021-02-25T09:22:22", "name": "ppc: qemu: Convert qemu-ppce500 to driver model and enable additional driver support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/230985/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1444217/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1444217/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20161025 header.b=AgW7j/qS;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.b=\"AgW7j/qS\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=bmeng.cn@gmail.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4DmSBb085Vz9s1l\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 25 Feb 2021 20:28:06 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 72F3C8204A;\n\tThu, 25 Feb 2021 10:27:11 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id C93DD812E4; Thu, 25 Feb 2021 10:25:17 +0100 (CET)", "from mail-ej1-x634.google.com (mail-ej1-x634.google.com\n [IPv6:2a00:1450:4864:20::634])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id B072A81F8D\n for <u-boot@lists.denx.de>; Thu, 25 Feb 2021 10:25:02 +0100 (CET)", "by mail-ej1-x634.google.com with SMTP id do6so7661851ejc.3\n for <u-boot@lists.denx.de>; Thu, 25 Feb 2021 01:25:02 -0800 (PST)", "from pek-vx-bsp2.wrs.com\n (ec2-44-242-66-180.us-west-2.compute.amazonaws.com. [44.242.66.180])\n by smtp.gmail.com with ESMTPSA id k22sm2987368edv.33.2021.02.25.01.24.58\n (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128);\n Thu, 25 Feb 2021 01:25:01 -0800 (PST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n h=from:to:cc:subject:date:message-id:in-reply-to:references;\n bh=/QjqrpuejqfJw7u5PLUrfacuzHo8AvQ+FlXln2zSOu0=;\n b=AgW7j/qSb6ZduM7MukuQ1kxiIGcL3bXU+4fxpxVwlvs9EE/4XiYROlH6k/Icb4XvYu\n C7vWrlzifNZol3j1vEYNDEqcXl4YwZGSxtr1H8rWiDk7ejj9rFxPweRivJ7kxm0bY5Zl\n wrqji2OoKMIVgzIBOPah9NzT5y7CBMFX8MudWNrdnpaRyiOBi3yt6qnxfexcfVFwuHpw\n Sd6jEjvS5dzq1obUITCDl9C3iAwNxRk7xvtZW8/kDb05U8KMSWNgdZpm/pXeCrvK1a21\n 8Y5vmvxZCMcMErMFo1Jo72hEzw3gTjYd/ntVXDCrb1hJ3X+wIAqcPLFow3iqh/jSdhcs\n PMVA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references;\n bh=/QjqrpuejqfJw7u5PLUrfacuzHo8AvQ+FlXln2zSOu0=;\n b=fo3OvdRncXpDpMmNDLm63M4pBrmvbwdEDPIn5sPqURKnoH698JnPFK7pkbjq31RUTn\n sTXg0DjkvhI7AnedTIyxTFTs1IO+8+09MgJOOirx3NlO+a3Ktl7iMnsbwxPQVpK8JrbG\n cDkP5ukm1eiB8V0O1i1/ZF3bZOUAiKjef7qb76PZXMLqxgW5cnGuyPuR/sNwA7JuCdXR\n wyp7rtnxAvei+aEDlGBa0PIVD2ooP/lssd2Hjl58fsIo+nVtsJIUfq6cR9NVD0n4hZii\n IRpP4RnV3pc2ELcL+4I7S1Xvcr0hTX0yYOUO+WsxIkTSf022JpHqc6uTECGM3fbI5FSf\n HbLA==", "X-Gm-Message-State": "AOAM531QSwT2nkdN6yyaIGcS7IvxUezTdgZmucOWE3K4mI5SIDv3LCAt\n h7V6qy6ZYKPqnOm6pKgGCj8=", "X-Google-Smtp-Source": "\n ABdhPJwSwV8FRloW70uI6JCbtZMF6jzEoB/A8yQ9i8i77wUmpDKxgIs9e1ytNiNz8mlAqp0tOCwPUg==", "X-Received": "by 2002:a17:907:12d0:: with SMTP id\n vp16mr1853760ejb.232.1614245102138;\n Thu, 25 Feb 2021 01:25:02 -0800 (PST)", "From": "Bin Meng <bmeng.cn@gmail.com>", "To": "Simon Glass <sjg@chromium.org>, Alexander Graf <agraf@csgraf.de>,\n Priyanka Jain <priyanka.jain@nxp.com>", "Cc": "U-Boot Mailing List <u-boot@lists.denx.de>, Tom Rini <trini@konsulko.com>", "Subject": "[PATCH v3 22/38] ppc: qemu: Switch over to use DM ETH and PCI", "Date": "Thu, 25 Feb 2021 17:22:43 +0800", "Message-Id": "<1614244979-48216-23-git-send-email-bmeng.cn@gmail.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1614244979-48216-1-git-send-email-bmeng.cn@gmail.com>", "References": "<1614244979-48216-1-git-send-email-bmeng.cn@gmail.com>", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.4 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "At present the board supports non-DM version PCI and E1000 drivers.\nSwitch over to use DM ETH and PCI by:\n\n- Rewrite the PCI address map functions using DM APIs\n- Enable CONFIG_MISC_INIT_R to do the PCI initialization and\n address map\n- Drop unnecessary ad-hoc config macros\n- Remove board_eth_init() in the board codes\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\nReviewed-by: Simon Glass <sjg@chromium.org>\nReviewed-by: Priyanka Jain <priyanka.jain@nxp.com>\n---\n\n(no changes since v1)\n\n board/freescale/qemu-ppce500/qemu-ppce500.c | 111 ++++++----------------------\n configs/qemu-ppce500_defconfig | 4 +-\n include/configs/qemu-ppce500.h | 13 ----\n 3 files changed, 24 insertions(+), 104 deletions(-)", "diff": "diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c\nindex db13582..659f794 100644\n--- a/board/freescale/qemu-ppce500/qemu-ppce500.c\n+++ b/board/freescale/qemu-ppce500/qemu-ppce500.c\n@@ -6,6 +6,7 @@\n #include <common.h>\n #include <command.h>\n #include <cpu_func.h>\n+#include <dm.h>\n #include <env.h>\n #include <init.h>\n #include <log.h>\n@@ -79,27 +80,9 @@ int checkboard(void)\n \treturn 0;\n }\n \n-static int pci_map_region(void *fdt, int pci_node, int range_id,\n-\t\t\t phys_addr_t *pbaddr, phys_size_t *ppaddr,\n-\t\t\t pci_addr_t *pvaddr, pci_size_t *psize,\n-\t\t\t ulong *pmap_addr)\n+static int pci_map_region(phys_addr_t paddr, phys_size_t size, ulong *pmap_addr)\n {\n-\tuint64_t baddr;\n-\tuint64_t paddr;\n-\tuint64_t size;\n \tulong map_addr;\n-\tint r;\n-\n-\tr = fdt_read_range(fdt, pci_node, range_id, &baddr, &paddr, &size);\n-\tif (r)\n-\t\treturn r;\n-\n-\tif (pbaddr)\n-\t\t*pbaddr = baddr;\n-\tif (ppaddr)\n-\t\t*ppaddr = paddr;\n-\tif (psize)\n-\t\t*psize = size;\n \n \tif (!pmap_addr)\n \t\treturn 0;\n@@ -117,82 +100,37 @@ static int pci_map_region(void *fdt, int pci_node, int range_id,\n \tassert(!tlb_map_range(map_addr, paddr, size, TLB_MAP_IO));\n \t*pmap_addr = map_addr + size;\n \n-\tif (pvaddr)\n-\t\t*pvaddr = map_addr;\n-\n \treturn 0;\n }\n \n-void pci_init_board(void)\n+int misc_init_r(void)\n {\n-\tstruct pci_controller *pci_hoses;\n-\tvoid *fdt = get_fdt_virt();\n-\tint pci_node = -1;\n-\tint pci_num = 0;\n-\tint pci_count = 0;\n+\tstruct udevice *dev;\n+\tstruct pci_region *io;\n+\tstruct pci_region *mem;\n+\tstruct pci_region *pre;\n \tulong map_addr;\n+\tint ret;\n \n-\tputs(\"\\n\");\n+\t/* Ensure PCI is probed */\n+\tuclass_first_device(UCLASS_PCI, &dev);\n+\n+\tpci_get_regions(dev, &io, &mem, &pre);\n \n \t/* Start MMIO and PIO range maps above RAM */\n \tmap_addr = CONFIG_SYS_PCI_MAP_START;\n \n-\t/* Count and allocate PCI buses */\n-\tpci_node = fdt_node_offset_by_prop_value(fdt, pci_node,\n-\t\t\t\"device_type\", \"pci\", 4);\n-\twhile (pci_node != -FDT_ERR_NOTFOUND) {\n-\t\tpci_node = fdt_node_offset_by_prop_value(fdt, pci_node,\n-\t\t\t\t\"device_type\", \"pci\", 4);\n-\t\tpci_count++;\n-\t}\n-\n-\tif (pci_count) {\n-\t\tpci_hoses = malloc(sizeof(struct pci_controller) * pci_count);\n-\t} else {\n-\t\tprintf(\"PCI: disabled\\n\\n\");\n-\t\treturn;\n-\t}\n+\t/* Map MMIO range */\n+\tret = pci_map_region(mem->phys_start, mem->size, &map_addr);\n+\tif (ret)\n+\t\treturn ret;\n \n-\t/* Spawn PCI buses based on device tree */\n-\tpci_node = fdt_node_offset_by_prop_value(fdt, pci_node,\n-\t\t\t\"device_type\", \"pci\", 4);\n-\twhile (pci_node != -FDT_ERR_NOTFOUND) {\n-\t\tstruct fsl_pci_info pci_info = { };\n-\t\tconst fdt32_t *reg;\n-\t\tint r;\n-\n-\t\treg = fdt_getprop(fdt, pci_node, \"reg\", NULL);\n-\t\tpci_info.regs = fdt_translate_address(fdt, pci_node, reg);\n-\n-\t\t/* Map MMIO range */\n-\t\tr = pci_map_region(fdt, pci_node, 0, &pci_info.mem_bus,\n-\t\t\t\t &pci_info.mem_phys, NULL,\n-\t\t\t\t &pci_info.mem_size, &map_addr);\n-\t\tif (r)\n-\t\t\tbreak;\n-\n-\t\t/* Map PIO range */\n-\t\tr = pci_map_region(fdt, pci_node, 1, &pci_info.io_bus,\n-\t\t\t\t &pci_info.io_phys, NULL,\n-\t\t\t\t &pci_info.io_size, &map_addr);\n-\t\tif (r)\n-\t\t\tbreak;\n-\n-\t\t/* Instantiate */\n-\t\tpci_info.pci_num = pci_num + 1;\n-\n-\t\tfsl_setup_hose(&pci_hoses[pci_num], pci_info.regs);\n-\t\tprintf(\"PCI: base address %lx\\n\", pci_info.regs);\n-\n-\t\tfsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num);\n-\n-\t\t/* Jump to next PCI node */\n-\t\tpci_node = fdt_node_offset_by_prop_value(fdt, pci_node,\n-\t\t\t\t\"device_type\", \"pci\", 4);\n-\t\tpci_num++;\n-\t}\n+\t/* Map PIO range */\n+\tret = pci_map_region(io->phys_start, io->size, &map_addr);\n+\tif (ret)\n+\t\treturn ret;\n \n-\tputs(\"\\n\");\n+\treturn 0;\n }\n \n int last_stage_init(void)\n@@ -235,16 +173,9 @@ static uint64_t get_linear_ram_size(void)\n \tpanic(\"Couldn't determine RAM size\");\n }\n \n-int board_eth_init(struct bd_info *bis)\n-{\n-\treturn pci_eth_init(bis);\n-}\n-\n #if defined(CONFIG_OF_BOARD_SETUP)\n int ft_board_setup(void *blob, struct bd_info *bd)\n {\n-\tFT_FSL_PCI_SETUP;\n-\n \treturn 0;\n }\n #endif\ndiff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig\nindex c528a68..4a4b369 100644\n--- a/configs/qemu-ppce500_defconfig\n+++ b/configs/qemu-ppce500_defconfig\n@@ -11,7 +11,6 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y\n CONFIG_BOOTDELAY=1\n # CONFIG_DISPLAY_BOARDINFO is not set\n CONFIG_LAST_STAGE_INIT=y\n-# CONFIG_MISC_INIT_R is not set\n CONFIG_HUSH_PARSER=y\n CONFIG_CMD_REGINFO=y\n CONFIG_CMD_BOOTZ=y\n@@ -29,7 +28,10 @@ CONFIG_ENV_OVERWRITE=y\n CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n CONFIG_DM=y\n # CONFIG_MMC is not set\n+CONFIG_DM_ETH=y\n CONFIG_E1000=y\n+CONFIG_DM_PCI=y\n+CONFIG_PCI_MPC85XX=y\n CONFIG_DM_SERIAL=y\n CONFIG_SYS_NS16550=y\n CONFIG_ADDR_MAP=y\ndiff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h\nindex feac6ef..b1ee810 100644\n--- a/include/configs/qemu-ppce500.h\n+++ b/include/configs/qemu-ppce500.h\n@@ -13,8 +13,6 @@\n \n #define CONFIG_SYS_RAMBOOT\n \n-#define CONFIG_PCI1\t\t1\t/* PCI controller 1 */\n-#define CONFIG_FSL_PCI_INIT\t\t/* Use common FSL init code */\n #define CONFIG_SYS_PCI_64BIT\t\t/* enable 64-bit PCI resources */\n \n #define CONFIG_ENABLE_36BIT_PHYS\n@@ -73,17 +71,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);\n #define CONFIG_SYS_MONITOR_LEN\t\t(512 * 1024)\n #define CONFIG_SYS_MALLOC_LEN\t\t(4 * 1024 * 1024)\n \n-/*\n- * General PCI\n- * Memory space is mapped 1-1, but I/O space must start from 0.\n- */\n-\n-#ifdef CONFIG_PCI\n-#define CONFIG_PCI_INDIRECT_BRIDGE\n-\n-#define CONFIG_PCI_SCAN_SHOW\t\t/* show pci devices on startup */\n-#endif\t/* CONFIG_PCI */\n-\n #define CONFIG_LBA48\n \n /*\n", "prefixes": [ "v3", "22/38" ] }