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GET /api/patches/1429477/?format=api
{ "id": 1429477, "url": "http://patchwork.ozlabs.org/api/patches/1429477/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210120224444.71840-8-agraf@csgraf.de/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210120224444.71840-8-agraf@csgraf.de>", "list_archive_url": null, "date": "2021-01-20T22:44:40", "name": "[v6,07/11] hvf: Add Apple Silicon support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "074b3f82846981d71ffb49214c1d7ced64e12e73", "submitter": { "id": 65661, "url": "http://patchwork.ozlabs.org/api/people/65661/?format=api", "name": "Alexander Graf", "email": "agraf@csgraf.de" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210120224444.71840-8-agraf@csgraf.de/mbox/", "series": [ { "id": 225556, "url": "http://patchwork.ozlabs.org/api/series/225556/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=225556", "date": "2021-01-20T22:44:33", "name": "hvf: Implement Apple Silicon Support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/225556/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1429477/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1429477/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4DLgsV27fXz9sT6\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 21 Jan 2021 09:57:50 +1100 (AEDT)", "from localhost ([::1]:58860 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1l2MQ8-00062c-7R\n\tfor incoming@patchwork.ozlabs.org; Wed, 20 Jan 2021 17:57:48 -0500", "from eggs.gnu.org ([2001:470:142:3::10]:56626)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <agraf@csgraf.de>)\n id 1l2MDk-0003w8-WE; Wed, 20 Jan 2021 17:45:01 -0500", "from mail.csgraf.de ([188.138.100.120]:45212\n helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <agraf@csgraf.de>)\n id 1l2MDe-0001VL-Hb; Wed, 20 Jan 2021 17:45:00 -0500", "from localhost.localdomain\n (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253])\n by csgraf.de (Postfix) with ESMTPSA id 57B1F390056B;\n Wed, 20 Jan 2021 23:44:50 +0100 (CET)" ], "From": "Alexander Graf <agraf@csgraf.de>", "To": "qemu-devel@nongnu.org", "Subject": "[PATCH v6 07/11] hvf: Add Apple Silicon support", "Date": "Wed, 20 Jan 2021 23:44:40 +0100", "Message-Id": "<20210120224444.71840-8-agraf@csgraf.de>", "X-Mailer": "git-send-email 2.24.3 (Apple Git-128)", "In-Reply-To": "<20210120224444.71840-1-agraf@csgraf.de>", "References": "<20210120224444.71840-1-agraf@csgraf.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de;\n helo=zulu616.server4you.de", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Peter Maydell <peter.maydell@linaro.org>,\n Eduardo Habkost <ehabkost@redhat.com>,\n Richard Henderson <richard.henderson@linaro.org>,\n Cameron Esfahani <dirty@apple.com>, Roman Bolshakov <r.bolshakov@yadro.com>,\n qemu-arm@nongnu.org, Frank Yang <lfy@google.com>,\n Paolo Bonzini <pbonzini@redhat.com>, Peter Collingbourne <pcc@google.com>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "With Apple Silicon available to the masses, it's a good time to add support\nfor driving its virtualization extensions from QEMU.\n\nThis patch adds all necessary architecture specific code to get basic VMs\nworking. It's still pretty raw, but definitely functional.\n\nKnown limitations:\n\n - Vtimer acknowledgement is hacky\n - Should implement more sysregs and fault on invalid ones then\n - WFI handling is missing, need to marry it with vtimer\n\nSigned-off-by: Alexander Graf <agraf@csgraf.de>\nReviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>\n\n---\n\nv1 -> v2:\n\n - Merge vcpu kick function patch\n - Implement WFI handling (allows vCPUs to sleep)\n - Synchronize system registers (fixes OVMF crashes and reboot)\n - Don't always call cpu_synchronize_state()\n - Use more fine grained iothread locking\n - Populate aa64mmfr0 from hardware\n\nv2 -> v3:\n\n - Advance PC on SMC\n - Use cp list interface for sysreg syncs\n - Do not set current_cpu\n - Fix sysreg isread mask\n - Move sysreg handling to functions\n - Remove WFI logic again\n - Revert to global iothread locking\n - Use Hypervisor.h on arm, hv.h does not contain aarch64 definitions\n\nv3 -> v4:\n\n - No longer include Hypervisor.h\n\nv5 -> v6:\n\n - Swap sysreg definition order. This way we're in line with asm outputs.\n---\n MAINTAINERS | 5 +\n accel/hvf/hvf-cpus.c | 14 +\n include/sysemu/hvf_int.h | 9 +-\n target/arm/hvf/hvf.c | 618 +++++++++++++++++++++++++++++++++++++++\n 4 files changed, 645 insertions(+), 1 deletion(-)\n create mode 100644 target/arm/hvf/hvf.c", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex e589ec02e0..8cbb3f37b9 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -442,6 +442,11 @@ F: accel/accel.c\n F: accel/Makefile.objs\n F: accel/stubs/Makefile.objs\n \n+Apple Silicon HVF CPUs\n+M: Alexander Graf <agraf@csgraf.de>\n+S: Maintained\n+F: target/arm/hvf/\n+\n X86 HVF CPUs\n M: Cameron Esfahani <dirty@apple.com>\n M: Roman Bolshakov <r.bolshakov@yadro.com>\ndiff --git a/accel/hvf/hvf-cpus.c b/accel/hvf/hvf-cpus.c\nindex a324da2757..6d70ee742e 100644\n--- a/accel/hvf/hvf-cpus.c\n+++ b/accel/hvf/hvf-cpus.c\n@@ -58,6 +58,10 @@\n #include \"sysemu/runstate.h\"\n #include \"qemu/guest-random.h\"\n \n+#ifdef __aarch64__\n+#define HV_VM_DEFAULT NULL\n+#endif\n+\n /* Memory slots */\n \n struct mac_slot {\n@@ -328,7 +332,11 @@ static int hvf_init_vcpu(CPUState *cpu)\n pthread_sigmask(SIG_BLOCK, NULL, &set);\n sigdelset(&set, SIG_IPI);\n \n+#ifdef __aarch64__\n+ r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL);\n+#else\n r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT);\n+#endif\n cpu->vcpu_dirty = 1;\n assert_hvf_ok(r);\n \n@@ -399,8 +407,14 @@ static void hvf_start_vcpu_thread(CPUState *cpu)\n cpu, QEMU_THREAD_JOINABLE);\n }\n \n+__attribute__((weak)) void hvf_kick_vcpu_thread(CPUState *cpu)\n+{\n+ cpus_kick_thread(cpu);\n+}\n+\n static const CpusAccel hvf_cpus = {\n .create_vcpu_thread = hvf_start_vcpu_thread,\n+ .kick_vcpu_thread = hvf_kick_vcpu_thread,\n \n .synchronize_post_reset = hvf_cpu_synchronize_post_reset,\n .synchronize_post_init = hvf_cpu_synchronize_post_init,\ndiff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h\nindex 9d3cb53e47..c2ac6c8f97 100644\n--- a/include/sysemu/hvf_int.h\n+++ b/include/sysemu/hvf_int.h\n@@ -11,7 +11,12 @@\n #ifndef HVF_INT_H\n #define HVF_INT_H\n \n+#include \"qemu/osdep.h\"\n+#ifdef __aarch64__\n+#include <Hypervisor/Hypervisor.h>\n+#else\n #include <Hypervisor/hv.h>\n+#endif\n \n /* hvf_slot flags */\n #define HVF_SLOT_LOG (1 << 0)\n@@ -44,7 +49,8 @@ struct HVFState {\n extern HVFState *hvf_state;\n \n struct hvf_vcpu_state {\n- int fd;\n+ uint64_t fd;\n+ void *exit;\n };\n \n void assert_hvf_ok(hv_return_t ret);\n@@ -54,5 +60,6 @@ int hvf_arch_init_vcpu(CPUState *cpu);\n void hvf_arch_vcpu_destroy(CPUState *cpu);\n int hvf_vcpu_exec(CPUState *cpu);\n hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t);\n+void hvf_kick_vcpu_thread(CPUState *cpu);\n \n #endif\ndiff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\nnew file mode 100644\nindex 0000000000..8f18efe856\n--- /dev/null\n+++ b/target/arm/hvf/hvf.c\n@@ -0,0 +1,618 @@\n+/*\n+ * QEMU Hypervisor.framework support for Apple Silicon\n+\n+ * Copyright 2020 Alexander Graf <agraf@csgraf.de>\n+ *\n+ * This work is licensed under the terms of the GNU GPL, version 2 or later.\n+ * See the COPYING file in the top-level directory.\n+ *\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu-common.h\"\n+#include \"qemu/error-report.h\"\n+\n+#include \"sysemu/runstate.h\"\n+#include \"sysemu/hvf.h\"\n+#include \"sysemu/hvf_int.h\"\n+#include \"sysemu/hw_accel.h\"\n+\n+#include \"exec/address-spaces.h\"\n+#include \"hw/irq.h\"\n+#include \"qemu/main-loop.h\"\n+#include \"sysemu/accel.h\"\n+#include \"sysemu/cpus.h\"\n+#include \"target/arm/cpu.h\"\n+#include \"target/arm/internals.h\"\n+\n+#define HVF_DEBUG 0\n+#define DPRINTF(...) \\\n+ if (HVF_DEBUG) { \\\n+ fprintf(stderr, \"HVF %s:%d \", __func__, __LINE__); \\\n+ fprintf(stderr, __VA_ARGS__); \\\n+ fprintf(stderr, \"\\n\"); \\\n+ }\n+\n+#define HVF_SYSREG(crn, crm, op0, op1, op2) \\\n+ ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)\n+#define PL1_WRITE_MASK 0x4\n+\n+#define SYSREG(op0, op1, crn, crm, op2) \\\n+ ((op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (crm << 1))\n+#define SYSREG_MASK SYSREG(0x3, 0x7, 0xf, 0xf, 0x7)\n+#define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1)\n+#define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0)\n+\n+#define WFX_IS_WFE (1 << 0)\n+\n+struct hvf_reg_match {\n+ int reg;\n+ uint64_t offset;\n+};\n+\n+static const struct hvf_reg_match hvf_reg_match[] = {\n+ { HV_REG_X0, offsetof(CPUARMState, xregs[0]) },\n+ { HV_REG_X1, offsetof(CPUARMState, xregs[1]) },\n+ { HV_REG_X2, offsetof(CPUARMState, xregs[2]) },\n+ { HV_REG_X3, offsetof(CPUARMState, xregs[3]) },\n+ { HV_REG_X4, offsetof(CPUARMState, xregs[4]) },\n+ { HV_REG_X5, offsetof(CPUARMState, xregs[5]) },\n+ { HV_REG_X6, offsetof(CPUARMState, xregs[6]) },\n+ { HV_REG_X7, offsetof(CPUARMState, xregs[7]) },\n+ { HV_REG_X8, offsetof(CPUARMState, xregs[8]) },\n+ { HV_REG_X9, offsetof(CPUARMState, xregs[9]) },\n+ { HV_REG_X10, offsetof(CPUARMState, xregs[10]) },\n+ { HV_REG_X11, offsetof(CPUARMState, xregs[11]) },\n+ { HV_REG_X12, offsetof(CPUARMState, xregs[12]) },\n+ { HV_REG_X13, offsetof(CPUARMState, xregs[13]) },\n+ { HV_REG_X14, offsetof(CPUARMState, xregs[14]) },\n+ { HV_REG_X15, offsetof(CPUARMState, xregs[15]) },\n+ { HV_REG_X16, offsetof(CPUARMState, xregs[16]) },\n+ { HV_REG_X17, offsetof(CPUARMState, xregs[17]) },\n+ { HV_REG_X18, offsetof(CPUARMState, xregs[18]) },\n+ { HV_REG_X19, offsetof(CPUARMState, xregs[19]) },\n+ { HV_REG_X20, offsetof(CPUARMState, xregs[20]) },\n+ { HV_REG_X21, offsetof(CPUARMState, xregs[21]) },\n+ { HV_REG_X22, offsetof(CPUARMState, xregs[22]) },\n+ { HV_REG_X23, offsetof(CPUARMState, xregs[23]) },\n+ { HV_REG_X24, offsetof(CPUARMState, xregs[24]) },\n+ { HV_REG_X25, offsetof(CPUARMState, xregs[25]) },\n+ { HV_REG_X26, offsetof(CPUARMState, xregs[26]) },\n+ { HV_REG_X27, offsetof(CPUARMState, xregs[27]) },\n+ { HV_REG_X28, offsetof(CPUARMState, xregs[28]) },\n+ { HV_REG_X29, offsetof(CPUARMState, xregs[29]) },\n+ { HV_REG_X30, offsetof(CPUARMState, xregs[30]) },\n+ { HV_REG_PC, offsetof(CPUARMState, pc) },\n+};\n+\n+struct hvf_sreg_match {\n+ int reg;\n+ uint32_t key;\n+};\n+\n+static const struct hvf_sreg_match hvf_sreg_match[] = {\n+ { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) },\n+\n+ { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) },\n+ { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) },\n+ { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) },\n+ { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) },\n+\n+#ifdef SYNC_NO_RAW_REGS\n+ /*\n+ * The registers below are manually synced on init because they are\n+ * marked as NO_RAW. We still list them to make number space sync easier.\n+ */\n+ { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) },\n+ { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) },\n+ { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) },\n+ { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) },\n+#endif\n+ { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) },\n+ { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) },\n+ { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) },\n+ { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) },\n+ { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) },\n+#ifdef SYNC_NO_MMFR0\n+ /* We keep the hardware MMFR0 around. HW limits are there anyway */\n+ { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) },\n+#endif\n+ { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) },\n+ { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },\n+\n+ { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },\n+ { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) },\n+ { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) },\n+ { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) },\n+ { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) },\n+ { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) },\n+\n+ { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) },\n+ { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) },\n+ { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) },\n+ { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) },\n+ { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) },\n+ { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) },\n+ { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) },\n+ { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) },\n+ { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) },\n+ { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) },\n+\n+ { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 1, 0) },\n+ { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) },\n+ { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) },\n+ { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) },\n+ { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) },\n+ { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) },\n+ { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) },\n+ { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) },\n+ { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) },\n+ { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) },\n+ { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) },\n+ { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) },\n+ { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) },\n+ { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) },\n+ { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) },\n+ { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) },\n+ { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) },\n+ { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) },\n+ { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) },\n+ { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) },\n+};\n+\n+int hvf_get_registers(CPUState *cpu)\n+{\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ CPUARMState *env = &arm_cpu->env;\n+ hv_return_t ret;\n+ uint64_t val;\n+ int i;\n+\n+ for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {\n+ ret = hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val);\n+ *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val;\n+ assert_hvf_ok(ret);\n+ }\n+\n+ val = 0;\n+ ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val);\n+ assert_hvf_ok(ret);\n+ vfp_set_fpcr(env, val);\n+\n+ val = 0;\n+ ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val);\n+ assert_hvf_ok(ret);\n+ vfp_set_fpsr(env, val);\n+\n+ ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val);\n+ assert_hvf_ok(ret);\n+ pstate_write(env, val);\n+\n+ for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {\n+ ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &val);\n+ assert_hvf_ok(ret);\n+\n+ arm_cpu->cpreg_values[i] = val;\n+ }\n+ write_list_to_cpustate(arm_cpu);\n+\n+ return 0;\n+}\n+\n+int hvf_put_registers(CPUState *cpu)\n+{\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ CPUARMState *env = &arm_cpu->env;\n+ hv_return_t ret;\n+ uint64_t val;\n+ int i;\n+\n+ for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {\n+ val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset);\n+ ret = hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val);\n+\n+ assert_hvf_ok(ret);\n+ }\n+\n+ ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env));\n+ assert_hvf_ok(ret);\n+\n+ ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env));\n+ assert_hvf_ok(ret);\n+\n+ ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env));\n+ assert_hvf_ok(ret);\n+\n+ write_cpustate_to_list(arm_cpu, false);\n+ for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {\n+ val = arm_cpu->cpreg_values[i];\n+ ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, val);\n+ assert_hvf_ok(ret);\n+ }\n+\n+ return 0;\n+}\n+\n+static void flush_cpu_state(CPUState *cpu)\n+{\n+ if (cpu->vcpu_dirty) {\n+ hvf_put_registers(cpu);\n+ cpu->vcpu_dirty = false;\n+ }\n+}\n+\n+static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val)\n+{\n+ hv_return_t r;\n+\n+ flush_cpu_state(cpu);\n+\n+ if (rt < 31) {\n+ r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val);\n+ assert_hvf_ok(r);\n+ }\n+}\n+\n+static uint64_t hvf_get_reg(CPUState *cpu, int rt)\n+{\n+ uint64_t val = 0;\n+ hv_return_t r;\n+\n+ flush_cpu_state(cpu);\n+\n+ if (rt < 31) {\n+ r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val);\n+ assert_hvf_ok(r);\n+ }\n+\n+ return val;\n+}\n+\n+void hvf_arch_vcpu_destroy(CPUState *cpu)\n+{\n+}\n+\n+int hvf_arch_init_vcpu(CPUState *cpu)\n+{\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ CPUARMState *env = &arm_cpu->env;\n+ uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match);\n+ uint64_t pfr;\n+ hv_return_t ret;\n+ int i;\n+\n+ env->aarch64 = 1;\n+ asm volatile(\"mrs %0, cntfrq_el0\" : \"=r\"(arm_cpu->gt_cntfrq_hz));\n+\n+ /* Allocate enough space for our sysreg sync */\n+ arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes,\n+ sregs_match_len);\n+ arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values,\n+ sregs_match_len);\n+ arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t,\n+ arm_cpu->cpreg_vmstate_indexes,\n+ sregs_match_len);\n+ arm_cpu->cpreg_vmstate_values = g_renew(uint64_t,\n+ arm_cpu->cpreg_vmstate_values,\n+ sregs_match_len);\n+\n+ memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t));\n+ arm_cpu->cpreg_array_len = sregs_match_len;\n+ arm_cpu->cpreg_vmstate_array_len = sregs_match_len;\n+\n+ /* Populate cp list for all known sysregs */\n+ for (i = 0; i < sregs_match_len; i++) {\n+ const ARMCPRegInfo *ri;\n+\n+ arm_cpu->cpreg_indexes[i] = cpreg_to_kvm_id(hvf_sreg_match[i].key);\n+\n+ ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match[i].key);\n+ if (ri) {\n+ assert(!(ri->type & ARM_CP_NO_RAW));\n+ }\n+ }\n+ write_cpustate_to_list(arm_cpu, false);\n+\n+ /* Set CP_NO_RAW system registers on init */\n+ ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1,\n+ arm_cpu->midr);\n+ assert_hvf_ok(ret);\n+\n+ ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1,\n+ arm_cpu->mp_affinity);\n+ assert_hvf_ok(ret);\n+\n+ ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr);\n+ assert_hvf_ok(ret);\n+ pfr |= env->gicv3state ? (1 << 24) : 0;\n+ ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr);\n+ assert_hvf_ok(ret);\n+\n+ /* We're limited to underlying hardware caps, override internal versions */\n+ ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,\n+ &arm_cpu->isar.id_aa64mmfr0);\n+ assert_hvf_ok(ret);\n+\n+ return 0;\n+}\n+\n+void hvf_kick_vcpu_thread(CPUState *cpu)\n+{\n+ hv_vcpus_exit(&cpu->hvf->fd, 1);\n+}\n+\n+static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg)\n+{\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ uint64_t val = 0;\n+\n+ switch (reg) {\n+ case SYSREG_CNTPCT_EL0:\n+ val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /\n+ gt_cntfrq_period_ns(arm_cpu);\n+ break;\n+ case SYSREG_PMCCNTR_EL0:\n+ val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);\n+ break;\n+ default:\n+ DPRINTF(\"unhandled sysreg read %08x (op0=%d op1=%d op2=%d \"\n+ \"crn=%d crm=%d)\", reg, (reg >> 20) & 0x3,\n+ (reg >> 14) & 0x7, (reg >> 17) & 0x7,\n+ (reg >> 10) & 0xf, (reg >> 1) & 0xf);\n+ break;\n+ }\n+\n+ return val;\n+}\n+\n+static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)\n+{\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+\n+ switch (reg) {\n+ case SYSREG_CNTPCT_EL0:\n+ break;\n+ default:\n+ DPRINTF(\"unhandled sysreg write %08x\", reg);\n+ break;\n+ }\n+}\n+\n+static int hvf_inject_interrupts(CPUState *cpu)\n+{\n+ if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) {\n+ DPRINTF(\"injecting FIQ\");\n+ hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ, true);\n+ }\n+\n+ if (cpu->interrupt_request & CPU_INTERRUPT_HARD) {\n+ DPRINTF(\"injecting IRQ\");\n+ hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ, true);\n+ }\n+\n+ return 0;\n+}\n+\n+int hvf_vcpu_exec(CPUState *cpu)\n+{\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ CPUARMState *env = &arm_cpu->env;\n+ hv_vcpu_exit_t *hvf_exit = cpu->hvf->exit;\n+ hv_return_t r;\n+\n+ while (1) {\n+ bool advance_pc = false;\n+\n+ qemu_wait_io_event_common(cpu);\n+ flush_cpu_state(cpu);\n+\n+ if (hvf_inject_interrupts(cpu)) {\n+ return EXCP_INTERRUPT;\n+ }\n+\n+ if (cpu->halted) {\n+ return EXCP_HLT;\n+ }\n+\n+ qemu_mutex_unlock_iothread();\n+ assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd));\n+\n+ /* handle VMEXIT */\n+ uint64_t exit_reason = hvf_exit->reason;\n+ uint64_t syndrome = hvf_exit->exception.syndrome;\n+ uint32_t ec = syn_get_ec(syndrome);\n+\n+ qemu_mutex_lock_iothread();\n+ switch (exit_reason) {\n+ case HV_EXIT_REASON_EXCEPTION:\n+ /* This is the main one, handle below. */\n+ break;\n+ case HV_EXIT_REASON_VTIMER_ACTIVATED:\n+ qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1);\n+ continue;\n+ case HV_EXIT_REASON_CANCELED:\n+ /* we got kicked, no exit to process */\n+ continue;\n+ default:\n+ assert(0);\n+ }\n+\n+ switch (ec) {\n+ case EC_DATAABORT: {\n+ bool isv = syndrome & ARM_EL_ISV;\n+ bool iswrite = (syndrome >> 6) & 1;\n+ bool s1ptw = (syndrome >> 7) & 1;\n+ uint32_t sas = (syndrome >> 22) & 3;\n+ uint32_t len = 1 << sas;\n+ uint32_t srt = (syndrome >> 16) & 0x1f;\n+ uint64_t val = 0;\n+\n+ DPRINTF(\"data abort: [pc=0x%llx va=0x%016llx pa=0x%016llx isv=%x \"\n+ \"iswrite=%x s1ptw=%x len=%d srt=%d]\\n\",\n+ env->pc, hvf_exit->exception.virtual_address,\n+ hvf_exit->exception.physical_address, isv, iswrite,\n+ s1ptw, len, srt);\n+\n+ assert(isv);\n+\n+ if (iswrite) {\n+ val = hvf_get_reg(cpu, srt);\n+ address_space_write(&address_space_memory,\n+ hvf_exit->exception.physical_address,\n+ MEMTXATTRS_UNSPECIFIED, &val, len);\n+\n+ /*\n+ * We do not have a callback to see if the timer is out of\n+ * pending state. That means every MMIO write could\n+ * potentially be an EOI ends the vtimer. Until we get an\n+ * actual callback, let's just see if the timer is still\n+ * pending on every possible toggle point.\n+ */\n+ qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 0);\n+ hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false);\n+ } else {\n+ address_space_read(&address_space_memory,\n+ hvf_exit->exception.physical_address,\n+ MEMTXATTRS_UNSPECIFIED, &val, len);\n+ hvf_set_reg(cpu, srt, val);\n+ }\n+\n+ advance_pc = true;\n+ break;\n+ }\n+ case EC_SYSTEMREGISTERTRAP: {\n+ bool isread = (syndrome >> 0) & 1;\n+ uint32_t rt = (syndrome >> 5) & 0x1f;\n+ uint32_t reg = syndrome & SYSREG_MASK;\n+ uint64_t val = 0;\n+\n+ DPRINTF(\"sysreg %s operation reg=%08x (op0=%d op1=%d op2=%d \"\n+ \"crn=%d crm=%d)\", (isread) ? \"read\" : \"write\",\n+ reg, (reg >> 20) & 0x3,\n+ (reg >> 14) & 0x7, (reg >> 17) & 0x7,\n+ (reg >> 10) & 0xf, (reg >> 1) & 0xf);\n+\n+ if (isread) {\n+ hvf_set_reg(cpu, rt, hvf_sysreg_read(cpu, reg));\n+ } else {\n+ val = hvf_get_reg(cpu, rt);\n+ hvf_sysreg_write(cpu, reg, val);\n+ }\n+\n+ advance_pc = true;\n+ break;\n+ }\n+ case EC_WFX_TRAP:\n+ advance_pc = true;\n+ break;\n+ case EC_AA64_HVC:\n+ cpu_synchronize_state(cpu);\n+ if (arm_is_psci_call(arm_cpu, EXCP_HVC)) {\n+ arm_handle_psci_call(arm_cpu);\n+ } else {\n+ DPRINTF(\"unknown HVC! %016llx\", env->xregs[0]);\n+ env->xregs[0] = -1;\n+ }\n+ break;\n+ case EC_AA64_SMC:\n+ cpu_synchronize_state(cpu);\n+ if (arm_is_psci_call(arm_cpu, EXCP_SMC)) {\n+ arm_handle_psci_call(arm_cpu);\n+ } else {\n+ DPRINTF(\"unknown SMC! %016llx\", env->xregs[0]);\n+ env->xregs[0] = -1;\n+ }\n+ env->pc += 4;\n+ break;\n+ default:\n+ cpu_synchronize_state(cpu);\n+ DPRINTF(\"exit: %llx [ec=0x%x pc=0x%llx]\", syndrome, ec, env->pc);\n+ error_report(\"%llx: unhandled exit %llx\", env->pc, exit_reason);\n+ }\n+\n+ if (advance_pc) {\n+ uint64_t pc;\n+\n+ flush_cpu_state(cpu);\n+\n+ r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc);\n+ assert_hvf_ok(r);\n+ pc += 4;\n+ r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc);\n+ assert_hvf_ok(r);\n+ }\n+ }\n+}\n", "prefixes": [ "v6", "07/11" ] }