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GET /api/patches/1429475/?format=api
{ "id": 1429475, "url": "http://patchwork.ozlabs.org/api/patches/1429475/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210120224444.71840-11-agraf@csgraf.de/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210120224444.71840-11-agraf@csgraf.de>", "list_archive_url": null, "date": "2021-01-20T22:44:43", "name": "[v6,10/11] hvf: arm: Add support for GICv3", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8935600706972bcc8aa3d5376f2d59aec182651f", "submitter": { "id": 65661, "url": "http://patchwork.ozlabs.org/api/people/65661/?format=api", "name": "Alexander Graf", "email": "agraf@csgraf.de" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20210120224444.71840-11-agraf@csgraf.de/mbox/", "series": [ { "id": 225556, "url": "http://patchwork.ozlabs.org/api/series/225556/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=225556", "date": "2021-01-20T22:44:33", "name": "hvf: Implement Apple Silicon Support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/225556/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1429475/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1429475/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4DLgqm6zY7z9sT6\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 21 Jan 2021 09:56:20 +1100 (AEDT)", "from localhost ([::1]:56896 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1l2MOg-00057X-G6\n\tfor incoming@patchwork.ozlabs.org; Wed, 20 Jan 2021 17:56:18 -0500", "from eggs.gnu.org ([2001:470:142:3::10]:56746)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <agraf@csgraf.de>)\n id 1l2ME5-00049c-2k; Wed, 20 Jan 2021 17:45:21 -0500", "from mail.csgraf.de ([188.138.100.120]:45228\n helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <agraf@csgraf.de>)\n id 1l2ME0-0001WT-0A; Wed, 20 Jan 2021 17:45:20 -0500", "from localhost.localdomain\n (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253])\n by csgraf.de (Postfix) with ESMTPSA id 73BAD3900586;\n Wed, 20 Jan 2021 23:44:52 +0100 (CET)" ], "From": "Alexander Graf <agraf@csgraf.de>", "To": "qemu-devel@nongnu.org", "Subject": "[PATCH v6 10/11] hvf: arm: Add support for GICv3", "Date": "Wed, 20 Jan 2021 23:44:43 +0100", "Message-Id": "<20210120224444.71840-11-agraf@csgraf.de>", "X-Mailer": "git-send-email 2.24.3 (Apple Git-128)", "In-Reply-To": "<20210120224444.71840-1-agraf@csgraf.de>", "References": "<20210120224444.71840-1-agraf@csgraf.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de;\n helo=zulu616.server4you.de", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Peter Maydell <peter.maydell@linaro.org>,\n Eduardo Habkost <ehabkost@redhat.com>,\n Richard Henderson <richard.henderson@linaro.org>,\n Cameron Esfahani <dirty@apple.com>, Roman Bolshakov <r.bolshakov@yadro.com>,\n qemu-arm@nongnu.org, Frank Yang <lfy@google.com>,\n Paolo Bonzini <pbonzini@redhat.com>, Peter Collingbourne <pcc@google.com>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "We currently only support GICv2 emulation. To also support GICv3, we will\nneed to pass a few system registers into their respective handler functions.\n\nThis patch adds handling for all of the required system registers, so that\nwe can run with more than 8 vCPUs.\n\nSigned-off-by: Alexander Graf <agraf@csgraf.de>\nAcked-by: Roman Bolshakov <r.bolshakov@yadro.com>\n\n---\n\nv5 -> v6:\n\n - Adapt to new SYSREG() ordering\n---\n target/arm/hvf/hvf.c | 141 +++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 141 insertions(+)", "diff": "diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\nindex f0850ab14a..98bd6712c0 100644\n--- a/target/arm/hvf/hvf.c\n+++ b/target/arm/hvf/hvf.c\n@@ -22,6 +22,7 @@\n \n #include \"exec/address-spaces.h\"\n #include \"hw/irq.h\"\n+#include \"hw/intc/gicv3_internal.h\"\n #include \"qemu/main-loop.h\"\n #include \"sysemu/accel.h\"\n #include \"sysemu/cpus.h\"\n@@ -46,6 +47,33 @@\n #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1)\n #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0)\n \n+#define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4)\n+#define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5)\n+#define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6)\n+#define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7)\n+#define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0)\n+#define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1)\n+#define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2)\n+#define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3)\n+#define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6)\n+#define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3)\n+#define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3)\n+#define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4)\n+#define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1)\n+#define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1)\n+#define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1)\n+#define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2)\n+#define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2)\n+#define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0)\n+#define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0)\n+#define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6)\n+#define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7)\n+#define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0)\n+#define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3)\n+#define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7)\n+#define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5)\n+#define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5)\n+\n #define WFX_IS_WFE (1 << 0)\n \n struct hvf_reg_match {\n@@ -418,6 +446,38 @@ void hvf_kick_vcpu_thread(CPUState *cpu)\n hv_vcpus_exit(&cpu->hvf->fd, 1);\n }\n \n+static uint32_t hvf_reg2cp_reg(uint32_t reg)\n+{\n+ return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,\n+ (reg >> 10) & 0xf,\n+ (reg >> 1) & 0xf,\n+ (reg >> 20) & 0x3,\n+ (reg >> 14) & 0x7,\n+ (reg >> 17) & 0x7);\n+}\n+\n+static uint64_t hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg)\n+{\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ CPUARMState *env = &arm_cpu->env;\n+ const ARMCPRegInfo *ri;\n+ uint64_t val = 0;\n+\n+ ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));\n+ if (ri) {\n+ if (ri->type & ARM_CP_CONST) {\n+ val = ri->resetvalue;\n+ } else if (ri->readfn) {\n+ val = ri->readfn(env, ri);\n+ } else {\n+ val = CPREG_FIELD64(env, ri);\n+ }\n+ DPRINTF(\"vgic read from %s [val=%016llx]\", ri->name, val);\n+ }\n+\n+ return val;\n+}\n+\n static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg)\n {\n ARMCPU *arm_cpu = ARM_CPU(cpu);\n@@ -431,6 +491,39 @@ static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg)\n case SYSREG_PMCCNTR_EL0:\n val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);\n break;\n+ case SYSREG_ICC_AP0R0_EL1:\n+ case SYSREG_ICC_AP0R1_EL1:\n+ case SYSREG_ICC_AP0R2_EL1:\n+ case SYSREG_ICC_AP0R3_EL1:\n+ case SYSREG_ICC_AP1R0_EL1:\n+ case SYSREG_ICC_AP1R1_EL1:\n+ case SYSREG_ICC_AP1R2_EL1:\n+ case SYSREG_ICC_AP1R3_EL1:\n+ case SYSREG_ICC_ASGI1R_EL1:\n+ case SYSREG_ICC_BPR0_EL1:\n+ case SYSREG_ICC_BPR1_EL1:\n+ case SYSREG_ICC_DIR_EL1:\n+ case SYSREG_ICC_EOIR0_EL1:\n+ case SYSREG_ICC_EOIR1_EL1:\n+ case SYSREG_ICC_HPPIR0_EL1:\n+ case SYSREG_ICC_HPPIR1_EL1:\n+ case SYSREG_ICC_IAR0_EL1:\n+ case SYSREG_ICC_IAR1_EL1:\n+ case SYSREG_ICC_IGRPEN0_EL1:\n+ case SYSREG_ICC_IGRPEN1_EL1:\n+ case SYSREG_ICC_PMR_EL1:\n+ case SYSREG_ICC_SGI0R_EL1:\n+ case SYSREG_ICC_SGI1R_EL1:\n+ case SYSREG_ICC_SRE_EL1:\n+ val = hvf_sysreg_read_cp(cpu, reg);\n+ break;\n+ case SYSREG_ICC_CTLR_EL1:\n+ val = hvf_sysreg_read_cp(cpu, reg);\n+\n+ /* AP0R registers above 0 don't trap, expose less PRIs to fit */\n+ val &= ~ICC_CTLR_EL1_PRIBITS_MASK;\n+ val |= 4 << ICC_CTLR_EL1_PRIBITS_SHIFT;\n+ break;\n default:\n DPRINTF(\"unhandled sysreg read %08x (op0=%d op1=%d op2=%d \"\n \"crn=%d crm=%d)\", reg, (reg >> 20) & 0x3,\n@@ -442,6 +535,24 @@ static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg)\n return val;\n }\n \n+static void hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val)\n+{\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ CPUARMState *env = &arm_cpu->env;\n+ const ARMCPRegInfo *ri;\n+\n+ ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));\n+\n+ if (ri) {\n+ if (ri->writefn) {\n+ ri->writefn(env, ri, val);\n+ } else {\n+ CPREG_FIELD64(env, ri) = val;\n+ }\n+ DPRINTF(\"vgic write to %s [val=%016llx]\", ri->name, val);\n+ }\n+}\n+\n static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)\n {\n ARMCPU *arm_cpu = ARM_CPU(cpu);\n@@ -449,6 +560,36 @@ static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)\n switch (reg) {\n case SYSREG_CNTPCT_EL0:\n break;\n+ case SYSREG_ICC_AP0R0_EL1:\n+ case SYSREG_ICC_AP0R1_EL1:\n+ case SYSREG_ICC_AP0R2_EL1:\n+ case SYSREG_ICC_AP0R3_EL1:\n+ case SYSREG_ICC_AP1R0_EL1:\n+ case SYSREG_ICC_AP1R1_EL1:\n+ case SYSREG_ICC_AP1R2_EL1:\n+ case SYSREG_ICC_AP1R3_EL1:\n+ case SYSREG_ICC_ASGI1R_EL1:\n+ case SYSREG_ICC_BPR0_EL1:\n+ case SYSREG_ICC_BPR1_EL1:\n+ case SYSREG_ICC_CTLR_EL1:\n+ case SYSREG_ICC_DIR_EL1:\n+ case SYSREG_ICC_HPPIR0_EL1:\n+ case SYSREG_ICC_HPPIR1_EL1:\n+ case SYSREG_ICC_IAR0_EL1:\n+ case SYSREG_ICC_IAR1_EL1:\n+ case SYSREG_ICC_IGRPEN0_EL1:\n+ case SYSREG_ICC_IGRPEN1_EL1:\n+ case SYSREG_ICC_PMR_EL1:\n+ case SYSREG_ICC_SGI0R_EL1:\n+ case SYSREG_ICC_SGI1R_EL1:\n+ case SYSREG_ICC_SRE_EL1:\n+ hvf_sysreg_write_cp(cpu, reg, val);\n+ break;\n+ case SYSREG_ICC_EOIR0_EL1:\n+ case SYSREG_ICC_EOIR1_EL1:\n+ hvf_sysreg_write_cp(cpu, reg, val);\n+ qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 0);\n+ hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false);\n default:\n DPRINTF(\"unhandled sysreg write %08x\", reg);\n break;\n", "prefixes": [ "v6", "10/11" ] }