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GET /api/patches/1421832/?format=api
{ "id": 1421832, "url": "http://patchwork.ozlabs.org/api/patches/1421832/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20210103092633.36226-17-jernej.skrabec@siol.net/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210103092633.36226-17-jernej.skrabec@siol.net>", "list_archive_url": null, "date": "2021-01-03T09:26:32", "name": "[16/17] clk: sunxi: Add support for H616 clocks", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "4e896449fbe5c07e55c73a2ad0d8226839439220", "submitter": { "id": 70601, "url": "http://patchwork.ozlabs.org/api/people/70601/?format=api", "name": "Jernej Škrabec", "email": "jernej.skrabec@siol.net" }, "delegate": { "id": 114289, "url": "http://patchwork.ozlabs.org/api/users/114289/?format=api", "username": "apritzel", "first_name": "Andre", "last_name": "Przywara", "email": "andre.przywara@arm.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20210103092633.36226-17-jernej.skrabec@siol.net/mbox/", "series": [ { "id": 222511, "url": "http://patchwork.ozlabs.org/api/series/222511/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=222511", "date": "2021-01-03T09:26:16", "name": "sunxi: Introduce H616 support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/222511/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1421832/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1421832/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=fail (p=none dis=none) header.from=siol.net", "phobos.denx.de;\n dmarc=fail (p=none dis=none) header.from=siol.net", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=siol.net", "phobos.denx.de;\n spf=pass smtp.mailfrom=jernej.skrabec@siol.net" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4D7tlC3TSHz9sVn\n\tfor <incoming@patchwork.ozlabs.org>; Sun, 3 Jan 2021 20:29:59 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 6218C826C3;\n\tSun, 3 Jan 2021 10:27:31 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 83B26826BE; Sun, 3 Jan 2021 10:27:29 +0100 (CET)", "from mail.siol.net (mailoutvs41.siol.net [185.57.226.232])\n (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 252C6826B1\n for <u-boot@lists.denx.de>; Sun, 3 Jan 2021 10:27:26 +0100 (CET)", "from localhost (localhost [127.0.0.1])\n by mail.siol.net (Zimbra) with ESMTP id D1E21522DF7;\n Sun, 3 Jan 2021 10:27:25 +0100 (CET)", "from mail.siol.net ([127.0.0.1])\n by localhost (psrvmta12.zcs-production.pri [127.0.0.1]) (amavisd-new,\n port 10032)\n with ESMTP id INevboSyIqVh; Sun, 3 Jan 2021 10:27:25 +0100 (CET)", "from mail.siol.net (localhost [127.0.0.1])\n by mail.siol.net (Zimbra) with ESMTPS id 77BC6522DE5;\n Sun, 3 Jan 2021 10:27:25 +0100 (CET)", "from localhost.localdomain (89-212-178-211.dynamic.t-2.net\n [89.212.178.211]) (Authenticated sender: 031275009)\n by mail.siol.net (Zimbra) with ESMTPSA id 3F404522DE2;\n Sun, 3 Jan 2021 10:27:23 +0100 (CET)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Jernej Skrabec <jernej.skrabec@siol.net>", "To": "jagan@amarulasolutions.com,\n\tandre.przywara@arm.com", "Cc": "hdegoede@redhat.com, jernej.skrabec@siol.net, lukma@denx.de, hs@denx.de,\n peng.fan@nxp.com, joe.hershberger@ni.com, jh80.chung@samsung.com,\n u-boot@lists.denx.de, linux-sunxi@googlegroups.com", "Subject": "[PATCH 16/17] clk: sunxi: Add support for H616 clocks", "Date": "Sun, 3 Jan 2021 10:26:32 +0100", "Message-Id": "<20210103092633.36226-17-jernej.skrabec@siol.net>", "X-Mailer": "git-send-email 2.30.0", "In-Reply-To": "<20210103092633.36226-1-jernej.skrabec@siol.net>", "References": "<20210103092633.36226-1-jernej.skrabec@siol.net>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "quoted-printable", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "This commit introduces DM H616 clock driver.\n\nSigned-off-by: Jernej Skrabec <jernej.skrabec@siol.net>\n---\n drivers/clk/sunxi/Kconfig | 7 ++\n drivers/clk/sunxi/Makefile | 1 +\n drivers/clk/sunxi/clk_h616.c | 120 +++++++++++++++++++++++++++++++++++\n 3 files changed, 128 insertions(+)\n create mode 100644 drivers/clk/sunxi/clk_h616.c", "diff": "diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig\nindex 5ff101b99305..bf084fa7a84a 100644\n--- a/drivers/clk/sunxi/Kconfig\n+++ b/drivers/clk/sunxi/Kconfig\n@@ -79,6 +79,13 @@ config CLK_SUN50I_H6\n \t This enables common clock driver support for platforms based\n \t on Allwinner H6 SoC.\n \n+config CLK_SUN50I_H616\n+\tbool \"Clock driver for Allwinner H616\"\n+\tdefault MACH_SUN50I_H616\n+\thelp\n+\t This enables common clock driver support for platforms based\n+\t on Allwinner H616 SoC.\n+\n config CLK_SUN50I_A64\n \tbool \"Clock driver for Allwinner A64\"\n \tdefault MACH_SUN50I\ndiff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile\nindex 36fb2aeb56c5..0dfc0593fb1c 100644\n--- a/drivers/clk/sunxi/Makefile\n+++ b/drivers/clk/sunxi/Makefile\n@@ -16,4 +16,5 @@ obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o\n obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o\n obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o\n obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o\n+obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o\n obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o\ndiff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c\nnew file mode 100644\nindex 000000000000..e2e3a5c78c95\n--- /dev/null\n+++ b/drivers/clk/sunxi/clk_h616.c\n@@ -0,0 +1,120 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@siol.net>\n+ */\n+\n+#include <common.h>\n+#include <clk-uclass.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <asm/arch/ccu.h>\n+#include <dt-bindings/clock/sun50i-h616-ccu.h>\n+#include <dt-bindings/reset/sun50i-h616-ccu.h>\n+#include <linux/bitops.h>\n+\n+static struct ccu_clk_gate h616_gates[] = {\n+\t[CLK_BUS_MMC0]\t\t= GATE(0x84c, BIT(0)),\n+\t[CLK_BUS_MMC1]\t\t= GATE(0x84c, BIT(1)),\n+\t[CLK_BUS_MMC2]\t\t= GATE(0x84c, BIT(2)),\n+\n+\t[CLK_BUS_UART0]\t\t= GATE(0x90c, BIT(0)),\n+\t[CLK_BUS_UART1]\t\t= GATE(0x90c, BIT(1)),\n+\t[CLK_BUS_UART2]\t\t= GATE(0x90c, BIT(2)),\n+\t[CLK_BUS_UART3]\t\t= GATE(0x90c, BIT(3)),\n+\t[CLK_BUS_UART4]\t\t= GATE(0x90c, BIT(4)),\n+\t[CLK_BUS_UART5]\t\t= GATE(0x90c, BIT(5)),\n+\n+\t[CLK_SPI0]\t\t= GATE(0x940, BIT(31)),\n+\t[CLK_SPI1]\t\t= GATE(0x944, BIT(31)),\n+\n+\t[CLK_BUS_SPI0]\t\t= GATE(0x96c, BIT(0)),\n+\t[CLK_BUS_SPI1]\t\t= GATE(0x96c, BIT(1)),\n+\n+\t[CLK_BUS_EMAC0]\t\t= GATE(0x97c, BIT(0)),\n+\t[CLK_BUS_EMAC1]\t\t= GATE(0x97c, BIT(1)),\n+\n+\t[CLK_USB_PHY0]\t\t= GATE(0xa70, BIT(29)),\n+\t[CLK_USB_OHCI0]\t\t= GATE(0xa70, BIT(31)),\n+\n+\t[CLK_USB_PHY1]\t\t= GATE(0xa74, BIT(29)),\n+\t[CLK_USB_OHCI1]\t\t= GATE(0xa74, BIT(31)),\n+\n+\t[CLK_USB_PHY2]\t\t= GATE(0xa78, BIT(29)),\n+\t[CLK_USB_OHCI2]\t\t= GATE(0xa78, BIT(31)),\n+\n+\t[CLK_USB_PHY3]\t\t= GATE(0xa7c, BIT(29)),\n+\t[CLK_USB_OHCI3]\t\t= GATE(0xa7c, BIT(31)),\n+\n+\t[CLK_BUS_OHCI0]\t\t= GATE(0xa8c, BIT(0)),\n+\t[CLK_BUS_OHCI1]\t\t= GATE(0xa8c, BIT(1)),\n+\t[CLK_BUS_OHCI2]\t\t= GATE(0xa8c, BIT(2)),\n+\t[CLK_BUS_OHCI3]\t\t= GATE(0xa8c, BIT(3)),\n+\t[CLK_BUS_EHCI0]\t\t= GATE(0xa8c, BIT(4)),\n+\t[CLK_BUS_EHCI1]\t\t= GATE(0xa8c, BIT(5)),\n+\t[CLK_BUS_EHCI2]\t\t= GATE(0xa8c, BIT(6)),\n+\t[CLK_BUS_EHCI3]\t\t= GATE(0xa8c, BIT(7)),\n+\t[CLK_BUS_OTG]\t\t= GATE(0xa8c, BIT(8)),\n+};\n+\n+static struct ccu_reset h616_resets[] = {\n+\t[RST_BUS_MMC0]\t\t= RESET(0x84c, BIT(16)),\n+\t[RST_BUS_MMC1]\t\t= RESET(0x84c, BIT(17)),\n+\t[RST_BUS_MMC2]\t\t= RESET(0x84c, BIT(18)),\n+\n+\t[RST_BUS_UART0]\t\t= RESET(0x90c, BIT(16)),\n+\t[RST_BUS_UART1]\t\t= RESET(0x90c, BIT(17)),\n+\t[RST_BUS_UART2]\t\t= RESET(0x90c, BIT(18)),\n+\t[RST_BUS_UART3]\t\t= RESET(0x90c, BIT(19)),\n+\t[RST_BUS_UART4]\t\t= RESET(0x90c, BIT(20)),\n+\t[RST_BUS_UART5]\t\t= RESET(0x90c, BIT(21)),\n+\n+\t[RST_BUS_SPI0]\t\t= RESET(0x96c, BIT(16)),\n+\t[RST_BUS_SPI1]\t\t= RESET(0x96c, BIT(17)),\n+\n+\t[RST_BUS_EMAC0]\t\t= RESET(0x97c, BIT(16)),\n+\t[RST_BUS_EMAC1]\t\t= RESET(0x97c, BIT(17)),\n+\n+\t[RST_USB_PHY0]\t\t= RESET(0xa70, BIT(30)),\n+\n+\t[RST_USB_PHY1]\t\t= RESET(0xa74, BIT(30)),\n+\n+\t[RST_USB_PHY2]\t\t= RESET(0xa78, BIT(30)),\n+\n+\t[RST_USB_PHY3]\t\t= RESET(0xa7c, BIT(30)),\n+\n+\t[RST_BUS_OHCI0]\t\t= RESET(0xa8c, BIT(16)),\n+\t[RST_BUS_OHCI1]\t\t= RESET(0xa8c, BIT(17)),\n+\t[RST_BUS_OHCI2]\t\t= RESET(0xa8c, BIT(18)),\n+\t[RST_BUS_OHCI3]\t\t= RESET(0xa8c, BIT(19)),\n+\t[RST_BUS_EHCI0]\t\t= RESET(0xa8c, BIT(20)),\n+\t[RST_BUS_EHCI1]\t\t= RESET(0xa8c, BIT(21)),\n+\t[RST_BUS_EHCI2]\t\t= RESET(0xa8c, BIT(22)),\n+\t[RST_BUS_EHCI3]\t\t= RESET(0xa8c, BIT(23)),\n+\t[RST_BUS_OTG]\t\t= RESET(0xa8c, BIT(24)),\n+};\n+\n+static const struct ccu_desc h616_ccu_desc = {\n+\t.gates = h616_gates,\n+\t.resets = h616_resets,\n+};\n+\n+static int h616_clk_bind(struct udevice *dev)\n+{\n+\treturn sunxi_reset_bind(dev, ARRAY_SIZE(h616_resets));\n+}\n+\n+static const struct udevice_id h616_ccu_ids[] = {\n+\t{ .compatible = \"allwinner,sun50i-h616-ccu\",\n+\t .data = (ulong)&h616_ccu_desc },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(clk_sun50i_h616) = {\n+\t.name\t\t= \"sun50i_h616_ccu\",\n+\t.id\t\t= UCLASS_CLK,\n+\t.of_match\t= h616_ccu_ids,\n+\t.priv_auto_alloc_size\t= sizeof(struct ccu_priv),\n+\t.ops\t\t= &sunxi_clk_ops,\n+\t.probe\t\t= sunxi_clk_probe,\n+\t.bind\t\t= h616_clk_bind,\n+};\n", "prefixes": [ "16/17" ] }