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{
    "id": 1421831,
    "url": "http://patchwork.ozlabs.org/api/patches/1421831/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20210103092633.36226-15-jernej.skrabec@siol.net/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20210103092633.36226-15-jernej.skrabec@siol.net>",
    "list_archive_url": null,
    "date": "2021-01-03T09:26:30",
    "name": "[14/17] arm: sunxi: add initial H616 DTSI and headers",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "cad91eb80459ac8712d51462dd0dc88ac2ebb3c7",
    "submitter": {
        "id": 70601,
        "url": "http://patchwork.ozlabs.org/api/people/70601/?format=api",
        "name": "Jernej Škrabec",
        "email": "jernej.skrabec@siol.net"
    },
    "delegate": {
        "id": 114289,
        "url": "http://patchwork.ozlabs.org/api/users/114289/?format=api",
        "username": "apritzel",
        "first_name": "Andre",
        "last_name": "Przywara",
        "email": "andre.przywara@arm.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20210103092633.36226-15-jernej.skrabec@siol.net/mbox/",
    "series": [
        {
            "id": 222511,
            "url": "http://patchwork.ozlabs.org/api/series/222511/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=222511",
            "date": "2021-01-03T09:26:16",
            "name": "sunxi: Introduce H616 support",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/222511/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1421831/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1421831/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Jernej Skrabec <jernej.skrabec@siol.net>",
        "To": "jagan@amarulasolutions.com,\n\tandre.przywara@arm.com",
        "Cc": "hdegoede@redhat.com, jernej.skrabec@siol.net, lukma@denx.de, hs@denx.de,\n peng.fan@nxp.com, joe.hershberger@ni.com, jh80.chung@samsung.com,\n u-boot@lists.denx.de, linux-sunxi@googlegroups.com",
        "Subject": "[PATCH 14/17] arm: sunxi: add initial H616 DTSI and headers",
        "Date": "Sun,  3 Jan 2021 10:26:30 +0100",
        "Message-Id": "<20210103092633.36226-15-jernej.skrabec@siol.net>",
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    "content": "This commit introduces H616 DTSI file and dt-bindings headers needed for\ndevice tree files.\n\nFiles are taken from initial Linux H616 support submission with minor\nchange - emac0 fallback has H6 compatible instead of A64, otherwise\nnetwork doesn't work. H616 DTSI is not merged upstream yet.\n\nSigned-off-by: Jernej Skrabec <jernej.skrabec@siol.net>\n---\n arch/arm/dts/sun50i-h616.dtsi               | 716 ++++++++++++++++++++\n include/dt-bindings/clock/sun50i-h616-ccu.h | 115 ++++\n include/dt-bindings/reset/sun50i-h616-ccu.h |  70 ++\n 3 files changed, 901 insertions(+)\n create mode 100644 arch/arm/dts/sun50i-h616.dtsi\n create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h\n create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h",
    "diff": "diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi\nnew file mode 100644\nindex 000000000000..d416e9a3d3e6\n--- /dev/null\n+++ b/arch/arm/dts/sun50i-h616.dtsi\n@@ -0,0 +1,716 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+// Copyright (C) 2020 Arm Ltd.\n+// based on the H6 dtsi, which is:\n+//   Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>\n+\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/clock/sun50i-h616-ccu.h>\n+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>\n+#include <dt-bindings/reset/sun50i-h616-ccu.h>\n+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>\n+\n+/ {\n+\tinterrupt-parent = <&gic>;\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu0: cpu@0 {\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tclocks = <&ccu CLK_CPUX>;\n+\t\t};\n+\n+\t\tcpu1: cpu@1 {\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <1>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tclocks = <&ccu CLK_CPUX>;\n+\t\t};\n+\n+\t\tcpu2: cpu@2 {\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <2>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tclocks = <&ccu CLK_CPUX>;\n+\t\t};\n+\n+\t\tcpu3: cpu@3 {\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <3>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tclocks = <&ccu CLK_CPUX>;\n+\t\t};\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\t/* 512KiB reserved for ARM Trusted Firmware (BL31) */\n+\t\tsecmon_reserved: secmon@40000000 {\n+\t\t\treg = <0x0 0x40000000 0x0 0x80000>;\n+\t\t\tno-map;\n+\t\t};\n+\t};\n+\n+\tosc24M: osc24M_clk {\n+\t\t#clock-cells = <0>;\n+\t\tcompatible = \"fixed-clock\";\n+\t\tclock-frequency = <24000000>;\n+\t\tclock-output-names = \"osc24M\";\n+\t};\n+\n+\tpmu {\n+\t\tcompatible = \"arm,cortex-a53-pmu\";\n+\t\tinterrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tinterrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;\n+\t};\n+\n+\tpsci {\n+\t\tcompatible = \"arm,psci-0.2\";\n+\t\tmethod = \"smc\";\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv8-timer\";\n+\t\tarm,no-tick-in-suspend;\n+\t\tinterrupts = <GIC_PPI 13\n+\t\t\t(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,\n+\t\t\t     <GIC_PPI 14\n+\t\t\t(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,\n+\t\t\t     <GIC_PPI 11\n+\t\t\t(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,\n+\t\t\t     <GIC_PPI 10\n+\t\t\t(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n+\t};\n+\n+\tsoc {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges = <0x0 0x0 0x0 0x40000000>;\n+\n+\t\tsyscon: syscon@3000000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-system-control\";\n+\t\t\treg = <0x03000000 0x1000>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges;\n+\n+\t\t\tsram_c: sram@28000 {\n+\t\t\t\tcompatible = \"mmio-sram\";\n+\t\t\t\treg = <0x00028000 0x30000>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n+\t\t\t\tranges = <0 0x00028000 0x30000>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tccu: clock@3001000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-ccu\";\n+\t\t\treg = <0x03001000 0x1000>;\n+\t\t\tclocks = <&osc24M>, <&rtc 0>, <&rtc 2>;\n+\t\t\tclock-names = \"hosc\", \"losc\", \"iosc\";\n+\t\t\t#clock-cells = <1>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n+\t\twatchdog: watchdog@30090a0 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-wdt\",\n+\t\t\t\t     \"allwinner,sun6i-a31-wdt\";\n+\t\t\treg = <0x030090a0 0x20>;\n+\t\t\tinterrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&osc24M>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpio: pinctrl@300b000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-pinctrl\";\n+\t\t\treg = <0x0300b000 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;\n+\t\t\tclock-names = \"apb\", \"hosc\", \"losc\";\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <3>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <3>;\n+\n+\t\t\text_rgmii_pins: rgmii-pins {\n+\t\t\t\tpins = \"PI0\", \"PI1\", \"PI2\", \"PI3\", \"PI4\",\n+\t\t\t\t       \"PI5\", \"PI7\", \"PI8\", \"PI9\", \"PI10\",\n+\t\t\t\t       \"PI11\", \"PI12\", \"PI13\", \"PI14\", \"PI15\",\n+\t\t\t\t       \"PI16\";\n+\t\t\t\tfunction = \"emac0\";\n+\t\t\t\tdrive-strength = <40>;\n+\t\t\t};\n+\n+\t\t\ti2c0_pins: i2c0-pins {\n+\t\t\t\tpins = \"PI6\", \"PI7\";\n+\t\t\t\tfunction = \"i2c0\";\n+\t\t\t};\n+\n+\t\t\ti2c3_ph_pins: i2c3-ph-pins {\n+\t\t\t\tpins = \"PH4\", \"PH5\";\n+\t\t\t\tfunction = \"i2c3\";\n+\t\t\t};\n+\n+\t\t\tir_rx_pin: ir_rx_pin {\n+\t\t\t\tpins = \"PH10\";\n+\t\t\t\tfunction = \"ir_rx\";\n+\t\t\t};\n+\n+\t\t\tmmc0_pins: mmc0-pins {\n+\t\t\t\tpins = \"PF0\", \"PF1\", \"PF2\", \"PF3\",\n+\t\t\t\t       \"PF4\", \"PF5\";\n+\t\t\t\tfunction = \"mmc0\";\n+\t\t\t\tdrive-strength = <30>;\n+\t\t\t\tbias-pull-up;\n+\t\t\t};\n+\n+\t\t\tmmc1_pins: mmc1-pins {\n+\t\t\t\tpins = \"PG0\", \"PG1\", \"PG2\", \"PG3\",\n+\t\t\t\t       \"PG4\", \"PG5\";\n+\t\t\t\tfunction = \"mmc1\";\n+\t\t\t\tdrive-strength = <30>;\n+\t\t\t\tbias-pull-up;\n+\t\t\t};\n+\n+\t\t\tmmc2_pins: mmc2-pins {\n+\t\t\t\tpins = \"PC0\", \"PC1\", \"PC5\", \"PC6\",\n+\t\t\t\t       \"PC8\", \"PC9\", \"PC10\", \"PC11\",\n+\t\t\t\t       \"PC13\", \"PC14\", \"PC15\", \"PC16\";\n+\t\t\t\tfunction = \"mmc2\";\n+\t\t\t\tdrive-strength = <30>;\n+\t\t\t\tbias-pull-up;\n+\t\t\t};\n+\n+\t\t\tspi0_pins: spi0-pins {\n+\t\t\t\tpins = \"PC0\", \"PC2\", \"PC3\", \"PC4\";\n+\t\t\t\tfunction = \"spi0\";\n+\t\t\t};\n+\n+\t\t\tspi1_pins: spi1-pins {\n+\t\t\t\tpins = \"PH6\", \"PH7\", \"PH8\";\n+\t\t\t\tfunction = \"spi1\";\n+\t\t\t};\n+\n+\t\t\tspi1_cs_pin: spi1-cs-pin {\n+\t\t\t\tpins = \"PH5\";\n+\t\t\t\tfunction = \"spi1\";\n+\t\t\t};\n+\n+\t\t\tuart0_ph_pins: uart0-ph-pins {\n+\t\t\t\tpins = \"PH0\", \"PH1\";\n+\t\t\t\tfunction = \"uart0\";\n+\t\t\t};\n+\n+\t\t\tuart1_pins: uart1-pins {\n+\t\t\t\tpins = \"PG6\", \"PG7\";\n+\t\t\t\tfunction = \"uart1\";\n+\t\t\t};\n+\n+\t\t\tuart1_rts_cts_pins: uart1-rts-cts-pins {\n+\t\t\t\tpins = \"PG8\", \"PG9\";\n+\t\t\t\tfunction = \"uart1\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tgic: interrupt-controller@3021000 {\n+\t\t\tcompatible = \"arm,gic-400\";\n+\t\t\treg = <0x03021000 0x1000>,\n+\t\t\t      <0x03022000 0x2000>,\n+\t\t\t      <0x03024000 0x2000>,\n+\t\t\t      <0x03026000 0x2000>;\n+\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <3>;\n+\t\t};\n+\n+\t\tmmc0: mmc@4020000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-mmc\",\n+\t\t\t\t     \"allwinner,sun50i-a100-mmc\";\n+\t\t\treg = <0x04020000 0x1000>;\n+\t\t\tclocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;\n+\t\t\tclock-names = \"ahb\", \"mmc\";\n+\t\t\tresets = <&ccu RST_BUS_MMC0>;\n+\t\t\treset-names = \"ahb\";\n+\t\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&mmc0_pins>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\n+\t\tmmc1: mmc@4021000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-mmc\",\n+\t\t\t\t     \"allwinner,sun50i-a100-mmc\";\n+\t\t\treg = <0x04021000 0x1000>;\n+\t\t\tclocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;\n+\t\t\tclock-names = \"ahb\", \"mmc\";\n+\t\t\tresets = <&ccu RST_BUS_MMC1>;\n+\t\t\treset-names = \"ahb\";\n+\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&mmc1_pins>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\n+\t\tmmc2: mmc@4022000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-emmc\",\n+\t\t\t\t     \"allwinner,sun50i-a100-emmc\";\n+\t\t\treg = <0x04022000 0x1000>;\n+\t\t\tclocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;\n+\t\t\tclock-names = \"ahb\", \"mmc\";\n+\t\t\tresets = <&ccu RST_BUS_MMC2>;\n+\t\t\treset-names = \"ahb\";\n+\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&mmc2_pins>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\n+\t\tuart0: serial@5000000 {\n+\t\t\tcompatible = \"snps,dw-apb-uart\";\n+\t\t\treg = <0x05000000 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\treg-shift = <2>;\n+\t\t\treg-io-width = <4>;\n+\t\t\tclocks = <&ccu CLK_BUS_UART0>;\n+\t\t\tresets = <&ccu RST_BUS_UART0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart1: serial@5000400 {\n+\t\t\tcompatible = \"snps,dw-apb-uart\";\n+\t\t\treg = <0x05000400 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\treg-shift = <2>;\n+\t\t\treg-io-width = <4>;\n+\t\t\tclocks = <&ccu CLK_BUS_UART1>;\n+\t\t\tresets = <&ccu RST_BUS_UART1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart2: serial@5000800 {\n+\t\t\tcompatible = \"snps,dw-apb-uart\";\n+\t\t\treg = <0x05000800 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\treg-shift = <2>;\n+\t\t\treg-io-width = <4>;\n+\t\t\tclocks = <&ccu CLK_BUS_UART2>;\n+\t\t\tresets = <&ccu RST_BUS_UART2>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart3: serial@5000c00 {\n+\t\t\tcompatible = \"snps,dw-apb-uart\";\n+\t\t\treg = <0x05000c00 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\treg-shift = <2>;\n+\t\t\treg-io-width = <4>;\n+\t\t\tclocks = <&ccu CLK_BUS_UART3>;\n+\t\t\tresets = <&ccu RST_BUS_UART3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart4: serial@5001000 {\n+\t\t\tcompatible = \"snps,dw-apb-uart\";\n+\t\t\treg = <0x05001000 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\treg-shift = <2>;\n+\t\t\treg-io-width = <4>;\n+\t\t\tclocks = <&ccu CLK_BUS_UART4>;\n+\t\t\tresets = <&ccu RST_BUS_UART4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart5: serial@5001400 {\n+\t\t\tcompatible = \"snps,dw-apb-uart\";\n+\t\t\treg = <0x05001400 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\treg-shift = <2>;\n+\t\t\treg-io-width = <4>;\n+\t\t\tclocks = <&ccu CLK_BUS_UART5>;\n+\t\t\tresets = <&ccu RST_BUS_UART5>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ti2c0: i2c@5002000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-i2c\",\n+\t\t\t\t     \"allwinner,sun6i-a31-i2c\";\n+\t\t\treg = <0x05002000 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_I2C0>;\n+\t\t\tresets = <&ccu RST_BUS_I2C0>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&i2c0_pins>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\n+\t\ti2c1: i2c@5002400 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-i2c\",\n+\t\t\t\t     \"allwinner,sun6i-a31-i2c\";\n+\t\t\treg = <0x05002400 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_I2C1>;\n+\t\t\tresets = <&ccu RST_BUS_I2C1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\n+\t\ti2c2: i2c@5002800 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-i2c\",\n+\t\t\t\t     \"allwinner,sun6i-a31-i2c\";\n+\t\t\treg = <0x05002800 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_I2C2>;\n+\t\t\tresets = <&ccu RST_BUS_I2C2>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\n+\t\ti2c3: i2c@5002c00 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-i2c\",\n+\t\t\t\t     \"allwinner,sun6i-a31-i2c\";\n+\t\t\treg = <0x05002c00 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_I2C3>;\n+\t\t\tresets = <&ccu RST_BUS_I2C3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\n+\t\ti2c4: i2c@5003000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-i2c\",\n+\t\t\t\t     \"allwinner,sun6i-a31-i2c\";\n+\t\t\treg = <0x05003000 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_I2C4>;\n+\t\t\tresets = <&ccu RST_BUS_I2C4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\n+\t\tspi0: spi@5010000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-spi\",\n+\t\t\t\t     \"allwinner,sun8i-h3-spi\";\n+\t\t\treg = <0x05010000 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;\n+\t\t\tclock-names = \"ahb\", \"mod\";\n+\t\t\tresets = <&ccu RST_BUS_SPI0>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&spi0_pins>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\n+\t\tspi1: spi@5011000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-spi\",\n+\t\t\t\t     \"allwinner,sun8i-h3-spi\";\n+\t\t\treg = <0x05011000 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;\n+\t\t\tclock-names = \"ahb\", \"mod\";\n+\t\t\tresets = <&ccu RST_BUS_SPI1>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&spi1_pins>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\n+\t\temac0: ethernet@5020000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-emac\",\n+\t\t\t\t     \"allwinner,sun50i-h6-emac\",\n+\t\t\t\t     \"allwinner,sun50i-a64-emac\";\n+\t\t\tsyscon = <&syscon>;\n+\t\t\treg = <0x05020000 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"macirq\";\n+\t\t\tresets = <&ccu RST_BUS_EMAC0>;\n+\t\t\treset-names = \"stmmaceth\";\n+\t\t\tclocks = <&ccu CLK_BUS_EMAC0>;\n+\t\t\tclock-names = \"stmmaceth\";\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tmdio0: mdio {\n+\t\t\t\tcompatible = \"snps,dwmac-mdio\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\n+\t\temac1: ethernet@5030000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-emac\";\n+\t\t\tsyscon = <&syscon 1>;\n+\t\t\treg = <0x05030000 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"macirq\";\n+\t\t\tresets = <&ccu RST_BUS_EMAC1>;\n+\t\t\treset-names = \"stmmaceth\";\n+\t\t\tclocks = <&ccu CLK_BUS_EMAC1>;\n+\t\t\tclock-names = \"stmmaceth\";\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tmdio1: mdio {\n+\t\t\t\tcompatible = \"snps,dwmac-mdio\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tusbotg: usb@5100000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-musb\",\n+\t\t\t\t     \"allwinner,sun8i-h3-musb\";\n+\t\t\treg = <0x05100000 0x0400>;\n+\t\t\tclocks = <&ccu CLK_BUS_OTG>;\n+\t\t\tresets = <&ccu RST_BUS_OTG>;\n+\t\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"mc\";\n+\t\t\tphys = <&usbphy 0>;\n+\t\t\tphy-names = \"usb\";\n+\t\t\textcon = <&usbphy 0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tusbphy: phy@5100400 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-usb-phy\";\n+\t\t\treg = <0x05100400 0x24>,\n+\t\t\t      <0x05101800 0x14>,\n+\t\t\t      <0x05200800 0x14>,\n+\t\t\t      <0x05310800 0x14>,\n+\t\t\t      <0x05311800 0x14>;\n+\t\t\treg-names = \"phy_ctrl\",\n+\t\t\t\t    \"pmu0\",\n+\t\t\t\t    \"pmu1\",\n+\t\t\t\t    \"pmu2\",\n+\t\t\t\t    \"pmu3\";\n+\t\t\tclocks = <&ccu CLK_USB_PHY0>,\n+\t\t\t\t <&ccu CLK_USB_PHY1>,\n+\t\t\t\t <&ccu CLK_USB_PHY2>,\n+\t\t\t\t <&ccu CLK_USB_PHY3>;\n+\t\t\tclock-names = \"usb0_phy\",\n+\t\t\t\t      \"usb1_phy\",\n+\t\t\t\t      \"usb2_phy\",\n+\t\t\t\t      \"usb3_phy\";\n+\t\t\tresets = <&ccu RST_USB_PHY0>,\n+\t\t\t\t <&ccu RST_USB_PHY1>,\n+\t\t\t\t <&ccu RST_USB_PHY2>,\n+\t\t\t\t <&ccu RST_USB_PHY3>;\n+\t\t\treset-names = \"usb0_reset\",\n+\t\t\t\t      \"usb1_reset\",\n+\t\t\t\t      \"usb2_reset\",\n+\t\t\t\t      \"usb3_reset\";\n+\t\t\tstatus = \"disabled\";\n+\t\t\t#phy-cells = <1>;\n+\t\t};\n+\n+\t\tehci0: usb@5101000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-ehci\",\n+\t\t\t\t     \"generic-ehci\";\n+\t\t\treg = <0x05101000 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_OHCI0>,\n+\t\t\t\t <&ccu CLK_BUS_EHCI0>,\n+\t\t\t\t <&ccu CLK_USB_OHCI0>;\n+\t\t\tresets = <&ccu RST_BUS_OHCI0>,\n+\t\t\t\t <&ccu RST_BUS_EHCI0>;\n+\t\t\tphys = <&usbphy 0>;\n+\t\t\tphy-names = \"usb\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tohci0: usb@5101400 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-ohci\",\n+\t\t\t\t     \"generic-ohci\";\n+\t\t\treg = <0x05101400 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_OHCI0>,\n+\t\t\t\t <&ccu CLK_USB_OHCI0>;\n+\t\t\tresets = <&ccu RST_BUS_OHCI0>;\n+\t\t\tphys = <&usbphy 0>;\n+\t\t\tphy-names = \"usb\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tehci1: usb@5200000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-ehci\",\n+\t\t\t\t     \"generic-ehci\";\n+\t\t\treg = <0x05200000 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_OHCI1>,\n+\t\t\t\t <&ccu CLK_BUS_EHCI1>,\n+\t\t\t\t <&ccu CLK_USB_OHCI1>;\n+\t\t\tresets = <&ccu RST_BUS_OHCI1>,\n+\t\t\t\t <&ccu RST_BUS_EHCI1>;\n+\t\t\tphys = <&usbphy 1>;\n+\t\t\tphy-names = \"usb\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tohci1: usb@5200400 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-ohci\",\n+\t\t\t\t     \"generic-ohci\";\n+\t\t\treg = <0x05200400 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_OHCI1>,\n+\t\t\t\t <&ccu CLK_USB_OHCI1>;\n+\t\t\tresets = <&ccu RST_BUS_OHCI1>;\n+\t\t\tphys = <&usbphy 1>;\n+\t\t\tphy-names = \"usb\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tehci2: usb@5310000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-ehci\",\n+\t\t\t\t     \"generic-ehci\";\n+\t\t\treg = <0x05310000 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_OHCI2>,\n+\t\t\t\t <&ccu CLK_BUS_EHCI2>,\n+\t\t\t\t <&ccu CLK_USB_OHCI2>;\n+\t\t\tresets = <&ccu RST_BUS_OHCI2>,\n+\t\t\t\t <&ccu RST_BUS_EHCI2>;\n+\t\t\tphys = <&usbphy 2>;\n+\t\t\tphy-names = \"usb\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tohci2: usb@5310400 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-ohci\",\n+\t\t\t\t     \"generic-ohci\";\n+\t\t\treg = <0x05310400 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_OHCI2>,\n+\t\t\t\t <&ccu CLK_USB_OHCI2>;\n+\t\t\tresets = <&ccu RST_BUS_OHCI2>;\n+\t\t\tphys = <&usbphy 2>;\n+\t\t\tphy-names = \"usb\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tehci3: usb@5311000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-ehci\",\n+\t\t\t\t     \"generic-ehci\";\n+\t\t\treg = <0x05311000 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_OHCI3>,\n+\t\t\t\t <&ccu CLK_BUS_EHCI3>,\n+\t\t\t\t <&ccu CLK_USB_OHCI3>;\n+\t\t\tresets = <&ccu RST_BUS_OHCI3>,\n+\t\t\t\t <&ccu RST_BUS_EHCI3>;\n+\t\t\tphys = <&usbphy 3>;\n+\t\t\tphy-names = \"usb\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tohci3: usb@5311400 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-ohci\",\n+\t\t\t\t     \"generic-ohci\";\n+\t\t\treg = <0x05311400 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&ccu CLK_BUS_OHCI3>,\n+\t\t\t\t <&ccu CLK_USB_OHCI3>;\n+\t\t\tresets = <&ccu RST_BUS_OHCI3>;\n+\t\t\tphys = <&usbphy 3>;\n+\t\t\tphy-names = \"usb\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\trtc: rtc@7000000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-rtc\",\n+\t\t\t\t     \"allwinner,sun50i-h6-rtc\";\n+\t\t\treg = <0x07000000 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-output-names = \"osc32k\", \"osc32k-out\", \"iosc\";\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tr_ccu: clock@7010000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-r-ccu\";\n+\t\t\treg = <0x07010000 0x400>;\n+\t\t\tclocks = <&osc24M>, <&rtc 0>, <&rtc 2>,\n+\t\t\t\t <&ccu CLK_PLL_PERIPH0>;\n+\t\t\tclock-names = \"hosc\", \"losc\", \"iosc\", \"pll-periph\";\n+\t\t\t#clock-cells = <1>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n+\t\tr_pio: pinctrl@7022000 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-r-pinctrl\";\n+\t\t\treg = <0x07022000 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;\n+\t\t\tclock-names = \"apb\", \"hosc\", \"losc\";\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <3>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <3>;\n+\n+\t\t\tr_i2c_pins: r-i2c-pins {\n+\t\t\t\tpins = \"PL0\", \"PL1\";\n+\t\t\t\tfunction = \"s_i2c\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tir: ir@7040000 {\n+\t\t\t\tcompatible = \"allwinner,sun50i-h616-ir\",\n+\t\t\t\t\t     \"allwinner,sun6i-a31-ir\";\n+\t\t\t\treg = <0x07040000 0x400>;\n+\t\t\t\tinterrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tclocks = <&r_ccu CLK_R_APB1_IR>,\n+\t\t\t\t\t <&r_ccu CLK_IR>;\n+\t\t\t\tclock-names = \"apb\", \"ir\";\n+\t\t\t\tresets = <&r_ccu RST_R_APB1_IR>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&ir_rx_pin>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tr_i2c: i2c@7081400 {\n+\t\t\tcompatible = \"allwinner,sun50i-h616-i2c\",\n+\t\t\t\t     \"allwinner,sun6i-a31-i2c\";\n+\t\t\treg = <0x07081400 0x400>;\n+\t\t\tinterrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&r_ccu CLK_R_APB2_I2C>;\n+\t\t\tresets = <&r_ccu RST_R_APB2_I2C>;\n+\t\t\tstatus = \"disabled\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\t};\n+};\ndiff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h\nnew file mode 100644\nindex 000000000000..4fc08b0df2f3\n--- /dev/null\n+++ b/include/dt-bindings/clock/sun50i-h616-ccu.h\n@@ -0,0 +1,115 @@\n+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */\n+/*\n+ * Copyright (C) 2020 Arm Ltd.\n+ */\n+\n+#ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_\n+#define _DT_BINDINGS_CLK_SUN50I_H616_H_\n+\n+#define CLK_PLL_PERIPH0\t\t4\n+\n+#define CLK_CPUX\t\t21\n+\n+#define CLK_APB1\t\t26\n+\n+#define CLK_DE\t\t\t29\n+#define CLK_BUS_DE\t\t30\n+#define CLK_DEINTERLACE\t\t31\n+#define CLK_BUS_DEINTERLACE\t32\n+#define CLK_G2D\t\t\t33\n+#define CLK_BUS_G2D\t\t34\n+#define CLK_GPU0\t\t35\n+#define CLK_BUS_GPU\t\t36\n+#define CLK_GPU1\t\t37\n+#define CLK_CE\t\t\t38\n+#define CLK_BUS_CE\t\t39\n+#define CLK_VE\t\t\t40\n+#define CLK_BUS_VE\t\t41\n+#define CLK_BUS_DMA\t\t42\n+#define CLK_BUS_HSTIMER\t\t43\n+#define CLK_AVS\t\t\t44\n+#define CLK_BUS_DBG\t\t45\n+#define CLK_BUS_PSI\t\t46\n+#define CLK_BUS_PWM\t\t47\n+#define CLK_BUS_IOMMU\t\t48\n+\n+#define CLK_MBUS_DMA\t\t50\n+#define CLK_MBUS_VE\t\t51\n+#define CLK_MBUS_CE\t\t52\n+#define CLK_MBUS_TS\t\t53\n+#define CLK_MBUS_NAND\t\t54\n+#define CLK_MBUS_G2D\t\t55\n+\n+#define CLK_NAND0\t\t57\n+#define CLK_NAND1\t\t58\n+#define CLK_BUS_NAND\t\t59\n+#define CLK_MMC0\t\t60\n+#define CLK_MMC1\t\t61\n+#define CLK_MMC2\t\t62\n+#define CLK_BUS_MMC0\t\t63\n+#define CLK_BUS_MMC1\t\t64\n+#define CLK_BUS_MMC2\t\t65\n+#define CLK_BUS_UART0\t\t66\n+#define CLK_BUS_UART1\t\t67\n+#define CLK_BUS_UART2\t\t68\n+#define CLK_BUS_UART3\t\t69\n+#define CLK_BUS_UART4\t\t70\n+#define CLK_BUS_UART5\t\t71\n+#define CLK_BUS_I2C0\t\t72\n+#define CLK_BUS_I2C1\t\t73\n+#define CLK_BUS_I2C2\t\t74\n+#define CLK_BUS_I2C3\t\t75\n+#define CLK_BUS_I2C4\t\t76\n+#define CLK_SPI0\t\t77\n+#define CLK_SPI1\t\t78\n+#define CLK_BUS_SPI0\t\t79\n+#define CLK_BUS_SPI1\t\t80\n+#define CLK_EMAC_25M\t\t81\n+#define CLK_BUS_EMAC0\t\t82\n+#define CLK_BUS_EMAC1\t\t83\n+#define CLK_TS\t\t\t84\n+#define CLK_BUS_TS\t\t85\n+#define CLK_BUS_THS\t\t86\n+#define CLK_SPDIF\t\t87\n+#define CLK_BUS_SPDIF\t\t88\n+#define CLK_DMIC\t\t89\n+#define CLK_BUS_DMIC\t\t90\n+#define CLK_AUDIO_CODEC_1X\t91\n+#define CLK_AUDIO_CODEC_4X\t92\n+#define CLK_BUS_AUDIO_CODEC\t93\n+#define CLK_AUDIO_HUB\t\t94\n+#define CLK_BUS_AUDIO_HUB\t95\n+#define CLK_USB_OHCI0\t\t96\n+#define CLK_USB_PHY0\t\t97\n+#define CLK_USB_OHCI1\t\t98\n+#define CLK_USB_PHY1\t\t99\n+#define CLK_USB_OHCI2\t\t100\n+#define CLK_USB_PHY2\t\t101\n+#define CLK_USB_OHCI3\t\t102\n+#define CLK_USB_PHY3\t\t103\n+#define CLK_BUS_OHCI0\t\t104\n+#define CLK_BUS_OHCI1\t\t105\n+#define CLK_BUS_OHCI2\t\t106\n+#define CLK_BUS_OHCI3\t\t107\n+#define CLK_BUS_EHCI0\t\t108\n+#define CLK_BUS_EHCI1\t\t109\n+#define CLK_BUS_EHCI2\t\t110\n+#define CLK_BUS_EHCI3\t\t111\n+#define CLK_BUS_OTG\t\t112\n+#define CLK_BUS_KEYADC\t\t113\n+#define CLK_HDMI\t\t114\n+#define CLK_HDMI_SLOW\t\t115\n+#define CLK_HDMI_CEC\t\t116\n+#define CLK_BUS_HDMI\t\t117\n+#define CLK_BUS_TCON_TOP\t118\n+#define CLK_TCON_TV0\t\t119\n+#define CLK_TCON_TV1\t\t120\n+#define CLK_BUS_TCON_TV0\t121\n+#define CLK_BUS_TCON_TV1\t122\n+#define CLK_TVE0\t\t123\n+#define CLK_BUS_TVE_TOP\t\t124\n+#define CLK_BUS_TVE0\t\t125\n+#define CLK_HDCP\t\t126\n+#define CLK_BUS_HDCP\t\t127\n+\n+#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */\ndiff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h\nnew file mode 100644\nindex 000000000000..cb6285a8d128\n--- /dev/null\n+++ b/include/dt-bindings/reset/sun50i-h616-ccu.h\n@@ -0,0 +1,70 @@\n+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */\n+/*\n+ * Copyright (C) 2020 Arm Ltd.\n+ */\n+\n+#ifndef _DT_BINDINGS_RESET_SUN50I_H616_H_\n+#define _DT_BINDINGS_RESET_SUN50I_H616_H_\n+\n+#define RST_MBUS\t\t0\n+#define RST_BUS_DE\t\t1\n+#define RST_BUS_DEINTERLACE\t2\n+#define RST_BUS_GPU\t\t3\n+#define RST_BUS_CE\t\t4\n+#define RST_BUS_VE\t\t5\n+#define RST_BUS_DMA\t\t6\n+#define RST_BUS_HSTIMER\t\t7\n+#define RST_BUS_DBG\t\t8\n+#define RST_BUS_PSI\t\t9\n+#define RST_BUS_PWM\t\t10\n+#define RST_BUS_IOMMU\t\t11\n+#define RST_BUS_DRAM\t\t12\n+#define RST_BUS_NAND\t\t13\n+#define RST_BUS_MMC0\t\t14\n+#define RST_BUS_MMC1\t\t15\n+#define RST_BUS_MMC2\t\t16\n+#define RST_BUS_UART0\t\t17\n+#define RST_BUS_UART1\t\t18\n+#define RST_BUS_UART2\t\t19\n+#define RST_BUS_UART3\t\t20\n+#define RST_BUS_UART4\t\t21\n+#define RST_BUS_UART5\t\t22\n+#define RST_BUS_I2C0\t\t23\n+#define RST_BUS_I2C1\t\t24\n+#define RST_BUS_I2C2\t\t25\n+#define RST_BUS_I2C3\t\t26\n+#define RST_BUS_I2C4\t\t27\n+#define RST_BUS_SPI0\t\t28\n+#define RST_BUS_SPI1\t\t29\n+#define RST_BUS_EMAC0\t\t30\n+#define RST_BUS_EMAC1\t\t31\n+#define RST_BUS_TS\t\t32\n+#define RST_BUS_THS\t\t33\n+#define RST_BUS_SPDIF\t\t34\n+#define RST_BUS_DMIC\t\t35\n+#define RST_BUS_AUDIO_CODEC\t36\n+#define RST_BUS_AUDIO_HUB\t37\n+#define RST_USB_PHY0\t\t38\n+#define RST_USB_PHY1\t\t39\n+#define RST_USB_PHY2\t\t40\n+#define RST_USB_PHY3\t\t41\n+#define RST_BUS_OHCI0\t\t42\n+#define RST_BUS_OHCI1\t\t43\n+#define RST_BUS_OHCI2\t\t44\n+#define RST_BUS_OHCI3\t\t45\n+#define RST_BUS_EHCI0\t\t46\n+#define RST_BUS_EHCI1\t\t47\n+#define RST_BUS_EHCI2\t\t48\n+#define RST_BUS_EHCI3\t\t49\n+#define RST_BUS_OTG\t\t50\n+#define RST_BUS_HDMI\t\t51\n+#define RST_BUS_HDMI_SUB\t52\n+#define RST_BUS_TCON_TOP\t53\n+#define RST_BUS_TCON_TV0\t54\n+#define RST_BUS_TCON_TV1\t55\n+#define RST_BUS_TVE_TOP\t\t56\n+#define RST_BUS_TVE0\t\t57\n+#define RST_BUS_HDCP\t\t58\n+#define RST_BUS_KEYADC\t\t59\n+\n+#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */\n",
    "prefixes": [
        "14/17"
    ]
}