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GET /api/patches/1421823/?format=api
{ "id": 1421823, "url": "http://patchwork.ozlabs.org/api/patches/1421823/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20210103092633.36226-6-jernej.skrabec@siol.net/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20210103092633.36226-6-jernej.skrabec@siol.net>", "list_archive_url": null, "date": "2021-01-03T09:26:21", "name": "[05/17] sunxi: prcm: Add memory map for H6 like SoCs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "c0256b117f718ab8794fd081cbaaa1eab5721eb9", "submitter": { "id": 70601, "url": "http://patchwork.ozlabs.org/api/people/70601/?format=api", "name": "Jernej Škrabec", "email": "jernej.skrabec@siol.net" }, "delegate": { "id": 114289, "url": "http://patchwork.ozlabs.org/api/users/114289/?format=api", "username": "apritzel", "first_name": "Andre", "last_name": "Przywara", "email": "andre.przywara@arm.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20210103092633.36226-6-jernej.skrabec@siol.net/mbox/", "series": [ { "id": 222511, "url": "http://patchwork.ozlabs.org/api/series/222511/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=222511", "date": "2021-01-03T09:26:16", "name": "sunxi: Introduce H616 support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/222511/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1421823/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1421823/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=fail (p=none dis=none) header.from=siol.net", "phobos.denx.de;\n dmarc=fail (p=none dis=none) header.from=siol.net", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=siol.net", "phobos.denx.de;\n spf=pass smtp.mailfrom=jernej.skrabec@siol.net" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4D7tjL0jB2z9sVn\n\tfor <incoming@patchwork.ozlabs.org>; Sun, 3 Jan 2021 20:28:21 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 6EFCE8266F;\n\tSun, 3 Jan 2021 10:27:12 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 6E6308266A; Sun, 3 Jan 2021 10:27:09 +0100 (CET)", "from mail.siol.net (mailoutvs34.siol.net [185.57.226.225])\n (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id B292B8264E\n for <u-boot@lists.denx.de>; Sun, 3 Jan 2021 10:27:01 +0100 (CET)", "from localhost (localhost [127.0.0.1])\n by mail.siol.net (Zimbra) with ESMTP id 66334522AFF;\n Sun, 3 Jan 2021 10:27:01 +0100 (CET)", "from mail.siol.net ([127.0.0.1])\n by localhost (psrvmta12.zcs-production.pri [127.0.0.1]) (amavisd-new,\n port 10032)\n with ESMTP id 7r9gq384xezo; Sun, 3 Jan 2021 10:27:00 +0100 (CET)", "from mail.siol.net (localhost [127.0.0.1])\n by mail.siol.net (Zimbra) with ESMTPS id 75E0B522B0D;\n Sun, 3 Jan 2021 10:27:00 +0100 (CET)", "from localhost.localdomain (89-212-178-211.dynamic.t-2.net\n [89.212.178.211]) (Authenticated sender: 031275009)\n by mail.siol.net (Zimbra) with ESMTPSA id 39730522AFF;\n Sun, 3 Jan 2021 10:26:58 +0100 (CET)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE,UPPERCASE_50_75 autolearn=ham autolearn_force=no\n version=3.4.2", "From": "Jernej Skrabec <jernej.skrabec@siol.net>", "To": "jagan@amarulasolutions.com,\n\tandre.przywara@arm.com", "Cc": "hdegoede@redhat.com, jernej.skrabec@siol.net, lukma@denx.de, hs@denx.de,\n peng.fan@nxp.com, joe.hershberger@ni.com, jh80.chung@samsung.com,\n u-boot@lists.denx.de, linux-sunxi@googlegroups.com", "Subject": "[PATCH 05/17] sunxi: prcm: Add memory map for H6 like SoCs", "Date": "Sun, 3 Jan 2021 10:26:21 +0100", "Message-Id": "<20210103092633.36226-6-jernej.skrabec@siol.net>", "X-Mailer": "git-send-email 2.30.0", "In-Reply-To": "<20210103092633.36226-1-jernej.skrabec@siol.net>", "References": "<20210103092633.36226-1-jernej.skrabec@siol.net>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "quoted-printable", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "There was no need to have prcm definitions for H6 and similar SoCs till\nnow. However, support R_I2C will be needed soon in SPL.\n\nMove old definitions to prcm_sun6i.h and add new ones in prcm_sun50i.h.\nOne of those files will be selected in common prcm.h based on defined\nmacros.\n\nThis commit doesn't do any functional change.\n\nSigned-off-by: Jernej Skrabec <jernej.skrabec@siol.net>\n---\n arch/arm/include/asm/arch-sunxi/prcm.h | 249 +-----------------\n arch/arm/include/asm/arch-sunxi/prcm_sun50i.h | 41 +++\n arch/arm/include/asm/arch-sunxi/prcm_sun6i.h | 247 +++++++++++++++++\n 3 files changed, 298 insertions(+), 239 deletions(-)\n create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun50i.h\n create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun6i.h", "diff": "diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h\nindex 767d1ff98d74..5106076f5e91 100644\n--- a/arch/arm/include/asm/arch-sunxi/prcm.h\n+++ b/arch/arm/include/asm/arch-sunxi/prcm.h\n@@ -1,247 +1,18 @@\n /* SPDX-License-Identifier: GPL-2.0+ */\n /*\n- * Sunxi A31 Power Management Unit register definition.\n+ * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>\n *\n- * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>\n- * http://linux-sunxi.org\n- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>\n- * Berg Xing <bergxing@allwinnertech.com>\n- * Tom Cubie <tangliang@allwinnertech.com>\n+ * Sunxi platform prcm register definition.\n */\n \n #ifndef _SUNXI_PRCM_H\n #define _SUNXI_PRCM_H\n \n-#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)\n-#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)\n-#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)\n-#define PRCM_CPUS_CFG_PRE_DIV(n) \\\n-\t__PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))\n-#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)\n-#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)\n-#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)\n-#define PRCM_CPUS_CFG_POST_DIV(n) \\\n-\t__PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))\n-#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)\n-#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)\n-#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0\n-#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1\n-#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2\n-#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3\n-#define PRCM_CPUS_CFG_CLK_SRC_LOSC \\\n-\t__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)\n-#define PRCM_CPUS_CFG_CLK_SRC_HOSC \\\n-\t__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)\n-#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \\\n-\t__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)\n-#define PRCM_CPUS_CFG_CLK_SRC_PDIV \\\n-\t__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)\n-\n-#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0)\n-#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)\n-#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)\n-#define PRCM_APB0_RATIO_DIV(n) \\\n-\t__PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))\n-\n-#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)\n-#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)\n-\n-#define PRCM_APB0_GATE_PIO (0x1 << 0)\n-#define PRCM_APB0_GATE_IR (0x1 << 1)\n-#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)\n-#define PRCM_APB0_GATE_P2WI (0x1 << 3)\t\t/* sun6i */\n-#define PRCM_APB0_GATE_RSB (0x1 << 3)\t\t/* sun8i */\n-#define PRCM_APB0_GATE_UART (0x1 << 4)\n-#define PRCM_APB0_GATE_1WIRE (0x1 << 5)\n-#define PRCM_APB0_GATE_I2C (0x1 << 6)\n-\n-#define PRCM_APB0_RESET_PIO (0x1 << 0)\n-#define PRCM_APB0_RESET_IR (0x1 << 1)\n-#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)\n-#define PRCM_APB0_RESET_P2WI (0x1 << 3)\n-#define PRCM_APB0_RESET_UART (0x1 << 4)\n-#define PRCM_APB0_RESET_1WIRE (0x1 << 5)\n-#define PRCM_APB0_RESET_I2C (0x1 << 6)\n-\n-#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)\n-#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)\n-#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)\n-#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \\\n-\t__PRCM_PLL_CTRL_USB_CLK_SRC(0x3)\n-#define __PRCM_PLL_CTRL_USB_CLK_0 0x0\n-#define __PRCM_PLL_CTRL_USB_CLK_1 0x1\n-#define __PRCM_PLL_CTRL_USB_CLK_2 0x2\n-#define __PRCM_PLL_CTRL_USB_CLK_3 0x3\n-#define PRCM_PLL_CTRL_USB_CLK_0 \\\n-\t__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0)\n-#define PRCM_PLL_CTRL_USB_CLK_1 \\\n-\t__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1)\n-#define PRCM_PLL_CTRL_USB_CLK_2 \\\n-\t__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2)\n-#define PRCM_PLL_CTRL_USB_CLK_3 \\\n-\t__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3)\n-#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12)\n-#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \\\n-\t__PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3)\n-#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \\\n-\t__PRCM_PLL_CTRL_INT_PLL_IN_SEL(n)\n-#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20)\n-#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \\\n-\t__PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3)\n-#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0\n-#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1\n-#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2\n-#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3\n-#define PRCM_PLL_CTRL_HOSC_CLK_0 \\\n-\t__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0)\n-#define PRCM_PLL_CTRL_HOSC_CLK_1 \\\n-\t__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1)\n-#define PRCM_PLL_CTRL_HOSC_CLK_2 \\\n-\t__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2)\n-#define PRCM_PLL_CTRL_HOSC_CLK_3 \\\n-\t__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3)\n-#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24)\n-#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0)\n-#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1)\n-#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2)\n-#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3)\n-#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */\n-#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16)\n-#define PRCM_PLL_CTRL_LDO_OUT_MASK \\\n-\t__PRCM_PLL_CTRL_LDO_OUT(0x7)\n-/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */\n-#define PRCM_PLL_CTRL_LDO_OUT_L(n) \\\n-\t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)\n-#define PRCM_PLL_CTRL_LDO_OUT_H(n) \\\n-\t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)\n-#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \\\n-\t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)\n-#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \\\n-\t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)\n-#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)\n-#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)\n-\n-#define PRCM_CLK_1WIRE_GATE (0x1 << 31)\n-\n-#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0)\n-#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf)\n-#define __PRCM_CLK_MOD0_M_X(n) (n - 1)\n-#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n))\n-#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8)\n-#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7)\n-#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16)\n-#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3)\n-#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1)\n-#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n))\n-#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20)\n-#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7)\n-#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24)\n-#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7)\n-#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31)\n-\n-#define PRCM_APB0_RESET_PIO (0x1 << 0)\n-#define PRCM_APB0_RESET_IR (0x1 << 1)\n-#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)\n-#define PRCM_APB0_RESET_P2WI (0x1 << 3)\n-#define PRCM_APB0_RESET_UART (0x1 << 4)\n-#define PRCM_APB0_RESET_1WIRE (0x1 << 5)\n-#define PRCM_APB0_RESET_I2C (0x1 << 6)\n-\n-#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8)\n-#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7)\n-#define __PRCM_CLK_OUTD_M_X() ((n) - 1)\n-#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n))\n-#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20)\n-#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7)\n-#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1)\n-#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n)\n-#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24)\n-#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3)\n-#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0\n-#define __PRCM_CLK_OUTD_SRC_LOSC 0x1\n-#define __PRCM_CLK_OUTD_SRC_HOSC 0x2\n-#define __PRCM_CLK_OUTD_SRC_ERR 0x3\n-#define PRCM_CLK_OUTD_SRC_LOSC2 \\\n-#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2)\n-#define PRCM_CLK_OUTD_SRC_LOSC \\\n-#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC)\n-#define PRCM_CLK_OUTD_SRC_HOSC \\\n-#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC)\n-#define PRCM_CLK_OUTD_SRC_ERR \\\n-#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR)\n-#define PRCM_CLK_OUTD_EN (0x1 << 31)\n-\n-#define PRCM_CPU0_PWROFF (0x1 << 0)\n-#define PRCM_CPU1_PWROFF (0x1 << 1)\n-#define PRCM_CPU2_PWROFF (0x1 << 2)\n-#define PRCM_CPU3_PWROFF (0x1 << 3)\n-#define PRCM_CPU_ALL_PWROFF (0xf << 0)\n-\n-#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0)\n-#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1)\n-#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2)\n-#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3)\n-\n-#define PRCM_VDD_GPU_PWROFF (0x1 << 0)\n-\n-#define PRCM_VDD_SYS_RESET (0x1 << 0)\n-\n-#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0)\n-#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff)\n-\n-#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0)\n-#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff)\n-\n-#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)\n-#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)\n-\n-#define PRCM_SEC_SWITCH_APB0_CLK_NONSEC (0x1 << 0)\n-#define PRCM_SEC_SWITCH_PLL_CFG_NONSEC (0x1 << 1)\n-#define PRCM_SEC_SWITCH_PWR_GATE_NONSEC (0x1 << 2)\n-\n-#ifndef __ASSEMBLY__\n-#include <linux/compiler.h>\n-\n-struct sunxi_prcm_reg {\n-\tu32 cpus_cfg;\t\t/* 0x000 */\n-\tu8 res0[0x8];\t\t/* 0x004 */\n-\tu32 apb0_ratio;\t\t/* 0x00c */\n-\tu32 cpu0_cfg;\t\t/* 0x010 */\n-\tu32 cpu1_cfg;\t\t/* 0x014 */\n-\tu32 cpu2_cfg;\t\t/* 0x018 */\n-\tu32 cpu3_cfg;\t\t/* 0x01c */\n-\tu8 res1[0x8];\t\t/* 0x020 */\n-\tu32 apb0_gate;\t\t/* 0x028 */\n-\tu8 res2[0x14];\t\t/* 0x02c */\n-\tu32 pll_ctrl0;\t\t/* 0x040 */\n-\tu32 pll_ctrl1;\t\t/* 0x044 */\n-\tu8 res3[0x8];\t\t/* 0x048 */\n-\tu32 clk_1wire;\t\t/* 0x050 */\n-\tu32 clk_ir;\t\t/* 0x054 */\n-\tu8 res4[0x58];\t\t/* 0x058 */\n-\tu32 apb0_reset;\t\t/* 0x0b0 */\n-\tu8 res5[0x3c];\t\t/* 0x0b4 */\n-\tu32 clk_outd;\t\t/* 0x0f0 */\n-\tu8 res6[0xc];\t\t/* 0x0f4 */\n-\tu32 cpu_pwroff;\t\t/* 0x100 */\n-\tu8 res7[0xc];\t\t/* 0x104 */\n-\tu32 vdd_sys_pwroff;\t/* 0x110 */\n-\tu8 res8[0x4];\t\t/* 0x114 */\n-\tu32 gpu_pwroff;\t\t/* 0x118 */\n-\tu8 res9[0x4];\t\t/* 0x11c */\n-\tu32 vdd_pwr_reset;\t/* 0x120 */\n-\tu8 res10[0x1c];\t\t/* 0x124 */\n-\tu32 cpu_pwr_clamp[4];\t/* 0x140 but first one is actually unused */\n-\tu8 res11[0x30];\t\t/* 0x150 */\n-\tu32 dram_pwr;\t\t/* 0x180 */\n-\tu8 res12[0xc];\t\t/* 0x184 */\n-\tu32 dram_tst;\t\t/* 0x190 */\n-\tu8 res13[0x3c];\t\t/* 0x194 */\n-\tu32 prcm_sec_switch;\t/* 0x1d0 */\n-};\n-\n-void prcm_apb0_enable(u32 flags);\n-void prcm_apb0_disable(u32 flags);\n-\n-#endif /* __ASSEMBLY__ */\n-#endif /* _PRCM_H */\n+/* prcm regs definition */\n+#if defined(CONFIG_SUN50I_GEN_H6)\n+#include <asm/arch/prcm_sun50i.h>\n+#else\n+#include <asm/arch/prcm_sun6i.h>\n+#endif\n+\n+#endif /* _SUNXI_PRCM_H */\ndiff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h\nnew file mode 100644\nindex 000000000000..68a78e50ce64\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h\n@@ -0,0 +1,41 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Sunxi H6 Power Management Unit register definition.\n+ *\n+ * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>\n+ */\n+\n+#ifndef _SUN50I_PRCM_H\n+#define _SUN50I_PRCM_H\n+\n+#ifndef __ASSEMBLY__\n+#include <linux/compiler.h>\n+\n+struct sunxi_prcm_reg {\n+\tu32 cpus_cfg;\t\t/* 0x000 */\n+\tu8 res0[0x8];\t\t/* 0x004 */\n+\tu32 apbs1_cfg;\t\t/* 0x00c */\n+\tu32 apbs2_cfg;\t\t/* 0x010 */\n+\tu8 res1[0x118];\t\t/* 0x014 */\n+\tu32 wdg_gate_reset;\t/* 0x12c */\n+\tu8 res2[0x6c];\t\t/* 0x130 */\n+\tu32 twi_gate_reset;\t/* 0x19c */\n+\tu8 res3[0x1c];\t\t/* 0x1a0 */\n+\tu32 rsb_gate_reset;\t/* 0x1bc */\n+\tu32 cir_cfg;\t\t/* 0x1c0 */\n+\tu8 res4[0x8];\t\t/* 0x1c4 */\n+\tu32 cir_gate_reset;\t/* 0x1cc */\n+\tu8 res5[0x10];\t\t/* 0x1d0 */\n+\tu32 w1_cfg;\t\t/* 0x1e0 */\n+\tu8 res6[0x8];\t\t/* 0x1e4 */\n+\tu32 w1_gate_reset;\t/* 0x1ec */\n+\tu8 res7[0x1c];\t\t/* 0x1f0 */\n+\tu32 rtc_gate_reset;\t/* 0x20c */\n+};\n+check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c);\n+\n+#define PRCM_TWI_GATE\t\t(1 << 0)\n+#define PRCM_TWI_RESET\t\t(1 << 16)\n+\n+#endif /* __ASSEMBLY__ */\n+#endif /* _PRCM_H */\ndiff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h\nnew file mode 100644\nindex 000000000000..ab664e80bbe8\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h\n@@ -0,0 +1,247 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Sunxi A31 Power Management Unit register definition.\n+ *\n+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>\n+ * http://linux-sunxi.org\n+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>\n+ * Berg Xing <bergxing@allwinnertech.com>\n+ * Tom Cubie <tangliang@allwinnertech.com>\n+ */\n+\n+#ifndef _SUN6I_PRCM_H\n+#define _SUN6I_PRCM_H\n+\n+#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)\n+#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)\n+#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)\n+#define PRCM_CPUS_CFG_PRE_DIV(n) \\\n+\t__PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))\n+#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)\n+#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)\n+#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)\n+#define PRCM_CPUS_CFG_POST_DIV(n) \\\n+\t__PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))\n+#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)\n+#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)\n+#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0\n+#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1\n+#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2\n+#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3\n+#define PRCM_CPUS_CFG_CLK_SRC_LOSC \\\n+\t__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)\n+#define PRCM_CPUS_CFG_CLK_SRC_HOSC \\\n+\t__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)\n+#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \\\n+\t__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)\n+#define PRCM_CPUS_CFG_CLK_SRC_PDIV \\\n+\t__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)\n+\n+#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0)\n+#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)\n+#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)\n+#define PRCM_APB0_RATIO_DIV(n) \\\n+\t__PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))\n+\n+#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)\n+#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)\n+\n+#define PRCM_APB0_GATE_PIO (0x1 << 0)\n+#define PRCM_APB0_GATE_IR (0x1 << 1)\n+#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)\n+#define PRCM_APB0_GATE_P2WI (0x1 << 3)\t\t/* sun6i */\n+#define PRCM_APB0_GATE_RSB (0x1 << 3)\t\t/* sun8i */\n+#define PRCM_APB0_GATE_UART (0x1 << 4)\n+#define PRCM_APB0_GATE_1WIRE (0x1 << 5)\n+#define PRCM_APB0_GATE_I2C (0x1 << 6)\n+\n+#define PRCM_APB0_RESET_PIO (0x1 << 0)\n+#define PRCM_APB0_RESET_IR (0x1 << 1)\n+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)\n+#define PRCM_APB0_RESET_P2WI (0x1 << 3)\n+#define PRCM_APB0_RESET_UART (0x1 << 4)\n+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)\n+#define PRCM_APB0_RESET_I2C (0x1 << 6)\n+\n+#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)\n+#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)\n+#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)\n+#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \\\n+\t__PRCM_PLL_CTRL_USB_CLK_SRC(0x3)\n+#define __PRCM_PLL_CTRL_USB_CLK_0 0x0\n+#define __PRCM_PLL_CTRL_USB_CLK_1 0x1\n+#define __PRCM_PLL_CTRL_USB_CLK_2 0x2\n+#define __PRCM_PLL_CTRL_USB_CLK_3 0x3\n+#define PRCM_PLL_CTRL_USB_CLK_0 \\\n+\t__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0)\n+#define PRCM_PLL_CTRL_USB_CLK_1 \\\n+\t__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1)\n+#define PRCM_PLL_CTRL_USB_CLK_2 \\\n+\t__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2)\n+#define PRCM_PLL_CTRL_USB_CLK_3 \\\n+\t__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3)\n+#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12)\n+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \\\n+\t__PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3)\n+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \\\n+\t__PRCM_PLL_CTRL_INT_PLL_IN_SEL(n)\n+#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20)\n+#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \\\n+\t__PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3)\n+#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0\n+#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1\n+#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2\n+#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3\n+#define PRCM_PLL_CTRL_HOSC_CLK_0 \\\n+\t__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0)\n+#define PRCM_PLL_CTRL_HOSC_CLK_1 \\\n+\t__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1)\n+#define PRCM_PLL_CTRL_HOSC_CLK_2 \\\n+\t__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2)\n+#define PRCM_PLL_CTRL_HOSC_CLK_3 \\\n+\t__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3)\n+#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24)\n+#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0)\n+#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1)\n+#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2)\n+#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3)\n+#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */\n+#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16)\n+#define PRCM_PLL_CTRL_LDO_OUT_MASK \\\n+\t__PRCM_PLL_CTRL_LDO_OUT(0x7)\n+/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */\n+#define PRCM_PLL_CTRL_LDO_OUT_L(n) \\\n+\t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)\n+#define PRCM_PLL_CTRL_LDO_OUT_H(n) \\\n+\t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)\n+#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \\\n+\t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)\n+#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \\\n+\t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)\n+#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)\n+#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)\n+\n+#define PRCM_CLK_1WIRE_GATE (0x1 << 31)\n+\n+#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0)\n+#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf)\n+#define __PRCM_CLK_MOD0_M_X(n) (n - 1)\n+#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n))\n+#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8)\n+#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7)\n+#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16)\n+#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3)\n+#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1)\n+#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n))\n+#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20)\n+#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7)\n+#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24)\n+#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7)\n+#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31)\n+\n+#define PRCM_APB0_RESET_PIO (0x1 << 0)\n+#define PRCM_APB0_RESET_IR (0x1 << 1)\n+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)\n+#define PRCM_APB0_RESET_P2WI (0x1 << 3)\n+#define PRCM_APB0_RESET_UART (0x1 << 4)\n+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)\n+#define PRCM_APB0_RESET_I2C (0x1 << 6)\n+\n+#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8)\n+#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7)\n+#define __PRCM_CLK_OUTD_M_X() ((n) - 1)\n+#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n))\n+#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20)\n+#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7)\n+#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1)\n+#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n)\n+#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24)\n+#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3)\n+#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0\n+#define __PRCM_CLK_OUTD_SRC_LOSC 0x1\n+#define __PRCM_CLK_OUTD_SRC_HOSC 0x2\n+#define __PRCM_CLK_OUTD_SRC_ERR 0x3\n+#define PRCM_CLK_OUTD_SRC_LOSC2 \\\n+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2)\n+#define PRCM_CLK_OUTD_SRC_LOSC \\\n+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC)\n+#define PRCM_CLK_OUTD_SRC_HOSC \\\n+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC)\n+#define PRCM_CLK_OUTD_SRC_ERR \\\n+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR)\n+#define PRCM_CLK_OUTD_EN (0x1 << 31)\n+\n+#define PRCM_CPU0_PWROFF (0x1 << 0)\n+#define PRCM_CPU1_PWROFF (0x1 << 1)\n+#define PRCM_CPU2_PWROFF (0x1 << 2)\n+#define PRCM_CPU3_PWROFF (0x1 << 3)\n+#define PRCM_CPU_ALL_PWROFF (0xf << 0)\n+\n+#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0)\n+#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1)\n+#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2)\n+#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3)\n+\n+#define PRCM_VDD_GPU_PWROFF (0x1 << 0)\n+\n+#define PRCM_VDD_SYS_RESET (0x1 << 0)\n+\n+#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0)\n+#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff)\n+\n+#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0)\n+#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff)\n+\n+#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)\n+#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)\n+\n+#define PRCM_SEC_SWITCH_APB0_CLK_NONSEC (0x1 << 0)\n+#define PRCM_SEC_SWITCH_PLL_CFG_NONSEC (0x1 << 1)\n+#define PRCM_SEC_SWITCH_PWR_GATE_NONSEC (0x1 << 2)\n+\n+#ifndef __ASSEMBLY__\n+#include <linux/compiler.h>\n+\n+struct sunxi_prcm_reg {\n+\tu32 cpus_cfg;\t\t/* 0x000 */\n+\tu8 res0[0x8];\t\t/* 0x004 */\n+\tu32 apb0_ratio;\t\t/* 0x00c */\n+\tu32 cpu0_cfg;\t\t/* 0x010 */\n+\tu32 cpu1_cfg;\t\t/* 0x014 */\n+\tu32 cpu2_cfg;\t\t/* 0x018 */\n+\tu32 cpu3_cfg;\t\t/* 0x01c */\n+\tu8 res1[0x8];\t\t/* 0x020 */\n+\tu32 apb0_gate;\t\t/* 0x028 */\n+\tu8 res2[0x14];\t\t/* 0x02c */\n+\tu32 pll_ctrl0;\t\t/* 0x040 */\n+\tu32 pll_ctrl1;\t\t/* 0x044 */\n+\tu8 res3[0x8];\t\t/* 0x048 */\n+\tu32 clk_1wire;\t\t/* 0x050 */\n+\tu32 clk_ir;\t\t/* 0x054 */\n+\tu8 res4[0x58];\t\t/* 0x058 */\n+\tu32 apb0_reset;\t\t/* 0x0b0 */\n+\tu8 res5[0x3c];\t\t/* 0x0b4 */\n+\tu32 clk_outd;\t\t/* 0x0f0 */\n+\tu8 res6[0xc];\t\t/* 0x0f4 */\n+\tu32 cpu_pwroff;\t\t/* 0x100 */\n+\tu8 res7[0xc];\t\t/* 0x104 */\n+\tu32 vdd_sys_pwroff;\t/* 0x110 */\n+\tu8 res8[0x4];\t\t/* 0x114 */\n+\tu32 gpu_pwroff;\t\t/* 0x118 */\n+\tu8 res9[0x4];\t\t/* 0x11c */\n+\tu32 vdd_pwr_reset;\t/* 0x120 */\n+\tu8 res10[0x1c];\t\t/* 0x124 */\n+\tu32 cpu_pwr_clamp[4];\t/* 0x140 but first one is actually unused */\n+\tu8 res11[0x30];\t\t/* 0x150 */\n+\tu32 dram_pwr;\t\t/* 0x180 */\n+\tu8 res12[0xc];\t\t/* 0x184 */\n+\tu32 dram_tst;\t\t/* 0x190 */\n+\tu8 res13[0x3c];\t\t/* 0x194 */\n+\tu32 prcm_sec_switch;\t/* 0x1d0 */\n+};\n+\n+void prcm_apb0_enable(u32 flags);\n+void prcm_apb0_disable(u32 flags);\n+\n+#endif /* __ASSEMBLY__ */\n+#endif /* _PRCM_H */\n", "prefixes": [ "05/17" ] }