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GET /api/patches/1415045/?format=api
{ "id": 1415045, "url": "http://patchwork.ozlabs.org/api/patches/1415045/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-10-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-10-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:31", "name": "[v1,09/50] mips: octeon: Add cvmx-dtx-defs.h header file", "commit_ref": "f3b97678275feb8a2b67356071a9ad8c1e395f4b", "pull_url": null, "state": "accepted", "archived": false, "hash": "0c222f81ce31c2d2927397f1e82447ff455e612d", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-10-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1415045/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1415045/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=wIUi96W9;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4CsxPw2s6Zz9sSn\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:41:40 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id CDBC1826C2;\n\tFri, 11 Dec 2020 17:38:47 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 39666827A4; Fri, 11 Dec 2020 17:07:49 +0100 (CET)", "from mx2.mailbox.org (mx2a.mailbox.org\n [IPv6:2001:67c:2050:104:0:2:25:2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 96D0282697\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:25 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id 8D107A0BBC;\n Fri, 11 Dec 2020 17:06:24 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de\n [80.241.56.116]) (amavisd-new, port 10030)\n with ESMTP id JCO98xYpwMzT; Fri, 11 Dec 2020 17:06:16 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607704728;\n\tbh=qVEQTnSfYo0o3IwFZYPkG4CMwp7jmGD3Pa6lTDCAUSw=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=wIUi96W9GBMoRT5sIRN11ZyPWDRP8t0f9TzNgXtuMSSmh7JQGipJX7rwuB7rNq37W\n\t nueubwVkdG16/wFxLtLoqYEGQOyTv5y7YvCfDr7S3hE6INWXsZNqSfcYeBzjh3GROx\n\t 6LYAw/3yWmstbR4wqLFX8G3a4s4G+Vx14Xwmw89mjGahQdbvwmAVbquT4oqbVlEeRG\n\t ak/y/T2eqv0PifydTIst03pr9TOgZUAdylQXlqvgI392BCVJeE7ScjAhCg8S7Ez7we\n\t 0F0toJmY8ZBShugoJNmPMUzbQkGAUU8XcpcOCLdebTPsrz01clLZTxElc+X68LAzXs\n\t pNNx9wa+IBagw==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 09/50] mips: octeon: Add cvmx-dtx-defs.h header file", "Date": "Fri, 11 Dec 2020 17:05:31 +0100", "Message-Id": "<20201211160612.1498780-10-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.74 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "72F14188D", "X-Rspamd-UID": "a8e67f", "X-Mailman-Approved-At": "Fri, 11 Dec 2020 17:38:11 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-dtx-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-dtx-defs.h | 6962 +++++++++++++++++\n 1 file changed, 6962 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-dtx-defs.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-dtx-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-dtx-defs.h\nnew file mode 100644\nindex 0000000000..afb581a5ea\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-dtx-defs.h\n@@ -0,0 +1,6962 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon dtx.\n+ */\n+\n+#ifndef __CVMX_DTX_DEFS_H__\n+#define __CVMX_DTX_DEFS_H__\n+\n+#define CVMX_DTX_AGL_BCST_RSP\t (0x00011800FE700080ull)\n+#define CVMX_DTX_AGL_CTL\t (0x00011800FE700060ull)\n+#define CVMX_DTX_AGL_DATX(offset) (0x00011800FE700040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_AGL_ENAX(offset) (0x00011800FE700020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_AGL_SELX(offset) (0x00011800FE700000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ASE_BCST_RSP\t (0x00011800FE6E8080ull)\n+#define CVMX_DTX_ASE_CTL\t (0x00011800FE6E8060ull)\n+#define CVMX_DTX_ASE_DATX(offset) (0x00011800FE6E8040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ASE_ENAX(offset) (0x00011800FE6E8020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ASE_SELX(offset) (0x00011800FE6E8000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BBX1I_BCST_RSP\t (0x00011800FED78080ull)\n+#define CVMX_DTX_BBX1I_CTL\t (0x00011800FED78060ull)\n+#define CVMX_DTX_BBX1I_DATX(offset) (0x00011800FED78040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BBX1I_ENAX(offset) (0x00011800FED78020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BBX1I_SELX(offset) (0x00011800FED78000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BBX2I_BCST_RSP\t (0x00011800FED80080ull)\n+#define CVMX_DTX_BBX2I_CTL\t (0x00011800FED80060ull)\n+#define CVMX_DTX_BBX2I_DATX(offset) (0x00011800FED80040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BBX2I_ENAX(offset) (0x00011800FED80020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BBX2I_SELX(offset) (0x00011800FED80000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BBX3I_BCST_RSP\t (0x00011800FED88080ull)\n+#define CVMX_DTX_BBX3I_CTL\t (0x00011800FED88060ull)\n+#define CVMX_DTX_BBX3I_DATX(offset) (0x00011800FED88040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BBX3I_ENAX(offset) (0x00011800FED88020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BBX3I_SELX(offset) (0x00011800FED88000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BCH_BCST_RSP\t (0x00011800FE388080ull)\n+#define CVMX_DTX_BCH_CTL\t (0x00011800FE388060ull)\n+#define CVMX_DTX_BCH_DATX(offset) (0x00011800FE388040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BCH_ENAX(offset) (0x00011800FE388020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BCH_SELX(offset) (0x00011800FE388000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BGXX_BCST_RSP(offset) (0x00011800FE700080ull + ((offset) & 7) * 32768)\n+#define CVMX_DTX_BGXX_CTL(offset) (0x00011800FE700060ull + ((offset) & 7) * 32768)\n+#define CVMX_DTX_BGXX_DATX(offset, block_id) \\\n+\t(0x00011800FE700040ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)\n+#define CVMX_DTX_BGXX_ENAX(offset, block_id) \\\n+\t(0x00011800FE700020ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)\n+#define CVMX_DTX_BGXX_SELX(offset, block_id) \\\n+\t(0x00011800FE700000ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)\n+#define CVMX_DTX_BROADCAST_CTL\t\t(0x00011800FE7F0060ull)\n+#define CVMX_DTX_BROADCAST_ENAX(offset) (0x00011800FE7F0020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BROADCAST_SELX(offset) (0x00011800FE7F0000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BTS_BCST_RSP\t\t(0x00011800FE5B0080ull)\n+#define CVMX_DTX_BTS_CTL\t\t(0x00011800FE5B0060ull)\n+#define CVMX_DTX_BTS_DATX(offset)\t(0x00011800FE5B0040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BTS_ENAX(offset)\t(0x00011800FE5B0020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_BTS_SELX(offset)\t(0x00011800FE5B0000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_CIU_BCST_RSP\t\t(0x00011800FE808080ull)\n+#define CVMX_DTX_CIU_CTL\t\t(0x00011800FE808060ull)\n+#define CVMX_DTX_CIU_DATX(offset)\t(0x00011800FE808040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_CIU_ENAX(offset)\t(0x00011800FE808020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_CIU_SELX(offset)\t(0x00011800FE808000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_DENC_BCST_RSP\t\t(0x00011800FED48080ull)\n+#define CVMX_DTX_DENC_CTL\t\t(0x00011800FED48060ull)\n+#define CVMX_DTX_DENC_DATX(offset)\t(0x00011800FED48040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_DENC_ENAX(offset)\t(0x00011800FED48020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_DENC_SELX(offset)\t(0x00011800FED48000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_DFA_BCST_RSP\t\t(0x00011800FE1B8080ull)\n+#define CVMX_DTX_DFA_CTL\t\t(0x00011800FE1B8060ull)\n+#define CVMX_DTX_DFA_DATX(offset)\t(0x00011800FE1B8040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_DFA_ENAX(offset)\t(0x00011800FE1B8020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_DFA_SELX(offset)\t(0x00011800FE1B8000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_DLFE_BCST_RSP\t\t(0x00011800FED18080ull)\n+#define CVMX_DTX_DLFE_CTL\t\t(0x00011800FED18060ull)\n+#define CVMX_DTX_DLFE_DATX(offset)\t(0x00011800FED18040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_DLFE_ENAX(offset)\t(0x00011800FED18020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_DLFE_SELX(offset)\t(0x00011800FED18000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_DPI_BCST_RSP\t\t(0x00011800FEEF8080ull)\n+#define CVMX_DTX_DPI_CTL\t\t(0x00011800FEEF8060ull)\n+#define CVMX_DTX_DPI_DATX(offset)\t(0x00011800FEEF8040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_DPI_ENAX(offset)\t(0x00011800FEEF8020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_DPI_SELX(offset)\t(0x00011800FEEF8000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_FDEQX_BCST_RSP(offset) (0x00011800FED30080ull + ((offset) & 1) * 0x20000ull)\n+#define CVMX_DTX_FDEQX_CTL(offset)\t(0x00011800FED30060ull + ((offset) & 1) * 0x20000ull)\n+#define CVMX_DTX_FDEQX_DATX(offset, block_id) \\\n+\t(0x00011800FED30040ull + (((offset) & 1) + ((block_id) & 1) * 0x4000ull) * 8)\n+#define CVMX_DTX_FDEQX_ENAX(offset, block_id) \\\n+\t(0x00011800FED30020ull + (((offset) & 1) + ((block_id) & 1) * 0x4000ull) * 8)\n+#define CVMX_DTX_FDEQX_SELX(offset, block_id) \\\n+\t(0x00011800FED30000ull + (((offset) & 1) + ((block_id) & 1) * 0x4000ull) * 8)\n+#define CVMX_DTX_FPA_BCST_RSP CVMX_DTX_FPA_BCST_RSP_FUNC()\n+static inline u64 CVMX_DTX_FPA_BCST_RSP_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FE940080ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FE940080ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE940080ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE140080ull;\n+\t}\n+\treturn 0x00011800FE940080ull;\n+}\n+\n+#define CVMX_DTX_FPA_CTL CVMX_DTX_FPA_CTL_FUNC()\n+static inline u64 CVMX_DTX_FPA_CTL_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FE940060ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FE940060ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE940060ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE140060ull;\n+\t}\n+\treturn 0x00011800FE940060ull;\n+}\n+\n+static inline u64 CVMX_DTX_FPA_DATX(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FE940040ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FE940040ull + (offset) * 8;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE940040ull + (offset) * 8;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE140040ull + (offset) * 8;\n+\t}\n+\treturn 0x00011800FE940040ull + (offset) * 8;\n+}\n+\n+static inline u64 CVMX_DTX_FPA_ENAX(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FE940020ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FE940020ull + (offset) * 8;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE940020ull + (offset) * 8;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE140020ull + (offset) * 8;\n+\t}\n+\treturn 0x00011800FE940020ull + (offset) * 8;\n+}\n+\n+static inline u64 CVMX_DTX_FPA_SELX(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FE940000ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FE940000ull + (offset) * 8;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE940000ull + (offset) * 8;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE140000ull + (offset) * 8;\n+\t}\n+\treturn 0x00011800FE940000ull + (offset) * 8;\n+}\n+\n+#define CVMX_DTX_GMXX_BCST_RSP(offset) (0x00011800FE040080ull + ((offset) & 1) * 0x40000ull)\n+#define CVMX_DTX_GMXX_CTL(offset) (0x00011800FE040060ull + ((offset) & 1) * 0x40000ull)\n+#define CVMX_DTX_GMXX_DATX(offset, block_id) \\\n+\t(0x00011800FE040040ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)\n+#define CVMX_DTX_GMXX_ENAX(offset, block_id) \\\n+\t(0x00011800FE040020ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)\n+#define CVMX_DTX_GMXX_SELX(offset, block_id) \\\n+\t(0x00011800FE040000ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)\n+#define CVMX_DTX_GSERX_BCST_RSP(offset) (0x00011800FE480080ull + ((offset) & 15) * 32768)\n+#define CVMX_DTX_GSERX_CTL(offset)\t(0x00011800FE480060ull + ((offset) & 15) * 32768)\n+#define CVMX_DTX_GSERX_DATX(offset, block_id) \\\n+\t(0x00011800FE480040ull + (((offset) & 1) + ((block_id) & 15) * 0x1000ull) * 8)\n+#define CVMX_DTX_GSERX_ENAX(offset, block_id) \\\n+\t(0x00011800FE480020ull + (((offset) & 1) + ((block_id) & 15) * 0x1000ull) * 8)\n+#define CVMX_DTX_GSERX_SELX(offset, block_id) \\\n+\t(0x00011800FE480000ull + (((offset) & 1) + ((block_id) & 15) * 0x1000ull) * 8)\n+#define CVMX_DTX_HNA_BCST_RSP\t\t (0x00011800FE238080ull)\n+#define CVMX_DTX_HNA_CTL\t\t (0x00011800FE238060ull)\n+#define CVMX_DTX_HNA_DATX(offset)\t (0x00011800FE238040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_HNA_ENAX(offset)\t (0x00011800FE238020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_HNA_SELX(offset)\t (0x00011800FE238000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ILA_BCST_RSP\t\t (0x00011800FE0B8080ull)\n+#define CVMX_DTX_ILA_CTL\t\t (0x00011800FE0B8060ull)\n+#define CVMX_DTX_ILA_DATX(offset)\t (0x00011800FE0B8040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ILA_ENAX(offset)\t (0x00011800FE0B8020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ILA_SELX(offset)\t (0x00011800FE0B8000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ILK_BCST_RSP\t\t (0x00011800FE0A0080ull)\n+#define CVMX_DTX_ILK_CTL\t\t (0x00011800FE0A0060ull)\n+#define CVMX_DTX_ILK_DATX(offset)\t (0x00011800FE0A0040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ILK_ENAX(offset)\t (0x00011800FE0A0020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ILK_SELX(offset)\t (0x00011800FE0A0000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_IOBN_BCST_RSP\t\t (0x00011800FE780080ull)\n+#define CVMX_DTX_IOBN_CTL\t\t (0x00011800FE780060ull)\n+#define CVMX_DTX_IOBN_DATX(offset)\t (0x00011800FE780040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_IOBN_ENAX(offset)\t (0x00011800FE780020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_IOBN_SELX(offset)\t (0x00011800FE780000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_IOBP_BCST_RSP\t\t (0x00011800FE7A0080ull)\n+#define CVMX_DTX_IOBP_CTL\t\t (0x00011800FE7A0060ull)\n+#define CVMX_DTX_IOBP_DATX(offset)\t (0x00011800FE7A0040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_IOBP_ENAX(offset)\t (0x00011800FE7A0020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_IOBP_SELX(offset)\t (0x00011800FE7A0000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_IOB_BCST_RSP\t\t (0x00011800FE780080ull)\n+#define CVMX_DTX_IOB_CTL\t\t (0x00011800FE780060ull)\n+#define CVMX_DTX_IOB_DATX(offset)\t (0x00011800FE780040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_IOB_ENAX(offset)\t (0x00011800FE780020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_IOB_SELX(offset)\t (0x00011800FE780000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_IPD_BCST_RSP\t\t (0x00011800FE278080ull)\n+#define CVMX_DTX_IPD_CTL\t\t (0x00011800FE278060ull)\n+#define CVMX_DTX_IPD_DATX(offset)\t (0x00011800FE278040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_IPD_ENAX(offset)\t (0x00011800FE278020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_IPD_SELX(offset)\t (0x00011800FE278000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_KEY_BCST_RSP\t\t (0x00011800FE100080ull)\n+#define CVMX_DTX_KEY_CTL\t\t (0x00011800FE100060ull)\n+#define CVMX_DTX_KEY_DATX(offset)\t (0x00011800FE100040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_KEY_ENAX(offset)\t (0x00011800FE100020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_KEY_SELX(offset)\t (0x00011800FE100000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_L2C_CBCX_BCST_RSP(offset) (0x00011800FE420080ull + ((offset) & 3) * 32768)\n+#define CVMX_DTX_L2C_CBCX_CTL(offset)\t (0x00011800FE420060ull + ((offset) & 3) * 32768)\n+#define CVMX_DTX_L2C_CBCX_DATX(offset, block_id) \\\n+\t(0x00011800FE420040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_L2C_CBCX_ENAX(offset, block_id) \\\n+\t(0x00011800FE420020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_L2C_CBCX_SELX(offset, block_id) \\\n+\t(0x00011800FE420000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_L2C_MCIX_BCST_RSP(offset) (0x00011800FE2E0080ull + ((offset) & 3) * 32768)\n+#define CVMX_DTX_L2C_MCIX_CTL(offset)\t (0x00011800FE2E0060ull + ((offset) & 3) * 32768)\n+#define CVMX_DTX_L2C_MCIX_DATX(offset, block_id) \\\n+\t(0x00011800FE2E0040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_L2C_MCIX_ENAX(offset, block_id) \\\n+\t(0x00011800FE2E0020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_L2C_MCIX_SELX(offset, block_id) \\\n+\t(0x00011800FE2E0000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_L2C_TADX_BCST_RSP(offset) (0x00011800FE240080ull + ((offset) & 7) * 32768)\n+#define CVMX_DTX_L2C_TADX_CTL(offset)\t (0x00011800FE240060ull + ((offset) & 7) * 32768)\n+#define CVMX_DTX_L2C_TADX_DATX(offset, block_id) \\\n+\t(0x00011800FE240040ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)\n+#define CVMX_DTX_L2C_TADX_ENAX(offset, block_id) \\\n+\t(0x00011800FE240020ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)\n+#define CVMX_DTX_L2C_TADX_SELX(offset, block_id) \\\n+\t(0x00011800FE240000ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)\n+#define CVMX_DTX_LAPX_BCST_RSP(offset) (0x00011800FE060080ull + ((offset) & 1) * 32768)\n+#define CVMX_DTX_LAPX_CTL(offset) (0x00011800FE060060ull + ((offset) & 1) * 32768)\n+#define CVMX_DTX_LAPX_DATX(offset, block_id) \\\n+\t(0x00011800FE060040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_LAPX_ENAX(offset, block_id) \\\n+\t(0x00011800FE060020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_LAPX_SELX(offset, block_id) \\\n+\t(0x00011800FE060000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_LBK_BCST_RSP\t (0x00011800FE090080ull)\n+#define CVMX_DTX_LBK_CTL\t (0x00011800FE090060ull)\n+#define CVMX_DTX_LBK_DATX(offset) (0x00011800FE090040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_LBK_ENAX(offset) (0x00011800FE090020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_LBK_SELX(offset) (0x00011800FE090000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_LMCX_BCST_RSP(offset) (0x00011800FE440080ull + ((offset) & 3) * 32768)\n+#define CVMX_DTX_LMCX_CTL(offset) (0x00011800FE440060ull + ((offset) & 3) * 32768)\n+#define CVMX_DTX_LMCX_DATX(offset, block_id) \\\n+\t(0x00011800FE440040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_LMCX_ENAX(offset, block_id) \\\n+\t(0x00011800FE440020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_LMCX_SELX(offset, block_id) \\\n+\t(0x00011800FE440000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_MDBX_BCST_RSP(offset) (0x00011800FEC00080ull + ((offset) & 31) * 32768)\n+#define CVMX_DTX_MDBX_CTL(offset) (0x00011800FEC00060ull + ((offset) & 31) * 32768)\n+#define CVMX_DTX_MDBX_DATX(offset, block_id) \\\n+\t(0x00011800FEC00040ull + (((offset) & 1) + ((block_id) & 31) * 0x1000ull) * 8)\n+#define CVMX_DTX_MDBX_ENAX(offset, block_id) \\\n+\t(0x00011800FEC00020ull + (((offset) & 1) + ((block_id) & 31) * 0x1000ull) * 8)\n+#define CVMX_DTX_MDBX_SELX(offset, block_id) \\\n+\t(0x00011800FEC00000ull + (((offset) & 1) + ((block_id) & 31) * 0x1000ull) * 8)\n+#define CVMX_DTX_MHBW_BCST_RSP\t\t (0x00011800FE598080ull)\n+#define CVMX_DTX_MHBW_CTL\t\t (0x00011800FE598060ull)\n+#define CVMX_DTX_MHBW_DATX(offset)\t (0x00011800FE598040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_MHBW_ENAX(offset)\t (0x00011800FE598020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_MHBW_SELX(offset)\t (0x00011800FE598000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_MIO_BCST_RSP\t\t (0x00011800FE000080ull)\n+#define CVMX_DTX_MIO_CTL\t\t (0x00011800FE000060ull)\n+#define CVMX_DTX_MIO_DATX(offset)\t (0x00011800FE000040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_MIO_ENAX(offset)\t (0x00011800FE000020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_MIO_SELX(offset)\t (0x00011800FE000000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_OCX_BOT_BCST_RSP\t (0x00011800FE198080ull)\n+#define CVMX_DTX_OCX_BOT_CTL\t\t (0x00011800FE198060ull)\n+#define CVMX_DTX_OCX_BOT_DATX(offset)\t (0x00011800FE198040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_OCX_BOT_ENAX(offset)\t (0x00011800FE198020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_OCX_BOT_SELX(offset)\t (0x00011800FE198000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_OCX_LNKX_BCST_RSP(offset) (0x00011800FE180080ull + ((offset) & 3) * 32768)\n+#define CVMX_DTX_OCX_LNKX_CTL(offset)\t (0x00011800FE180060ull + ((offset) & 3) * 32768)\n+#define CVMX_DTX_OCX_LNKX_DATX(offset, block_id) \\\n+\t(0x00011800FE180040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_OCX_LNKX_ENAX(offset, block_id) \\\n+\t(0x00011800FE180020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_OCX_LNKX_SELX(offset, block_id) \\\n+\t(0x00011800FE180000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_OCX_OLEX_BCST_RSP(offset) (0x00011800FE1A0080ull + ((offset) & 3) * 32768)\n+#define CVMX_DTX_OCX_OLEX_CTL(offset)\t (0x00011800FE1A0060ull + ((offset) & 3) * 32768)\n+#define CVMX_DTX_OCX_OLEX_DATX(offset, block_id) \\\n+\t(0x00011800FE1A0040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_OCX_OLEX_ENAX(offset, block_id) \\\n+\t(0x00011800FE1A0020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_OCX_OLEX_SELX(offset, block_id) \\\n+\t(0x00011800FE1A0000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_OCX_TOP_BCST_RSP (0x00011800FE088080ull)\n+#define CVMX_DTX_OCX_TOP_CTL\t (0x00011800FE088060ull)\n+#define CVMX_DTX_OCX_TOP_DATX(offset) (0x00011800FE088040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_OCX_TOP_ENAX(offset) (0x00011800FE088020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_OCX_TOP_SELX(offset) (0x00011800FE088000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_OSM_BCST_RSP\t CVMX_DTX_OSM_BCST_RSP_FUNC()\n+static inline u64 CVMX_DTX_OSM_BCST_RSP_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FE6E0080ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FE6E0080ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FEEE0080ull;\n+\t}\n+\treturn 0x00011800FE6E0080ull;\n+}\n+\n+#define CVMX_DTX_OSM_CTL CVMX_DTX_OSM_CTL_FUNC()\n+static inline u64 CVMX_DTX_OSM_CTL_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FE6E0060ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FE6E0060ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FEEE0060ull;\n+\t}\n+\treturn 0x00011800FE6E0060ull;\n+}\n+\n+static inline u64 CVMX_DTX_OSM_DATX(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FE6E0040ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FE6E0040ull + (offset) * 8;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FEEE0040ull + (offset) * 8;\n+\t}\n+\treturn 0x00011800FE6E0040ull + (offset) * 8;\n+}\n+\n+static inline u64 CVMX_DTX_OSM_ENAX(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FE6E0020ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FE6E0020ull + (offset) * 8;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FEEE0020ull + (offset) * 8;\n+\t}\n+\treturn 0x00011800FE6E0020ull + (offset) * 8;\n+}\n+\n+static inline u64 CVMX_DTX_OSM_SELX(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FE6E0000ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FE6E0000ull + (offset) * 8;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FEEE0000ull + (offset) * 8;\n+\t}\n+\treturn 0x00011800FE6E0000ull + (offset) * 8;\n+}\n+\n+#define CVMX_DTX_PCSX_BCST_RSP(offset) (0x00011800FE580080ull + ((offset) & 1) * 0x40000ull)\n+#define CVMX_DTX_PCSX_CTL(offset) (0x00011800FE580060ull + ((offset) & 1) * 0x40000ull)\n+#define CVMX_DTX_PCSX_DATX(offset, block_id) \\\n+\t(0x00011800FE580040ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)\n+#define CVMX_DTX_PCSX_ENAX(offset, block_id) \\\n+\t(0x00011800FE580020ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)\n+#define CVMX_DTX_PCSX_SELX(offset, block_id) \\\n+\t(0x00011800FE580000ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)\n+#define CVMX_DTX_PEMX_BCST_RSP(offset) (0x00011800FE600080ull + ((offset) & 3) * 32768)\n+#define CVMX_DTX_PEMX_CTL(offset) (0x00011800FE600060ull + ((offset) & 3) * 32768)\n+#define CVMX_DTX_PEMX_DATX(offset, block_id) \\\n+\t(0x00011800FE600040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_PEMX_ENAX(offset, block_id) \\\n+\t(0x00011800FE600020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_PEMX_SELX(offset, block_id) \\\n+\t(0x00011800FE600000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)\n+#define CVMX_DTX_PIP_BCST_RSP\t (0x00011800FE500080ull)\n+#define CVMX_DTX_PIP_CTL\t (0x00011800FE500060ull)\n+#define CVMX_DTX_PIP_DATX(offset) (0x00011800FE500040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PIP_ENAX(offset) (0x00011800FE500020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PIP_SELX(offset) (0x00011800FE500000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PKI_PBE_BCST_RSP (0x00011800FE228080ull)\n+#define CVMX_DTX_PKI_PBE_CTL\t (0x00011800FE228060ull)\n+#define CVMX_DTX_PKI_PBE_DATX(offset) (0x00011800FE228040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PKI_PBE_ENAX(offset) (0x00011800FE228020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PKI_PBE_SELX(offset) (0x00011800FE228000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PKI_PFE_BCST_RSP (0x00011800FE220080ull)\n+#define CVMX_DTX_PKI_PFE_CTL\t (0x00011800FE220060ull)\n+#define CVMX_DTX_PKI_PFE_DATX(offset) (0x00011800FE220040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PKI_PFE_ENAX(offset) (0x00011800FE220020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PKI_PFE_SELX(offset) (0x00011800FE220000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PKI_PIX_BCST_RSP (0x00011800FE230080ull)\n+#define CVMX_DTX_PKI_PIX_CTL\t (0x00011800FE230060ull)\n+#define CVMX_DTX_PKI_PIX_DATX(offset) (0x00011800FE230040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PKI_PIX_ENAX(offset) (0x00011800FE230020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PKI_PIX_SELX(offset) (0x00011800FE230000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PKO_BCST_RSP\t CVMX_DTX_PKO_BCST_RSP_FUNC()\n+static inline u64 CVMX_DTX_PKO_BCST_RSP_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FEAA0080ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FEAA0080ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FEAA0080ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE280080ull;\n+\t}\n+\treturn 0x00011800FEAA0080ull;\n+}\n+\n+#define CVMX_DTX_PKO_CTL CVMX_DTX_PKO_CTL_FUNC()\n+static inline u64 CVMX_DTX_PKO_CTL_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FEAA0060ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FEAA0060ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FEAA0060ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE280060ull;\n+\t}\n+\treturn 0x00011800FEAA0060ull;\n+}\n+\n+static inline u64 CVMX_DTX_PKO_DATX(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FEAA0040ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FEAA0040ull + (offset) * 8;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FEAA0040ull + (offset) * 8;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE280040ull + (offset) * 8;\n+\t}\n+\treturn 0x00011800FEAA0040ull + (offset) * 8;\n+}\n+\n+static inline u64 CVMX_DTX_PKO_ENAX(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FEAA0020ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FEAA0020ull + (offset) * 8;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FEAA0020ull + (offset) * 8;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE280020ull + (offset) * 8;\n+\t}\n+\treturn 0x00011800FEAA0020ull + (offset) * 8;\n+}\n+\n+static inline u64 CVMX_DTX_PKO_SELX(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800FEAA0000ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800FEAA0000ull + (offset) * 8;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FEAA0000ull + (offset) * 8;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800FE280000ull + (offset) * 8;\n+\t}\n+\treturn 0x00011800FEAA0000ull + (offset) * 8;\n+}\n+\n+#define CVMX_DTX_PNBDX_BCST_RSP(offset) (0x00011800FED90080ull + ((offset) & 1) * 32768)\n+#define CVMX_DTX_PNBDX_CTL(offset)\t(0x00011800FED90060ull + ((offset) & 1) * 32768)\n+#define CVMX_DTX_PNBDX_DATX(offset, block_id) \\\n+\t(0x00011800FED90040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_PNBDX_ENAX(offset, block_id) \\\n+\t(0x00011800FED90020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_PNBDX_SELX(offset, block_id) \\\n+\t(0x00011800FED90000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_PNBX_BCST_RSP(offset) (0x00011800FE580080ull + ((offset) & 1) * 32768)\n+#define CVMX_DTX_PNBX_CTL(offset) (0x00011800FE580060ull + ((offset) & 1) * 32768)\n+#define CVMX_DTX_PNBX_DATX(offset, block_id) \\\n+\t(0x00011800FE580040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_PNBX_ENAX(offset, block_id) \\\n+\t(0x00011800FE580020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_PNBX_SELX(offset, block_id) \\\n+\t(0x00011800FE580000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_POW_BCST_RSP\t\t(0x00011800FE338080ull)\n+#define CVMX_DTX_POW_CTL\t\t(0x00011800FE338060ull)\n+#define CVMX_DTX_POW_DATX(offset)\t(0x00011800FE338040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_POW_ENAX(offset)\t(0x00011800FE338020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_POW_SELX(offset)\t(0x00011800FE338000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PRCH_BCST_RSP\t\t(0x00011800FED00080ull)\n+#define CVMX_DTX_PRCH_CTL\t\t(0x00011800FED00060ull)\n+#define CVMX_DTX_PRCH_DATX(offset)\t(0x00011800FED00040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PRCH_ENAX(offset)\t(0x00011800FED00020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PRCH_SELX(offset)\t(0x00011800FED00000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PSM_BCST_RSP\t\t(0x00011800FEEA0080ull)\n+#define CVMX_DTX_PSM_CTL\t\t(0x00011800FEEA0060ull)\n+#define CVMX_DTX_PSM_DATX(offset)\t(0x00011800FEEA0040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PSM_ENAX(offset)\t(0x00011800FEEA0020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_PSM_SELX(offset)\t(0x00011800FEEA0000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RAD_BCST_RSP\t\t(0x00011800FE380080ull)\n+#define CVMX_DTX_RAD_CTL\t\t(0x00011800FE380060ull)\n+#define CVMX_DTX_RAD_DATX(offset)\t(0x00011800FE380040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RAD_ENAX(offset)\t(0x00011800FE380020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RAD_SELX(offset)\t(0x00011800FE380000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RDEC_BCST_RSP\t\t(0x00011800FED68080ull)\n+#define CVMX_DTX_RDEC_CTL\t\t(0x00011800FED68060ull)\n+#define CVMX_DTX_RDEC_DATX(offset)\t(0x00011800FED68040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RDEC_ENAX(offset)\t(0x00011800FED68020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RDEC_SELX(offset)\t(0x00011800FED68000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RFIF_BCST_RSP\t\t(0x00011800FE6A8080ull)\n+#define CVMX_DTX_RFIF_CTL\t\t(0x00011800FE6A8060ull)\n+#define CVMX_DTX_RFIF_DATX(offset)\t(0x00011800FE6A8040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RFIF_ENAX(offset)\t(0x00011800FE6A8020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RFIF_SELX(offset)\t(0x00011800FE6A8000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RMAP_BCST_RSP\t\t(0x00011800FED40080ull)\n+#define CVMX_DTX_RMAP_CTL\t\t(0x00011800FED40060ull)\n+#define CVMX_DTX_RMAP_DATX(offset)\t(0x00011800FED40040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RMAP_ENAX(offset)\t(0x00011800FED40020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RMAP_SELX(offset)\t(0x00011800FED40000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RNM_BCST_RSP\t\t(0x00011800FE200080ull)\n+#define CVMX_DTX_RNM_CTL\t\t(0x00011800FE200060ull)\n+#define CVMX_DTX_RNM_DATX(offset)\t(0x00011800FE200040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RNM_ENAX(offset)\t(0x00011800FE200020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RNM_SELX(offset)\t(0x00011800FE200000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RST_BCST_RSP\t\t(0x00011800FE030080ull)\n+#define CVMX_DTX_RST_CTL\t\t(0x00011800FE030060ull)\n+#define CVMX_DTX_RST_DATX(offset)\t(0x00011800FE030040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RST_ENAX(offset)\t(0x00011800FE030020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_RST_SELX(offset)\t(0x00011800FE030000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_SATA_BCST_RSP\t\t(0x00011800FE360080ull)\n+#define CVMX_DTX_SATA_CTL\t\t(0x00011800FE360060ull)\n+#define CVMX_DTX_SATA_DATX(offset)\t(0x00011800FE360040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_SATA_ENAX(offset)\t(0x00011800FE360020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_SATA_SELX(offset)\t(0x00011800FE360000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_SLI_BCST_RSP\t\t(0x00011800FE8F8080ull)\n+#define CVMX_DTX_SLI_CTL\t\t(0x00011800FE8F8060ull)\n+#define CVMX_DTX_SLI_DATX(offset)\t(0x00011800FE8F8040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_SLI_ENAX(offset)\t(0x00011800FE8F8020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_SLI_SELX(offset)\t(0x00011800FE8F8000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_SPEM_BCST_RSP\t\t(0x00011800FE600080ull)\n+#define CVMX_DTX_SPEM_CTL\t\t(0x00011800FE600060ull)\n+#define CVMX_DTX_SPEM_DATX(offset)\t(0x00011800FE600040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_SPEM_ENAX(offset)\t(0x00011800FE600020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_SPEM_SELX(offset)\t(0x00011800FE600000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_SRIOX_BCST_RSP(offset) (0x00011800FE640080ull + ((offset) & 1) * 32768)\n+#define CVMX_DTX_SRIOX_CTL(offset)\t(0x00011800FE640060ull + ((offset) & 1) * 32768)\n+#define CVMX_DTX_SRIOX_DATX(offset, block_id) \\\n+\t(0x00011800FE640040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_SRIOX_ENAX(offset, block_id) \\\n+\t(0x00011800FE640020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_SRIOX_SELX(offset, block_id) \\\n+\t(0x00011800FE640000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_SSO_BCST_RSP\t\t (0x00011800FEB38080ull)\n+#define CVMX_DTX_SSO_CTL\t\t (0x00011800FEB38060ull)\n+#define CVMX_DTX_SSO_DATX(offset)\t (0x00011800FEB38040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_SSO_ENAX(offset)\t (0x00011800FEB38020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_SSO_SELX(offset)\t (0x00011800FEB38000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_TDEC_BCST_RSP\t\t (0x00011800FED60080ull)\n+#define CVMX_DTX_TDEC_CTL\t\t (0x00011800FED60060ull)\n+#define CVMX_DTX_TDEC_DATX(offset)\t (0x00011800FED60040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_TDEC_ENAX(offset)\t (0x00011800FED60020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_TDEC_SELX(offset)\t (0x00011800FED60000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_TIM_BCST_RSP\t\t (0x00011800FE2C0080ull)\n+#define CVMX_DTX_TIM_CTL\t\t (0x00011800FE2C0060ull)\n+#define CVMX_DTX_TIM_DATX(offset)\t (0x00011800FE2C0040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_TIM_ENAX(offset)\t (0x00011800FE2C0020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_TIM_SELX(offset)\t (0x00011800FE2C0000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ULFE_BCST_RSP\t\t (0x00011800FED08080ull)\n+#define CVMX_DTX_ULFE_CTL\t\t (0x00011800FED08060ull)\n+#define CVMX_DTX_ULFE_DATX(offset)\t (0x00011800FED08040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ULFE_ENAX(offset)\t (0x00011800FED08020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ULFE_SELX(offset)\t (0x00011800FED08000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_USBDRDX_BCST_RSP(offset) (0x00011800FE340080ull + ((offset) & 1) * 32768)\n+#define CVMX_DTX_USBDRDX_CTL(offset)\t (0x00011800FE340060ull + ((offset) & 1) * 32768)\n+#define CVMX_DTX_USBDRDX_DATX(offset, block_id) \\\n+\t(0x00011800FE340040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_USBDRDX_ENAX(offset, block_id) \\\n+\t(0x00011800FE340020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_USBDRDX_SELX(offset, block_id) \\\n+\t(0x00011800FE340000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)\n+#define CVMX_DTX_USBHX_BCST_RSP(offset) (0x00011800FE340080ull)\n+#define CVMX_DTX_USBHX_CTL(offset)\t(0x00011800FE340060ull)\n+#define CVMX_DTX_USBHX_DATX(offset, block_id) \\\n+\t(0x00011800FE340040ull + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)\n+#define CVMX_DTX_USBHX_ENAX(offset, block_id) \\\n+\t(0x00011800FE340020ull + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)\n+#define CVMX_DTX_USBHX_SELX(offset, block_id) \\\n+\t(0x00011800FE340000ull + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)\n+#define CVMX_DTX_VDEC_BCST_RSP\t (0x00011800FED70080ull)\n+#define CVMX_DTX_VDEC_CTL\t (0x00011800FED70060ull)\n+#define CVMX_DTX_VDEC_DATX(offset) (0x00011800FED70040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_VDEC_ENAX(offset) (0x00011800FED70020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_VDEC_SELX(offset) (0x00011800FED70000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WPSE_BCST_RSP\t (0x00011800FED10080ull)\n+#define CVMX_DTX_WPSE_CTL\t (0x00011800FED10060ull)\n+#define CVMX_DTX_WPSE_DATX(offset) (0x00011800FED10040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WPSE_ENAX(offset) (0x00011800FED10020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WPSE_SELX(offset) (0x00011800FED10000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WRCE_BCST_RSP\t (0x00011800FED38080ull)\n+#define CVMX_DTX_WRCE_CTL\t (0x00011800FED38060ull)\n+#define CVMX_DTX_WRCE_DATX(offset) (0x00011800FED38040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WRCE_ENAX(offset) (0x00011800FED38020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WRCE_SELX(offset) (0x00011800FED38000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WRDE_BCST_RSP\t (0x00011800FED58080ull)\n+#define CVMX_DTX_WRDE_CTL\t (0x00011800FED58060ull)\n+#define CVMX_DTX_WRDE_DATX(offset) (0x00011800FED58040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WRDE_ENAX(offset) (0x00011800FED58020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WRDE_SELX(offset) (0x00011800FED58000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WRSE_BCST_RSP\t (0x00011800FED28080ull)\n+#define CVMX_DTX_WRSE_CTL\t (0x00011800FED28060ull)\n+#define CVMX_DTX_WRSE_DATX(offset) (0x00011800FED28040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WRSE_ENAX(offset) (0x00011800FED28020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WRSE_SELX(offset) (0x00011800FED28000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WTXE_BCST_RSP\t (0x00011800FED20080ull)\n+#define CVMX_DTX_WTXE_CTL\t (0x00011800FED20060ull)\n+#define CVMX_DTX_WTXE_DATX(offset) (0x00011800FED20040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WTXE_ENAX(offset) (0x00011800FED20020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_WTXE_SELX(offset) (0x00011800FED20000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_XCV_BCST_RSP\t (0x00011800FE6D8080ull)\n+#define CVMX_DTX_XCV_CTL\t (0x00011800FE6D8060ull)\n+#define CVMX_DTX_XCV_DATX(offset) (0x00011800FE6D8040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_XCV_ENAX(offset) (0x00011800FE6D8020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_XCV_SELX(offset) (0x00011800FE6D8000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_XSX_BCST_RSP\t (0x00011800FE5A8080ull)\n+#define CVMX_DTX_XSX_CTL\t (0x00011800FE5A8060ull)\n+#define CVMX_DTX_XSX_DATX(offset) (0x00011800FE5A8040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_XSX_ENAX(offset) (0x00011800FE5A8020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_XSX_SELX(offset) (0x00011800FE5A8000ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ZIP_BCST_RSP\t (0x00011800FE1C0080ull)\n+#define CVMX_DTX_ZIP_CTL\t (0x00011800FE1C0060ull)\n+#define CVMX_DTX_ZIP_DATX(offset) (0x00011800FE1C0040ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ZIP_ENAX(offset) (0x00011800FE1C0020ull + ((offset) & 1) * 8)\n+#define CVMX_DTX_ZIP_SELX(offset) (0x00011800FE1C0000ull + ((offset) & 1) * 8)\n+\n+/**\n+ * cvmx_dtx_agl_bcst_rsp\n+ */\n+union cvmx_dtx_agl_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_agl_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_agl_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_agl_bcst_rsp_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_agl_bcst_rsp cvmx_dtx_agl_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_agl_ctl\n+ */\n+union cvmx_dtx_agl_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_agl_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_agl_ctl_s cn70xx;\n+\tstruct cvmx_dtx_agl_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_agl_ctl cvmx_dtx_agl_ctl_t;\n+\n+/**\n+ * cvmx_dtx_agl_dat#\n+ */\n+union cvmx_dtx_agl_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_agl_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_agl_datx_s cn70xx;\n+\tstruct cvmx_dtx_agl_datx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_agl_datx cvmx_dtx_agl_datx_t;\n+\n+/**\n+ * cvmx_dtx_agl_ena#\n+ */\n+union cvmx_dtx_agl_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_agl_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_agl_enax_s cn70xx;\n+\tstruct cvmx_dtx_agl_enax_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_agl_enax cvmx_dtx_agl_enax_t;\n+\n+/**\n+ * cvmx_dtx_agl_sel#\n+ */\n+union cvmx_dtx_agl_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_agl_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_agl_selx_s cn70xx;\n+\tstruct cvmx_dtx_agl_selx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_agl_selx cvmx_dtx_agl_selx_t;\n+\n+/**\n+ * cvmx_dtx_ase_bcst_rsp\n+ */\n+union cvmx_dtx_ase_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ase_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ase_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_ase_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ase_bcst_rsp cvmx_dtx_ase_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_ase_ctl\n+ */\n+union cvmx_dtx_ase_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ase_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ase_ctl_s cn78xx;\n+\tstruct cvmx_dtx_ase_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ase_ctl cvmx_dtx_ase_ctl_t;\n+\n+/**\n+ * cvmx_dtx_ase_dat#\n+ */\n+union cvmx_dtx_ase_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ase_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ase_datx_s cn78xx;\n+\tstruct cvmx_dtx_ase_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ase_datx cvmx_dtx_ase_datx_t;\n+\n+/**\n+ * cvmx_dtx_ase_ena#\n+ */\n+union cvmx_dtx_ase_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ase_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ase_enax_s cn78xx;\n+\tstruct cvmx_dtx_ase_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ase_enax cvmx_dtx_ase_enax_t;\n+\n+/**\n+ * cvmx_dtx_ase_sel#\n+ */\n+union cvmx_dtx_ase_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ase_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_ase_selx_s cn78xx;\n+\tstruct cvmx_dtx_ase_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ase_selx cvmx_dtx_ase_selx_t;\n+\n+/**\n+ * cvmx_dtx_bbx1i_bcst_rsp\n+ */\n+union cvmx_dtx_bbx1i_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx1i_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_bbx1i_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx1i_bcst_rsp cvmx_dtx_bbx1i_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_bbx1i_ctl\n+ */\n+union cvmx_dtx_bbx1i_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx1i_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_bbx1i_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx1i_ctl cvmx_dtx_bbx1i_ctl_t;\n+\n+/**\n+ * cvmx_dtx_bbx1i_dat#\n+ */\n+union cvmx_dtx_bbx1i_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx1i_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_bbx1i_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx1i_datx cvmx_dtx_bbx1i_datx_t;\n+\n+/**\n+ * cvmx_dtx_bbx1i_ena#\n+ */\n+union cvmx_dtx_bbx1i_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx1i_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_bbx1i_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx1i_enax cvmx_dtx_bbx1i_enax_t;\n+\n+/**\n+ * cvmx_dtx_bbx1i_sel#\n+ */\n+union cvmx_dtx_bbx1i_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx1i_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_bbx1i_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx1i_selx cvmx_dtx_bbx1i_selx_t;\n+\n+/**\n+ * cvmx_dtx_bbx2i_bcst_rsp\n+ */\n+union cvmx_dtx_bbx2i_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx2i_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_bbx2i_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx2i_bcst_rsp cvmx_dtx_bbx2i_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_bbx2i_ctl\n+ */\n+union cvmx_dtx_bbx2i_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx2i_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_bbx2i_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx2i_ctl cvmx_dtx_bbx2i_ctl_t;\n+\n+/**\n+ * cvmx_dtx_bbx2i_dat#\n+ */\n+union cvmx_dtx_bbx2i_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx2i_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_bbx2i_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx2i_datx cvmx_dtx_bbx2i_datx_t;\n+\n+/**\n+ * cvmx_dtx_bbx2i_ena#\n+ */\n+union cvmx_dtx_bbx2i_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx2i_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_bbx2i_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx2i_enax cvmx_dtx_bbx2i_enax_t;\n+\n+/**\n+ * cvmx_dtx_bbx2i_sel#\n+ */\n+union cvmx_dtx_bbx2i_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx2i_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_bbx2i_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx2i_selx cvmx_dtx_bbx2i_selx_t;\n+\n+/**\n+ * cvmx_dtx_bbx3i_bcst_rsp\n+ */\n+union cvmx_dtx_bbx3i_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx3i_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_bbx3i_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx3i_bcst_rsp cvmx_dtx_bbx3i_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_bbx3i_ctl\n+ */\n+union cvmx_dtx_bbx3i_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx3i_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_bbx3i_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx3i_ctl cvmx_dtx_bbx3i_ctl_t;\n+\n+/**\n+ * cvmx_dtx_bbx3i_dat#\n+ */\n+union cvmx_dtx_bbx3i_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx3i_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_bbx3i_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx3i_datx cvmx_dtx_bbx3i_datx_t;\n+\n+/**\n+ * cvmx_dtx_bbx3i_ena#\n+ */\n+union cvmx_dtx_bbx3i_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx3i_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_bbx3i_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx3i_enax cvmx_dtx_bbx3i_enax_t;\n+\n+/**\n+ * cvmx_dtx_bbx3i_sel#\n+ */\n+union cvmx_dtx_bbx3i_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bbx3i_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_bbx3i_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bbx3i_selx cvmx_dtx_bbx3i_selx_t;\n+\n+/**\n+ * cvmx_dtx_bch_bcst_rsp\n+ */\n+union cvmx_dtx_bch_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bch_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_bch_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_bch_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bch_bcst_rsp cvmx_dtx_bch_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_bch_ctl\n+ */\n+union cvmx_dtx_bch_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bch_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_bch_ctl_s cn73xx;\n+\tstruct cvmx_dtx_bch_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bch_ctl cvmx_dtx_bch_ctl_t;\n+\n+/**\n+ * cvmx_dtx_bch_dat#\n+ */\n+union cvmx_dtx_bch_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bch_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_bch_datx_s cn73xx;\n+\tstruct cvmx_dtx_bch_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bch_datx cvmx_dtx_bch_datx_t;\n+\n+/**\n+ * cvmx_dtx_bch_ena#\n+ */\n+union cvmx_dtx_bch_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bch_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_bch_enax_s cn73xx;\n+\tstruct cvmx_dtx_bch_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bch_enax cvmx_dtx_bch_enax_t;\n+\n+/**\n+ * cvmx_dtx_bch_sel#\n+ */\n+union cvmx_dtx_bch_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bch_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_bch_selx_s cn73xx;\n+\tstruct cvmx_dtx_bch_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bch_selx cvmx_dtx_bch_selx_t;\n+\n+/**\n+ * cvmx_dtx_bgx#_bcst_rsp\n+ */\n+union cvmx_dtx_bgxx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bgxx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_bgxx_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_bgxx_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_bgxx_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_bgxx_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bgxx_bcst_rsp cvmx_dtx_bgxx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_bgx#_ctl\n+ */\n+union cvmx_dtx_bgxx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bgxx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_bgxx_ctl_s cn73xx;\n+\tstruct cvmx_dtx_bgxx_ctl_s cn78xx;\n+\tstruct cvmx_dtx_bgxx_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_bgxx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bgxx_ctl cvmx_dtx_bgxx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_bgx#_dat#\n+ */\n+union cvmx_dtx_bgxx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bgxx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_bgxx_datx_s cn73xx;\n+\tstruct cvmx_dtx_bgxx_datx_s cn78xx;\n+\tstruct cvmx_dtx_bgxx_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_bgxx_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bgxx_datx cvmx_dtx_bgxx_datx_t;\n+\n+/**\n+ * cvmx_dtx_bgx#_ena#\n+ */\n+union cvmx_dtx_bgxx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bgxx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_bgxx_enax_s cn73xx;\n+\tstruct cvmx_dtx_bgxx_enax_s cn78xx;\n+\tstruct cvmx_dtx_bgxx_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_bgxx_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bgxx_enax cvmx_dtx_bgxx_enax_t;\n+\n+/**\n+ * cvmx_dtx_bgx#_sel#\n+ */\n+union cvmx_dtx_bgxx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bgxx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_bgxx_selx_s cn73xx;\n+\tstruct cvmx_dtx_bgxx_selx_s cn78xx;\n+\tstruct cvmx_dtx_bgxx_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_bgxx_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bgxx_selx cvmx_dtx_bgxx_selx_t;\n+\n+/**\n+ * cvmx_dtx_broadcast_ctl\n+ */\n+union cvmx_dtx_broadcast_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_broadcast_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_broadcast_ctl_s cn70xx;\n+\tstruct cvmx_dtx_broadcast_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_broadcast_ctl_s cn73xx;\n+\tstruct cvmx_dtx_broadcast_ctl_s cn78xx;\n+\tstruct cvmx_dtx_broadcast_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_broadcast_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_broadcast_ctl cvmx_dtx_broadcast_ctl_t;\n+\n+/**\n+ * cvmx_dtx_broadcast_ena#\n+ */\n+union cvmx_dtx_broadcast_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_broadcast_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_broadcast_enax_s cn70xx;\n+\tstruct cvmx_dtx_broadcast_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_broadcast_enax_s cn73xx;\n+\tstruct cvmx_dtx_broadcast_enax_s cn78xx;\n+\tstruct cvmx_dtx_broadcast_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_broadcast_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_broadcast_enax cvmx_dtx_broadcast_enax_t;\n+\n+/**\n+ * cvmx_dtx_broadcast_sel#\n+ */\n+union cvmx_dtx_broadcast_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_broadcast_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_broadcast_selx_s cn70xx;\n+\tstruct cvmx_dtx_broadcast_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_broadcast_selx_s cn73xx;\n+\tstruct cvmx_dtx_broadcast_selx_s cn78xx;\n+\tstruct cvmx_dtx_broadcast_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_broadcast_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_broadcast_selx cvmx_dtx_broadcast_selx_t;\n+\n+/**\n+ * cvmx_dtx_bts_bcst_rsp\n+ */\n+union cvmx_dtx_bts_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bts_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_bts_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bts_bcst_rsp cvmx_dtx_bts_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_bts_ctl\n+ */\n+union cvmx_dtx_bts_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bts_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_bts_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bts_ctl cvmx_dtx_bts_ctl_t;\n+\n+/**\n+ * cvmx_dtx_bts_dat#\n+ */\n+union cvmx_dtx_bts_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bts_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_bts_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bts_datx cvmx_dtx_bts_datx_t;\n+\n+/**\n+ * cvmx_dtx_bts_ena#\n+ */\n+union cvmx_dtx_bts_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bts_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_bts_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bts_enax cvmx_dtx_bts_enax_t;\n+\n+/**\n+ * cvmx_dtx_bts_sel#\n+ */\n+union cvmx_dtx_bts_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_bts_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_bts_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_bts_selx cvmx_dtx_bts_selx_t;\n+\n+/**\n+ * cvmx_dtx_ciu_bcst_rsp\n+ */\n+union cvmx_dtx_ciu_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ciu_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ciu_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_ciu_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_ciu_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_ciu_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_ciu_bcst_rsp cvmx_dtx_ciu_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_ciu_ctl\n+ */\n+union cvmx_dtx_ciu_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ciu_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ciu_ctl_s cn73xx;\n+\tstruct cvmx_dtx_ciu_ctl_s cn78xx;\n+\tstruct cvmx_dtx_ciu_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_ciu_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_ciu_ctl cvmx_dtx_ciu_ctl_t;\n+\n+/**\n+ * cvmx_dtx_ciu_dat#\n+ */\n+union cvmx_dtx_ciu_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ciu_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ciu_datx_s cn73xx;\n+\tstruct cvmx_dtx_ciu_datx_s cn78xx;\n+\tstruct cvmx_dtx_ciu_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_ciu_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_ciu_datx cvmx_dtx_ciu_datx_t;\n+\n+/**\n+ * cvmx_dtx_ciu_ena#\n+ */\n+union cvmx_dtx_ciu_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ciu_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ciu_enax_s cn73xx;\n+\tstruct cvmx_dtx_ciu_enax_s cn78xx;\n+\tstruct cvmx_dtx_ciu_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_ciu_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_ciu_enax cvmx_dtx_ciu_enax_t;\n+\n+/**\n+ * cvmx_dtx_ciu_sel#\n+ */\n+union cvmx_dtx_ciu_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ciu_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_ciu_selx_s cn73xx;\n+\tstruct cvmx_dtx_ciu_selx_s cn78xx;\n+\tstruct cvmx_dtx_ciu_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_ciu_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_ciu_selx cvmx_dtx_ciu_selx_t;\n+\n+/**\n+ * cvmx_dtx_denc_bcst_rsp\n+ */\n+union cvmx_dtx_denc_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_denc_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_denc_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_denc_bcst_rsp cvmx_dtx_denc_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_denc_ctl\n+ */\n+union cvmx_dtx_denc_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_denc_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_denc_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_denc_ctl cvmx_dtx_denc_ctl_t;\n+\n+/**\n+ * cvmx_dtx_denc_dat#\n+ */\n+union cvmx_dtx_denc_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_denc_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_denc_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_denc_datx cvmx_dtx_denc_datx_t;\n+\n+/**\n+ * cvmx_dtx_denc_ena#\n+ */\n+union cvmx_dtx_denc_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_denc_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_denc_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_denc_enax cvmx_dtx_denc_enax_t;\n+\n+/**\n+ * cvmx_dtx_denc_sel#\n+ */\n+union cvmx_dtx_denc_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_denc_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_denc_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_denc_selx cvmx_dtx_denc_selx_t;\n+\n+/**\n+ * cvmx_dtx_dfa_bcst_rsp\n+ */\n+union cvmx_dtx_dfa_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dfa_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_dfa_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_dfa_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_dfa_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_dfa_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_dfa_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_dfa_bcst_rsp cvmx_dtx_dfa_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_dfa_ctl\n+ */\n+union cvmx_dtx_dfa_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dfa_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_dfa_ctl_s cn70xx;\n+\tstruct cvmx_dtx_dfa_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_dfa_ctl_s cn73xx;\n+\tstruct cvmx_dtx_dfa_ctl_s cn78xx;\n+\tstruct cvmx_dtx_dfa_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_dfa_ctl cvmx_dtx_dfa_ctl_t;\n+\n+/**\n+ * cvmx_dtx_dfa_dat#\n+ */\n+union cvmx_dtx_dfa_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dfa_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_dfa_datx_s cn70xx;\n+\tstruct cvmx_dtx_dfa_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_dfa_datx_s cn73xx;\n+\tstruct cvmx_dtx_dfa_datx_s cn78xx;\n+\tstruct cvmx_dtx_dfa_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_dfa_datx cvmx_dtx_dfa_datx_t;\n+\n+/**\n+ * cvmx_dtx_dfa_ena#\n+ */\n+union cvmx_dtx_dfa_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dfa_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_dfa_enax_s cn70xx;\n+\tstruct cvmx_dtx_dfa_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_dfa_enax_s cn73xx;\n+\tstruct cvmx_dtx_dfa_enax_s cn78xx;\n+\tstruct cvmx_dtx_dfa_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_dfa_enax cvmx_dtx_dfa_enax_t;\n+\n+/**\n+ * cvmx_dtx_dfa_sel#\n+ */\n+union cvmx_dtx_dfa_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dfa_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_dfa_selx_s cn70xx;\n+\tstruct cvmx_dtx_dfa_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_dfa_selx_s cn73xx;\n+\tstruct cvmx_dtx_dfa_selx_s cn78xx;\n+\tstruct cvmx_dtx_dfa_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_dfa_selx cvmx_dtx_dfa_selx_t;\n+\n+/**\n+ * cvmx_dtx_dlfe_bcst_rsp\n+ */\n+union cvmx_dtx_dlfe_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dlfe_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_dlfe_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_dlfe_bcst_rsp cvmx_dtx_dlfe_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_dlfe_ctl\n+ */\n+union cvmx_dtx_dlfe_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dlfe_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_dlfe_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_dlfe_ctl cvmx_dtx_dlfe_ctl_t;\n+\n+/**\n+ * cvmx_dtx_dlfe_dat#\n+ */\n+union cvmx_dtx_dlfe_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dlfe_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_dlfe_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_dlfe_datx cvmx_dtx_dlfe_datx_t;\n+\n+/**\n+ * cvmx_dtx_dlfe_ena#\n+ */\n+union cvmx_dtx_dlfe_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dlfe_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_dlfe_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_dlfe_enax cvmx_dtx_dlfe_enax_t;\n+\n+/**\n+ * cvmx_dtx_dlfe_sel#\n+ */\n+union cvmx_dtx_dlfe_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dlfe_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_dlfe_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_dlfe_selx cvmx_dtx_dlfe_selx_t;\n+\n+/**\n+ * cvmx_dtx_dpi_bcst_rsp\n+ */\n+union cvmx_dtx_dpi_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dpi_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_dpi_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_dpi_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_dpi_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_dpi_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_dpi_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_dpi_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_dpi_bcst_rsp cvmx_dtx_dpi_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_dpi_ctl\n+ */\n+union cvmx_dtx_dpi_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dpi_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_dpi_ctl_s cn70xx;\n+\tstruct cvmx_dtx_dpi_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_dpi_ctl_s cn73xx;\n+\tstruct cvmx_dtx_dpi_ctl_s cn78xx;\n+\tstruct cvmx_dtx_dpi_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_dpi_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_dpi_ctl cvmx_dtx_dpi_ctl_t;\n+\n+/**\n+ * cvmx_dtx_dpi_dat#\n+ */\n+union cvmx_dtx_dpi_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dpi_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_dpi_datx_s cn70xx;\n+\tstruct cvmx_dtx_dpi_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_dpi_datx_s cn73xx;\n+\tstruct cvmx_dtx_dpi_datx_s cn78xx;\n+\tstruct cvmx_dtx_dpi_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_dpi_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_dpi_datx cvmx_dtx_dpi_datx_t;\n+\n+/**\n+ * cvmx_dtx_dpi_ena#\n+ */\n+union cvmx_dtx_dpi_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dpi_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_dpi_enax_s cn70xx;\n+\tstruct cvmx_dtx_dpi_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_dpi_enax_s cn73xx;\n+\tstruct cvmx_dtx_dpi_enax_s cn78xx;\n+\tstruct cvmx_dtx_dpi_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_dpi_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_dpi_enax cvmx_dtx_dpi_enax_t;\n+\n+/**\n+ * cvmx_dtx_dpi_sel#\n+ */\n+union cvmx_dtx_dpi_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_dpi_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_dpi_selx_s cn70xx;\n+\tstruct cvmx_dtx_dpi_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_dpi_selx_s cn73xx;\n+\tstruct cvmx_dtx_dpi_selx_s cn78xx;\n+\tstruct cvmx_dtx_dpi_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_dpi_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_dpi_selx cvmx_dtx_dpi_selx_t;\n+\n+/**\n+ * cvmx_dtx_fdeq#_bcst_rsp\n+ */\n+union cvmx_dtx_fdeqx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_fdeqx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_fdeqx_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_fdeqx_bcst_rsp cvmx_dtx_fdeqx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_fdeq#_ctl\n+ */\n+union cvmx_dtx_fdeqx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_fdeqx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_fdeqx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_fdeqx_ctl cvmx_dtx_fdeqx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_fdeq#_dat#\n+ */\n+union cvmx_dtx_fdeqx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_fdeqx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_fdeqx_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_fdeqx_datx cvmx_dtx_fdeqx_datx_t;\n+\n+/**\n+ * cvmx_dtx_fdeq#_ena#\n+ */\n+union cvmx_dtx_fdeqx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_fdeqx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_fdeqx_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_fdeqx_enax cvmx_dtx_fdeqx_enax_t;\n+\n+/**\n+ * cvmx_dtx_fdeq#_sel#\n+ */\n+union cvmx_dtx_fdeqx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_fdeqx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_fdeqx_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_fdeqx_selx cvmx_dtx_fdeqx_selx_t;\n+\n+/**\n+ * cvmx_dtx_fpa_bcst_rsp\n+ */\n+union cvmx_dtx_fpa_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_fpa_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_fpa_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_fpa_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_fpa_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_fpa_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_fpa_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_fpa_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_fpa_bcst_rsp cvmx_dtx_fpa_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_fpa_ctl\n+ */\n+union cvmx_dtx_fpa_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_fpa_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_fpa_ctl_s cn70xx;\n+\tstruct cvmx_dtx_fpa_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_fpa_ctl_s cn73xx;\n+\tstruct cvmx_dtx_fpa_ctl_s cn78xx;\n+\tstruct cvmx_dtx_fpa_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_fpa_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_fpa_ctl cvmx_dtx_fpa_ctl_t;\n+\n+/**\n+ * cvmx_dtx_fpa_dat#\n+ */\n+union cvmx_dtx_fpa_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_fpa_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_fpa_datx_s cn70xx;\n+\tstruct cvmx_dtx_fpa_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_fpa_datx_s cn73xx;\n+\tstruct cvmx_dtx_fpa_datx_s cn78xx;\n+\tstruct cvmx_dtx_fpa_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_fpa_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_fpa_datx cvmx_dtx_fpa_datx_t;\n+\n+/**\n+ * cvmx_dtx_fpa_ena#\n+ */\n+union cvmx_dtx_fpa_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_fpa_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_fpa_enax_s cn70xx;\n+\tstruct cvmx_dtx_fpa_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_fpa_enax_s cn73xx;\n+\tstruct cvmx_dtx_fpa_enax_s cn78xx;\n+\tstruct cvmx_dtx_fpa_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_fpa_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_fpa_enax cvmx_dtx_fpa_enax_t;\n+\n+/**\n+ * cvmx_dtx_fpa_sel#\n+ */\n+union cvmx_dtx_fpa_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_fpa_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_fpa_selx_s cn70xx;\n+\tstruct cvmx_dtx_fpa_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_fpa_selx_s cn73xx;\n+\tstruct cvmx_dtx_fpa_selx_s cn78xx;\n+\tstruct cvmx_dtx_fpa_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_fpa_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_fpa_selx cvmx_dtx_fpa_selx_t;\n+\n+/**\n+ * cvmx_dtx_gmx#_bcst_rsp\n+ */\n+union cvmx_dtx_gmxx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_gmxx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_gmxx_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_gmxx_bcst_rsp_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_gmxx_bcst_rsp cvmx_dtx_gmxx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_gmx#_ctl\n+ */\n+union cvmx_dtx_gmxx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_gmxx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_gmxx_ctl_s cn70xx;\n+\tstruct cvmx_dtx_gmxx_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_gmxx_ctl cvmx_dtx_gmxx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_gmx#_dat#\n+ */\n+union cvmx_dtx_gmxx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_gmxx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_gmxx_datx_s cn70xx;\n+\tstruct cvmx_dtx_gmxx_datx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_gmxx_datx cvmx_dtx_gmxx_datx_t;\n+\n+/**\n+ * cvmx_dtx_gmx#_ena#\n+ */\n+union cvmx_dtx_gmxx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_gmxx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_gmxx_enax_s cn70xx;\n+\tstruct cvmx_dtx_gmxx_enax_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_gmxx_enax cvmx_dtx_gmxx_enax_t;\n+\n+/**\n+ * cvmx_dtx_gmx#_sel#\n+ */\n+union cvmx_dtx_gmxx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_gmxx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_gmxx_selx_s cn70xx;\n+\tstruct cvmx_dtx_gmxx_selx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_gmxx_selx cvmx_dtx_gmxx_selx_t;\n+\n+/**\n+ * cvmx_dtx_gser#_bcst_rsp\n+ */\n+union cvmx_dtx_gserx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_gserx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_gserx_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_gserx_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_gserx_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_gserx_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_gserx_bcst_rsp cvmx_dtx_gserx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_gser#_ctl\n+ */\n+union cvmx_dtx_gserx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_gserx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_gserx_ctl_s cn73xx;\n+\tstruct cvmx_dtx_gserx_ctl_s cn78xx;\n+\tstruct cvmx_dtx_gserx_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_gserx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_gserx_ctl cvmx_dtx_gserx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_gser#_dat#\n+ */\n+union cvmx_dtx_gserx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_gserx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_gserx_datx_s cn73xx;\n+\tstruct cvmx_dtx_gserx_datx_s cn78xx;\n+\tstruct cvmx_dtx_gserx_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_gserx_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_gserx_datx cvmx_dtx_gserx_datx_t;\n+\n+/**\n+ * cvmx_dtx_gser#_ena#\n+ */\n+union cvmx_dtx_gserx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_gserx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_gserx_enax_s cn73xx;\n+\tstruct cvmx_dtx_gserx_enax_s cn78xx;\n+\tstruct cvmx_dtx_gserx_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_gserx_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_gserx_enax cvmx_dtx_gserx_enax_t;\n+\n+/**\n+ * cvmx_dtx_gser#_sel#\n+ */\n+union cvmx_dtx_gserx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_gserx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_gserx_selx_s cn73xx;\n+\tstruct cvmx_dtx_gserx_selx_s cn78xx;\n+\tstruct cvmx_dtx_gserx_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_gserx_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_gserx_selx cvmx_dtx_gserx_selx_t;\n+\n+/**\n+ * cvmx_dtx_hna_bcst_rsp\n+ */\n+union cvmx_dtx_hna_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_hna_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_hna_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_hna_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_hna_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_hna_bcst_rsp cvmx_dtx_hna_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_hna_ctl\n+ */\n+union cvmx_dtx_hna_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_hna_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_hna_ctl_s cn73xx;\n+\tstruct cvmx_dtx_hna_ctl_s cn78xx;\n+\tstruct cvmx_dtx_hna_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_hna_ctl cvmx_dtx_hna_ctl_t;\n+\n+/**\n+ * cvmx_dtx_hna_dat#\n+ */\n+union cvmx_dtx_hna_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_hna_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_hna_datx_s cn73xx;\n+\tstruct cvmx_dtx_hna_datx_s cn78xx;\n+\tstruct cvmx_dtx_hna_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_hna_datx cvmx_dtx_hna_datx_t;\n+\n+/**\n+ * cvmx_dtx_hna_ena#\n+ */\n+union cvmx_dtx_hna_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_hna_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_hna_enax_s cn73xx;\n+\tstruct cvmx_dtx_hna_enax_s cn78xx;\n+\tstruct cvmx_dtx_hna_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_hna_enax cvmx_dtx_hna_enax_t;\n+\n+/**\n+ * cvmx_dtx_hna_sel#\n+ */\n+union cvmx_dtx_hna_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_hna_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_hna_selx_s cn73xx;\n+\tstruct cvmx_dtx_hna_selx_s cn78xx;\n+\tstruct cvmx_dtx_hna_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_hna_selx cvmx_dtx_hna_selx_t;\n+\n+/**\n+ * cvmx_dtx_ila_bcst_rsp\n+ */\n+union cvmx_dtx_ila_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ila_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ila_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_ila_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ila_bcst_rsp cvmx_dtx_ila_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_ila_ctl\n+ */\n+union cvmx_dtx_ila_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ila_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ila_ctl_s cn78xx;\n+\tstruct cvmx_dtx_ila_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ila_ctl cvmx_dtx_ila_ctl_t;\n+\n+/**\n+ * cvmx_dtx_ila_dat#\n+ */\n+union cvmx_dtx_ila_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ila_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ila_datx_s cn78xx;\n+\tstruct cvmx_dtx_ila_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ila_datx cvmx_dtx_ila_datx_t;\n+\n+/**\n+ * cvmx_dtx_ila_ena#\n+ */\n+union cvmx_dtx_ila_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ila_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ila_enax_s cn78xx;\n+\tstruct cvmx_dtx_ila_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ila_enax cvmx_dtx_ila_enax_t;\n+\n+/**\n+ * cvmx_dtx_ila_sel#\n+ */\n+union cvmx_dtx_ila_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ila_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_ila_selx_s cn78xx;\n+\tstruct cvmx_dtx_ila_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ila_selx cvmx_dtx_ila_selx_t;\n+\n+/**\n+ * cvmx_dtx_ilk_bcst_rsp\n+ */\n+union cvmx_dtx_ilk_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ilk_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ilk_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_ilk_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ilk_bcst_rsp cvmx_dtx_ilk_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_ilk_ctl\n+ */\n+union cvmx_dtx_ilk_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ilk_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ilk_ctl_s cn78xx;\n+\tstruct cvmx_dtx_ilk_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ilk_ctl cvmx_dtx_ilk_ctl_t;\n+\n+/**\n+ * cvmx_dtx_ilk_dat#\n+ */\n+union cvmx_dtx_ilk_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ilk_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ilk_datx_s cn78xx;\n+\tstruct cvmx_dtx_ilk_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ilk_datx cvmx_dtx_ilk_datx_t;\n+\n+/**\n+ * cvmx_dtx_ilk_ena#\n+ */\n+union cvmx_dtx_ilk_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ilk_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ilk_enax_s cn78xx;\n+\tstruct cvmx_dtx_ilk_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ilk_enax cvmx_dtx_ilk_enax_t;\n+\n+/**\n+ * cvmx_dtx_ilk_sel#\n+ */\n+union cvmx_dtx_ilk_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ilk_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_ilk_selx_s cn78xx;\n+\tstruct cvmx_dtx_ilk_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ilk_selx cvmx_dtx_ilk_selx_t;\n+\n+/**\n+ * cvmx_dtx_iob_bcst_rsp\n+ */\n+union cvmx_dtx_iob_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iob_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_iob_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_iob_bcst_rsp_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_iob_bcst_rsp cvmx_dtx_iob_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_iob_ctl\n+ */\n+union cvmx_dtx_iob_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iob_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_iob_ctl_s cn70xx;\n+\tstruct cvmx_dtx_iob_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_iob_ctl cvmx_dtx_iob_ctl_t;\n+\n+/**\n+ * cvmx_dtx_iob_dat#\n+ */\n+union cvmx_dtx_iob_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iob_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_iob_datx_s cn70xx;\n+\tstruct cvmx_dtx_iob_datx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_iob_datx cvmx_dtx_iob_datx_t;\n+\n+/**\n+ * cvmx_dtx_iob_ena#\n+ */\n+union cvmx_dtx_iob_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iob_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_iob_enax_s cn70xx;\n+\tstruct cvmx_dtx_iob_enax_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_iob_enax cvmx_dtx_iob_enax_t;\n+\n+/**\n+ * cvmx_dtx_iob_sel#\n+ */\n+union cvmx_dtx_iob_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iob_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_iob_selx_s cn70xx;\n+\tstruct cvmx_dtx_iob_selx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_iob_selx cvmx_dtx_iob_selx_t;\n+\n+/**\n+ * cvmx_dtx_iobn_bcst_rsp\n+ */\n+union cvmx_dtx_iobn_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iobn_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_iobn_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_iobn_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_iobn_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_iobn_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_iobn_bcst_rsp cvmx_dtx_iobn_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_iobn_ctl\n+ */\n+union cvmx_dtx_iobn_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iobn_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_iobn_ctl_s cn73xx;\n+\tstruct cvmx_dtx_iobn_ctl_s cn78xx;\n+\tstruct cvmx_dtx_iobn_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_iobn_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_iobn_ctl cvmx_dtx_iobn_ctl_t;\n+\n+/**\n+ * cvmx_dtx_iobn_dat#\n+ */\n+union cvmx_dtx_iobn_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iobn_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_iobn_datx_s cn73xx;\n+\tstruct cvmx_dtx_iobn_datx_s cn78xx;\n+\tstruct cvmx_dtx_iobn_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_iobn_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_iobn_datx cvmx_dtx_iobn_datx_t;\n+\n+/**\n+ * cvmx_dtx_iobn_ena#\n+ */\n+union cvmx_dtx_iobn_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iobn_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_iobn_enax_s cn73xx;\n+\tstruct cvmx_dtx_iobn_enax_s cn78xx;\n+\tstruct cvmx_dtx_iobn_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_iobn_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_iobn_enax cvmx_dtx_iobn_enax_t;\n+\n+/**\n+ * cvmx_dtx_iobn_sel#\n+ */\n+union cvmx_dtx_iobn_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iobn_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_iobn_selx_s cn73xx;\n+\tstruct cvmx_dtx_iobn_selx_s cn78xx;\n+\tstruct cvmx_dtx_iobn_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_iobn_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_iobn_selx cvmx_dtx_iobn_selx_t;\n+\n+/**\n+ * cvmx_dtx_iobp_bcst_rsp\n+ */\n+union cvmx_dtx_iobp_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iobp_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_iobp_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_iobp_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_iobp_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_iobp_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_iobp_bcst_rsp cvmx_dtx_iobp_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_iobp_ctl\n+ */\n+union cvmx_dtx_iobp_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iobp_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_iobp_ctl_s cn73xx;\n+\tstruct cvmx_dtx_iobp_ctl_s cn78xx;\n+\tstruct cvmx_dtx_iobp_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_iobp_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_iobp_ctl cvmx_dtx_iobp_ctl_t;\n+\n+/**\n+ * cvmx_dtx_iobp_dat#\n+ */\n+union cvmx_dtx_iobp_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iobp_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_iobp_datx_s cn73xx;\n+\tstruct cvmx_dtx_iobp_datx_s cn78xx;\n+\tstruct cvmx_dtx_iobp_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_iobp_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_iobp_datx cvmx_dtx_iobp_datx_t;\n+\n+/**\n+ * cvmx_dtx_iobp_ena#\n+ */\n+union cvmx_dtx_iobp_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iobp_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_iobp_enax_s cn73xx;\n+\tstruct cvmx_dtx_iobp_enax_s cn78xx;\n+\tstruct cvmx_dtx_iobp_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_iobp_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_iobp_enax cvmx_dtx_iobp_enax_t;\n+\n+/**\n+ * cvmx_dtx_iobp_sel#\n+ */\n+union cvmx_dtx_iobp_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_iobp_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_iobp_selx_s cn73xx;\n+\tstruct cvmx_dtx_iobp_selx_s cn78xx;\n+\tstruct cvmx_dtx_iobp_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_iobp_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_iobp_selx cvmx_dtx_iobp_selx_t;\n+\n+/**\n+ * cvmx_dtx_ipd_bcst_rsp\n+ */\n+union cvmx_dtx_ipd_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ipd_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ipd_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_ipd_bcst_rsp_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_ipd_bcst_rsp cvmx_dtx_ipd_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_ipd_ctl\n+ */\n+union cvmx_dtx_ipd_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ipd_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ipd_ctl_s cn70xx;\n+\tstruct cvmx_dtx_ipd_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_ipd_ctl cvmx_dtx_ipd_ctl_t;\n+\n+/**\n+ * cvmx_dtx_ipd_dat#\n+ */\n+union cvmx_dtx_ipd_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ipd_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ipd_datx_s cn70xx;\n+\tstruct cvmx_dtx_ipd_datx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_ipd_datx cvmx_dtx_ipd_datx_t;\n+\n+/**\n+ * cvmx_dtx_ipd_ena#\n+ */\n+union cvmx_dtx_ipd_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ipd_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ipd_enax_s cn70xx;\n+\tstruct cvmx_dtx_ipd_enax_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_ipd_enax cvmx_dtx_ipd_enax_t;\n+\n+/**\n+ * cvmx_dtx_ipd_sel#\n+ */\n+union cvmx_dtx_ipd_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ipd_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_ipd_selx_s cn70xx;\n+\tstruct cvmx_dtx_ipd_selx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_ipd_selx cvmx_dtx_ipd_selx_t;\n+\n+/**\n+ * cvmx_dtx_key_bcst_rsp\n+ */\n+union cvmx_dtx_key_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_key_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_key_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_key_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_key_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_key_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_key_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_key_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_key_bcst_rsp cvmx_dtx_key_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_key_ctl\n+ */\n+union cvmx_dtx_key_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_key_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_key_ctl_s cn70xx;\n+\tstruct cvmx_dtx_key_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_key_ctl_s cn73xx;\n+\tstruct cvmx_dtx_key_ctl_s cn78xx;\n+\tstruct cvmx_dtx_key_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_key_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_key_ctl cvmx_dtx_key_ctl_t;\n+\n+/**\n+ * cvmx_dtx_key_dat#\n+ */\n+union cvmx_dtx_key_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_key_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_key_datx_s cn70xx;\n+\tstruct cvmx_dtx_key_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_key_datx_s cn73xx;\n+\tstruct cvmx_dtx_key_datx_s cn78xx;\n+\tstruct cvmx_dtx_key_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_key_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_key_datx cvmx_dtx_key_datx_t;\n+\n+/**\n+ * cvmx_dtx_key_ena#\n+ */\n+union cvmx_dtx_key_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_key_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_key_enax_s cn70xx;\n+\tstruct cvmx_dtx_key_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_key_enax_s cn73xx;\n+\tstruct cvmx_dtx_key_enax_s cn78xx;\n+\tstruct cvmx_dtx_key_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_key_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_key_enax cvmx_dtx_key_enax_t;\n+\n+/**\n+ * cvmx_dtx_key_sel#\n+ */\n+union cvmx_dtx_key_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_key_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_key_selx_s cn70xx;\n+\tstruct cvmx_dtx_key_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_key_selx_s cn73xx;\n+\tstruct cvmx_dtx_key_selx_s cn78xx;\n+\tstruct cvmx_dtx_key_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_key_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_key_selx cvmx_dtx_key_selx_t;\n+\n+/**\n+ * cvmx_dtx_l2c_cbc#_bcst_rsp\n+ */\n+union cvmx_dtx_l2c_cbcx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_cbcx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_cbcx_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_l2c_cbcx_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_cbcx_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_l2c_cbcx_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_l2c_cbcx_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_cbcx_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_cbcx_bcst_rsp cvmx_dtx_l2c_cbcx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_l2c_cbc#_ctl\n+ */\n+union cvmx_dtx_l2c_cbcx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_cbcx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_cbcx_ctl_s cn70xx;\n+\tstruct cvmx_dtx_l2c_cbcx_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_cbcx_ctl_s cn73xx;\n+\tstruct cvmx_dtx_l2c_cbcx_ctl_s cn78xx;\n+\tstruct cvmx_dtx_l2c_cbcx_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_cbcx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_cbcx_ctl cvmx_dtx_l2c_cbcx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_l2c_cbc#_dat#\n+ */\n+union cvmx_dtx_l2c_cbcx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_cbcx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_cbcx_datx_s cn70xx;\n+\tstruct cvmx_dtx_l2c_cbcx_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_cbcx_datx_s cn73xx;\n+\tstruct cvmx_dtx_l2c_cbcx_datx_s cn78xx;\n+\tstruct cvmx_dtx_l2c_cbcx_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_cbcx_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_cbcx_datx cvmx_dtx_l2c_cbcx_datx_t;\n+\n+/**\n+ * cvmx_dtx_l2c_cbc#_ena#\n+ */\n+union cvmx_dtx_l2c_cbcx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_cbcx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_cbcx_enax_s cn70xx;\n+\tstruct cvmx_dtx_l2c_cbcx_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_cbcx_enax_s cn73xx;\n+\tstruct cvmx_dtx_l2c_cbcx_enax_s cn78xx;\n+\tstruct cvmx_dtx_l2c_cbcx_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_cbcx_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_cbcx_enax cvmx_dtx_l2c_cbcx_enax_t;\n+\n+/**\n+ * cvmx_dtx_l2c_cbc#_sel#\n+ */\n+union cvmx_dtx_l2c_cbcx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_cbcx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_cbcx_selx_s cn70xx;\n+\tstruct cvmx_dtx_l2c_cbcx_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_cbcx_selx_s cn73xx;\n+\tstruct cvmx_dtx_l2c_cbcx_selx_s cn78xx;\n+\tstruct cvmx_dtx_l2c_cbcx_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_cbcx_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_cbcx_selx cvmx_dtx_l2c_cbcx_selx_t;\n+\n+/**\n+ * cvmx_dtx_l2c_mci#_bcst_rsp\n+ */\n+union cvmx_dtx_l2c_mcix_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_mcix_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_mcix_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_l2c_mcix_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_mcix_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_l2c_mcix_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_l2c_mcix_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_mcix_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_mcix_bcst_rsp cvmx_dtx_l2c_mcix_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_l2c_mci#_ctl\n+ */\n+union cvmx_dtx_l2c_mcix_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_mcix_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_mcix_ctl_s cn70xx;\n+\tstruct cvmx_dtx_l2c_mcix_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_mcix_ctl_s cn73xx;\n+\tstruct cvmx_dtx_l2c_mcix_ctl_s cn78xx;\n+\tstruct cvmx_dtx_l2c_mcix_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_mcix_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_mcix_ctl cvmx_dtx_l2c_mcix_ctl_t;\n+\n+/**\n+ * cvmx_dtx_l2c_mci#_dat#\n+ */\n+union cvmx_dtx_l2c_mcix_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_mcix_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_mcix_datx_s cn70xx;\n+\tstruct cvmx_dtx_l2c_mcix_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_mcix_datx_s cn73xx;\n+\tstruct cvmx_dtx_l2c_mcix_datx_s cn78xx;\n+\tstruct cvmx_dtx_l2c_mcix_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_mcix_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_mcix_datx cvmx_dtx_l2c_mcix_datx_t;\n+\n+/**\n+ * cvmx_dtx_l2c_mci#_ena#\n+ */\n+union cvmx_dtx_l2c_mcix_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_mcix_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_mcix_enax_s cn70xx;\n+\tstruct cvmx_dtx_l2c_mcix_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_mcix_enax_s cn73xx;\n+\tstruct cvmx_dtx_l2c_mcix_enax_s cn78xx;\n+\tstruct cvmx_dtx_l2c_mcix_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_mcix_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_mcix_enax cvmx_dtx_l2c_mcix_enax_t;\n+\n+/**\n+ * cvmx_dtx_l2c_mci#_sel#\n+ */\n+union cvmx_dtx_l2c_mcix_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_mcix_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_mcix_selx_s cn70xx;\n+\tstruct cvmx_dtx_l2c_mcix_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_mcix_selx_s cn73xx;\n+\tstruct cvmx_dtx_l2c_mcix_selx_s cn78xx;\n+\tstruct cvmx_dtx_l2c_mcix_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_mcix_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_mcix_selx cvmx_dtx_l2c_mcix_selx_t;\n+\n+/**\n+ * cvmx_dtx_l2c_tad#_bcst_rsp\n+ */\n+union cvmx_dtx_l2c_tadx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_tadx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_tadx_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_l2c_tadx_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_tadx_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_l2c_tadx_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_l2c_tadx_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_tadx_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_tadx_bcst_rsp cvmx_dtx_l2c_tadx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_l2c_tad#_ctl\n+ */\n+union cvmx_dtx_l2c_tadx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_tadx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_tadx_ctl_s cn70xx;\n+\tstruct cvmx_dtx_l2c_tadx_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_tadx_ctl_s cn73xx;\n+\tstruct cvmx_dtx_l2c_tadx_ctl_s cn78xx;\n+\tstruct cvmx_dtx_l2c_tadx_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_tadx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_tadx_ctl cvmx_dtx_l2c_tadx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_l2c_tad#_dat#\n+ */\n+union cvmx_dtx_l2c_tadx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_tadx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_tadx_datx_s cn70xx;\n+\tstruct cvmx_dtx_l2c_tadx_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_tadx_datx_s cn73xx;\n+\tstruct cvmx_dtx_l2c_tadx_datx_s cn78xx;\n+\tstruct cvmx_dtx_l2c_tadx_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_tadx_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_tadx_datx cvmx_dtx_l2c_tadx_datx_t;\n+\n+/**\n+ * cvmx_dtx_l2c_tad#_ena#\n+ */\n+union cvmx_dtx_l2c_tadx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_tadx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_tadx_enax_s cn70xx;\n+\tstruct cvmx_dtx_l2c_tadx_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_tadx_enax_s cn73xx;\n+\tstruct cvmx_dtx_l2c_tadx_enax_s cn78xx;\n+\tstruct cvmx_dtx_l2c_tadx_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_tadx_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_tadx_enax cvmx_dtx_l2c_tadx_enax_t;\n+\n+/**\n+ * cvmx_dtx_l2c_tad#_sel#\n+ */\n+union cvmx_dtx_l2c_tadx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_l2c_tadx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_l2c_tadx_selx_s cn70xx;\n+\tstruct cvmx_dtx_l2c_tadx_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_l2c_tadx_selx_s cn73xx;\n+\tstruct cvmx_dtx_l2c_tadx_selx_s cn78xx;\n+\tstruct cvmx_dtx_l2c_tadx_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_l2c_tadx_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_l2c_tadx_selx cvmx_dtx_l2c_tadx_selx_t;\n+\n+/**\n+ * cvmx_dtx_lap#_bcst_rsp\n+ */\n+union cvmx_dtx_lapx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lapx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_lapx_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_lapx_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_lapx_bcst_rsp cvmx_dtx_lapx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_lap#_ctl\n+ */\n+union cvmx_dtx_lapx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lapx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_lapx_ctl_s cn78xx;\n+\tstruct cvmx_dtx_lapx_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_lapx_ctl cvmx_dtx_lapx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_lap#_dat#\n+ */\n+union cvmx_dtx_lapx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lapx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_lapx_datx_s cn78xx;\n+\tstruct cvmx_dtx_lapx_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_lapx_datx cvmx_dtx_lapx_datx_t;\n+\n+/**\n+ * cvmx_dtx_lap#_ena#\n+ */\n+union cvmx_dtx_lapx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lapx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_lapx_enax_s cn78xx;\n+\tstruct cvmx_dtx_lapx_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_lapx_enax cvmx_dtx_lapx_enax_t;\n+\n+/**\n+ * cvmx_dtx_lap#_sel#\n+ */\n+union cvmx_dtx_lapx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lapx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_lapx_selx_s cn78xx;\n+\tstruct cvmx_dtx_lapx_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_lapx_selx cvmx_dtx_lapx_selx_t;\n+\n+/**\n+ * cvmx_dtx_lbk_bcst_rsp\n+ */\n+union cvmx_dtx_lbk_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lbk_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_lbk_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_lbk_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_lbk_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_lbk_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_lbk_bcst_rsp cvmx_dtx_lbk_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_lbk_ctl\n+ */\n+union cvmx_dtx_lbk_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lbk_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_lbk_ctl_s cn73xx;\n+\tstruct cvmx_dtx_lbk_ctl_s cn78xx;\n+\tstruct cvmx_dtx_lbk_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_lbk_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_lbk_ctl cvmx_dtx_lbk_ctl_t;\n+\n+/**\n+ * cvmx_dtx_lbk_dat#\n+ */\n+union cvmx_dtx_lbk_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lbk_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_lbk_datx_s cn73xx;\n+\tstruct cvmx_dtx_lbk_datx_s cn78xx;\n+\tstruct cvmx_dtx_lbk_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_lbk_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_lbk_datx cvmx_dtx_lbk_datx_t;\n+\n+/**\n+ * cvmx_dtx_lbk_ena#\n+ */\n+union cvmx_dtx_lbk_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lbk_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_lbk_enax_s cn73xx;\n+\tstruct cvmx_dtx_lbk_enax_s cn78xx;\n+\tstruct cvmx_dtx_lbk_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_lbk_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_lbk_enax cvmx_dtx_lbk_enax_t;\n+\n+/**\n+ * cvmx_dtx_lbk_sel#\n+ */\n+union cvmx_dtx_lbk_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lbk_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_lbk_selx_s cn73xx;\n+\tstruct cvmx_dtx_lbk_selx_s cn78xx;\n+\tstruct cvmx_dtx_lbk_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_lbk_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_lbk_selx cvmx_dtx_lbk_selx_t;\n+\n+/**\n+ * cvmx_dtx_lmc#_bcst_rsp\n+ */\n+union cvmx_dtx_lmcx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lmcx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_lmcx_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_lmcx_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_lmcx_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_lmcx_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_lmcx_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_lmcx_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_lmcx_bcst_rsp cvmx_dtx_lmcx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_lmc#_ctl\n+ */\n+union cvmx_dtx_lmcx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lmcx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_lmcx_ctl_s cn70xx;\n+\tstruct cvmx_dtx_lmcx_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_lmcx_ctl_s cn73xx;\n+\tstruct cvmx_dtx_lmcx_ctl_s cn78xx;\n+\tstruct cvmx_dtx_lmcx_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_lmcx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_lmcx_ctl cvmx_dtx_lmcx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_lmc#_dat#\n+ */\n+union cvmx_dtx_lmcx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lmcx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_lmcx_datx_s cn70xx;\n+\tstruct cvmx_dtx_lmcx_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_lmcx_datx_s cn73xx;\n+\tstruct cvmx_dtx_lmcx_datx_s cn78xx;\n+\tstruct cvmx_dtx_lmcx_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_lmcx_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_lmcx_datx cvmx_dtx_lmcx_datx_t;\n+\n+/**\n+ * cvmx_dtx_lmc#_ena#\n+ */\n+union cvmx_dtx_lmcx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lmcx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_lmcx_enax_s cn70xx;\n+\tstruct cvmx_dtx_lmcx_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_lmcx_enax_s cn73xx;\n+\tstruct cvmx_dtx_lmcx_enax_s cn78xx;\n+\tstruct cvmx_dtx_lmcx_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_lmcx_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_lmcx_enax cvmx_dtx_lmcx_enax_t;\n+\n+/**\n+ * cvmx_dtx_lmc#_sel#\n+ */\n+union cvmx_dtx_lmcx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_lmcx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_lmcx_selx_s cn70xx;\n+\tstruct cvmx_dtx_lmcx_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_lmcx_selx_s cn73xx;\n+\tstruct cvmx_dtx_lmcx_selx_s cn78xx;\n+\tstruct cvmx_dtx_lmcx_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_lmcx_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_lmcx_selx cvmx_dtx_lmcx_selx_t;\n+\n+/**\n+ * cvmx_dtx_mdb#_bcst_rsp\n+ */\n+union cvmx_dtx_mdbx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mdbx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_mdbx_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mdbx_bcst_rsp cvmx_dtx_mdbx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_mdb#_ctl\n+ */\n+union cvmx_dtx_mdbx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mdbx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_mdbx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mdbx_ctl cvmx_dtx_mdbx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_mdb#_dat#\n+ */\n+union cvmx_dtx_mdbx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mdbx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_mdbx_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mdbx_datx cvmx_dtx_mdbx_datx_t;\n+\n+/**\n+ * cvmx_dtx_mdb#_ena#\n+ */\n+union cvmx_dtx_mdbx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mdbx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_mdbx_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mdbx_enax cvmx_dtx_mdbx_enax_t;\n+\n+/**\n+ * cvmx_dtx_mdb#_sel#\n+ */\n+union cvmx_dtx_mdbx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mdbx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_mdbx_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mdbx_selx cvmx_dtx_mdbx_selx_t;\n+\n+/**\n+ * cvmx_dtx_mhbw_bcst_rsp\n+ */\n+union cvmx_dtx_mhbw_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mhbw_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_mhbw_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mhbw_bcst_rsp cvmx_dtx_mhbw_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_mhbw_ctl\n+ */\n+union cvmx_dtx_mhbw_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mhbw_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_mhbw_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mhbw_ctl cvmx_dtx_mhbw_ctl_t;\n+\n+/**\n+ * cvmx_dtx_mhbw_dat#\n+ */\n+union cvmx_dtx_mhbw_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mhbw_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_mhbw_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mhbw_datx cvmx_dtx_mhbw_datx_t;\n+\n+/**\n+ * cvmx_dtx_mhbw_ena#\n+ */\n+union cvmx_dtx_mhbw_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mhbw_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_mhbw_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mhbw_enax cvmx_dtx_mhbw_enax_t;\n+\n+/**\n+ * cvmx_dtx_mhbw_sel#\n+ */\n+union cvmx_dtx_mhbw_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mhbw_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_mhbw_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mhbw_selx cvmx_dtx_mhbw_selx_t;\n+\n+/**\n+ * cvmx_dtx_mio_bcst_rsp\n+ */\n+union cvmx_dtx_mio_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mio_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_mio_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_mio_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_mio_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_mio_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_mio_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_mio_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mio_bcst_rsp cvmx_dtx_mio_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_mio_ctl\n+ */\n+union cvmx_dtx_mio_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mio_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_mio_ctl_s cn70xx;\n+\tstruct cvmx_dtx_mio_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_mio_ctl_s cn73xx;\n+\tstruct cvmx_dtx_mio_ctl_s cn78xx;\n+\tstruct cvmx_dtx_mio_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_mio_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mio_ctl cvmx_dtx_mio_ctl_t;\n+\n+/**\n+ * cvmx_dtx_mio_dat#\n+ */\n+union cvmx_dtx_mio_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mio_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_mio_datx_s cn70xx;\n+\tstruct cvmx_dtx_mio_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_mio_datx_s cn73xx;\n+\tstruct cvmx_dtx_mio_datx_s cn78xx;\n+\tstruct cvmx_dtx_mio_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_mio_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mio_datx cvmx_dtx_mio_datx_t;\n+\n+/**\n+ * cvmx_dtx_mio_ena#\n+ */\n+union cvmx_dtx_mio_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mio_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_mio_enax_s cn70xx;\n+\tstruct cvmx_dtx_mio_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_mio_enax_s cn73xx;\n+\tstruct cvmx_dtx_mio_enax_s cn78xx;\n+\tstruct cvmx_dtx_mio_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_mio_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mio_enax cvmx_dtx_mio_enax_t;\n+\n+/**\n+ * cvmx_dtx_mio_sel#\n+ */\n+union cvmx_dtx_mio_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_mio_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_mio_selx_s cn70xx;\n+\tstruct cvmx_dtx_mio_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_mio_selx_s cn73xx;\n+\tstruct cvmx_dtx_mio_selx_s cn78xx;\n+\tstruct cvmx_dtx_mio_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_mio_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_mio_selx cvmx_dtx_mio_selx_t;\n+\n+/**\n+ * cvmx_dtx_ocx_bot_bcst_rsp\n+ */\n+union cvmx_dtx_ocx_bot_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_bot_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_bot_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_ocx_bot_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_bot_bcst_rsp cvmx_dtx_ocx_bot_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_ocx_bot_ctl\n+ */\n+union cvmx_dtx_ocx_bot_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_bot_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_bot_ctl_s cn78xx;\n+\tstruct cvmx_dtx_ocx_bot_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_bot_ctl cvmx_dtx_ocx_bot_ctl_t;\n+\n+/**\n+ * cvmx_dtx_ocx_bot_dat#\n+ */\n+union cvmx_dtx_ocx_bot_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_bot_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_bot_datx_s cn78xx;\n+\tstruct cvmx_dtx_ocx_bot_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_bot_datx cvmx_dtx_ocx_bot_datx_t;\n+\n+/**\n+ * cvmx_dtx_ocx_bot_ena#\n+ */\n+union cvmx_dtx_ocx_bot_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_bot_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_bot_enax_s cn78xx;\n+\tstruct cvmx_dtx_ocx_bot_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_bot_enax cvmx_dtx_ocx_bot_enax_t;\n+\n+/**\n+ * cvmx_dtx_ocx_bot_sel#\n+ */\n+union cvmx_dtx_ocx_bot_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_bot_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_bot_selx_s cn78xx;\n+\tstruct cvmx_dtx_ocx_bot_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_bot_selx cvmx_dtx_ocx_bot_selx_t;\n+\n+/**\n+ * cvmx_dtx_ocx_lnk#_bcst_rsp\n+ */\n+union cvmx_dtx_ocx_lnkx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_lnkx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_lnkx_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_ocx_lnkx_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_lnkx_bcst_rsp cvmx_dtx_ocx_lnkx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_ocx_lnk#_ctl\n+ */\n+union cvmx_dtx_ocx_lnkx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_lnkx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_lnkx_ctl_s cn78xx;\n+\tstruct cvmx_dtx_ocx_lnkx_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_lnkx_ctl cvmx_dtx_ocx_lnkx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_ocx_lnk#_dat#\n+ */\n+union cvmx_dtx_ocx_lnkx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_lnkx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_lnkx_datx_s cn78xx;\n+\tstruct cvmx_dtx_ocx_lnkx_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_lnkx_datx cvmx_dtx_ocx_lnkx_datx_t;\n+\n+/**\n+ * cvmx_dtx_ocx_lnk#_ena#\n+ */\n+union cvmx_dtx_ocx_lnkx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_lnkx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_lnkx_enax_s cn78xx;\n+\tstruct cvmx_dtx_ocx_lnkx_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_lnkx_enax cvmx_dtx_ocx_lnkx_enax_t;\n+\n+/**\n+ * cvmx_dtx_ocx_lnk#_sel#\n+ */\n+union cvmx_dtx_ocx_lnkx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_lnkx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_lnkx_selx_s cn78xx;\n+\tstruct cvmx_dtx_ocx_lnkx_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_lnkx_selx cvmx_dtx_ocx_lnkx_selx_t;\n+\n+/**\n+ * cvmx_dtx_ocx_ole#_bcst_rsp\n+ */\n+union cvmx_dtx_ocx_olex_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_olex_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_olex_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_ocx_olex_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_olex_bcst_rsp cvmx_dtx_ocx_olex_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_ocx_ole#_ctl\n+ */\n+union cvmx_dtx_ocx_olex_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_olex_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_olex_ctl_s cn78xx;\n+\tstruct cvmx_dtx_ocx_olex_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_olex_ctl cvmx_dtx_ocx_olex_ctl_t;\n+\n+/**\n+ * cvmx_dtx_ocx_ole#_dat#\n+ */\n+union cvmx_dtx_ocx_olex_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_olex_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_olex_datx_s cn78xx;\n+\tstruct cvmx_dtx_ocx_olex_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_olex_datx cvmx_dtx_ocx_olex_datx_t;\n+\n+/**\n+ * cvmx_dtx_ocx_ole#_ena#\n+ */\n+union cvmx_dtx_ocx_olex_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_olex_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_olex_enax_s cn78xx;\n+\tstruct cvmx_dtx_ocx_olex_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_olex_enax cvmx_dtx_ocx_olex_enax_t;\n+\n+/**\n+ * cvmx_dtx_ocx_ole#_sel#\n+ */\n+union cvmx_dtx_ocx_olex_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_olex_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_olex_selx_s cn78xx;\n+\tstruct cvmx_dtx_ocx_olex_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_olex_selx cvmx_dtx_ocx_olex_selx_t;\n+\n+/**\n+ * cvmx_dtx_ocx_top_bcst_rsp\n+ */\n+union cvmx_dtx_ocx_top_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_top_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_top_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_ocx_top_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_top_bcst_rsp cvmx_dtx_ocx_top_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_ocx_top_ctl\n+ */\n+union cvmx_dtx_ocx_top_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_top_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_top_ctl_s cn78xx;\n+\tstruct cvmx_dtx_ocx_top_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_top_ctl cvmx_dtx_ocx_top_ctl_t;\n+\n+/**\n+ * cvmx_dtx_ocx_top_dat#\n+ */\n+union cvmx_dtx_ocx_top_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_top_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_top_datx_s cn78xx;\n+\tstruct cvmx_dtx_ocx_top_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_top_datx cvmx_dtx_ocx_top_datx_t;\n+\n+/**\n+ * cvmx_dtx_ocx_top_ena#\n+ */\n+union cvmx_dtx_ocx_top_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_top_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_top_enax_s cn78xx;\n+\tstruct cvmx_dtx_ocx_top_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_top_enax cvmx_dtx_ocx_top_enax_t;\n+\n+/**\n+ * cvmx_dtx_ocx_top_sel#\n+ */\n+union cvmx_dtx_ocx_top_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ocx_top_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_ocx_top_selx_s cn78xx;\n+\tstruct cvmx_dtx_ocx_top_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_ocx_top_selx cvmx_dtx_ocx_top_selx_t;\n+\n+/**\n+ * cvmx_dtx_osm_bcst_rsp\n+ */\n+union cvmx_dtx_osm_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_osm_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_osm_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_osm_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_osm_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_osm_bcst_rsp cvmx_dtx_osm_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_osm_ctl\n+ */\n+union cvmx_dtx_osm_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_osm_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_osm_ctl_s cn73xx;\n+\tstruct cvmx_dtx_osm_ctl_s cn78xx;\n+\tstruct cvmx_dtx_osm_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_osm_ctl cvmx_dtx_osm_ctl_t;\n+\n+/**\n+ * cvmx_dtx_osm_dat#\n+ */\n+union cvmx_dtx_osm_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_osm_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_osm_datx_s cn73xx;\n+\tstruct cvmx_dtx_osm_datx_s cn78xx;\n+\tstruct cvmx_dtx_osm_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_osm_datx cvmx_dtx_osm_datx_t;\n+\n+/**\n+ * cvmx_dtx_osm_ena#\n+ */\n+union cvmx_dtx_osm_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_osm_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_osm_enax_s cn73xx;\n+\tstruct cvmx_dtx_osm_enax_s cn78xx;\n+\tstruct cvmx_dtx_osm_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_osm_enax cvmx_dtx_osm_enax_t;\n+\n+/**\n+ * cvmx_dtx_osm_sel#\n+ */\n+union cvmx_dtx_osm_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_osm_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_osm_selx_s cn73xx;\n+\tstruct cvmx_dtx_osm_selx_s cn78xx;\n+\tstruct cvmx_dtx_osm_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_osm_selx cvmx_dtx_osm_selx_t;\n+\n+/**\n+ * cvmx_dtx_pcs#_bcst_rsp\n+ */\n+union cvmx_dtx_pcsx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pcsx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pcsx_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_pcsx_bcst_rsp_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pcsx_bcst_rsp cvmx_dtx_pcsx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_pcs#_ctl\n+ */\n+union cvmx_dtx_pcsx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pcsx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pcsx_ctl_s cn70xx;\n+\tstruct cvmx_dtx_pcsx_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pcsx_ctl cvmx_dtx_pcsx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_pcs#_dat#\n+ */\n+union cvmx_dtx_pcsx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pcsx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pcsx_datx_s cn70xx;\n+\tstruct cvmx_dtx_pcsx_datx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pcsx_datx cvmx_dtx_pcsx_datx_t;\n+\n+/**\n+ * cvmx_dtx_pcs#_ena#\n+ */\n+union cvmx_dtx_pcsx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pcsx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pcsx_enax_s cn70xx;\n+\tstruct cvmx_dtx_pcsx_enax_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pcsx_enax cvmx_dtx_pcsx_enax_t;\n+\n+/**\n+ * cvmx_dtx_pcs#_sel#\n+ */\n+union cvmx_dtx_pcsx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pcsx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_pcsx_selx_s cn70xx;\n+\tstruct cvmx_dtx_pcsx_selx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pcsx_selx cvmx_dtx_pcsx_selx_t;\n+\n+/**\n+ * cvmx_dtx_pem#_bcst_rsp\n+ */\n+union cvmx_dtx_pemx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pemx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pemx_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_pemx_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_pemx_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_pemx_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_pemx_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_pemx_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pemx_bcst_rsp cvmx_dtx_pemx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_pem#_ctl\n+ */\n+union cvmx_dtx_pemx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pemx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pemx_ctl_s cn70xx;\n+\tstruct cvmx_dtx_pemx_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_pemx_ctl_s cn73xx;\n+\tstruct cvmx_dtx_pemx_ctl_s cn78xx;\n+\tstruct cvmx_dtx_pemx_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_pemx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pemx_ctl cvmx_dtx_pemx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_pem#_dat#\n+ */\n+union cvmx_dtx_pemx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pemx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pemx_datx_s cn70xx;\n+\tstruct cvmx_dtx_pemx_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_pemx_datx_s cn73xx;\n+\tstruct cvmx_dtx_pemx_datx_s cn78xx;\n+\tstruct cvmx_dtx_pemx_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_pemx_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pemx_datx cvmx_dtx_pemx_datx_t;\n+\n+/**\n+ * cvmx_dtx_pem#_ena#\n+ */\n+union cvmx_dtx_pemx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pemx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pemx_enax_s cn70xx;\n+\tstruct cvmx_dtx_pemx_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_pemx_enax_s cn73xx;\n+\tstruct cvmx_dtx_pemx_enax_s cn78xx;\n+\tstruct cvmx_dtx_pemx_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_pemx_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pemx_enax cvmx_dtx_pemx_enax_t;\n+\n+/**\n+ * cvmx_dtx_pem#_sel#\n+ */\n+union cvmx_dtx_pemx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pemx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_pemx_selx_s cn70xx;\n+\tstruct cvmx_dtx_pemx_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_pemx_selx_s cn73xx;\n+\tstruct cvmx_dtx_pemx_selx_s cn78xx;\n+\tstruct cvmx_dtx_pemx_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_pemx_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pemx_selx cvmx_dtx_pemx_selx_t;\n+\n+/**\n+ * cvmx_dtx_pip_bcst_rsp\n+ */\n+union cvmx_dtx_pip_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pip_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pip_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_pip_bcst_rsp_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pip_bcst_rsp cvmx_dtx_pip_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_pip_ctl\n+ */\n+union cvmx_dtx_pip_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pip_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pip_ctl_s cn70xx;\n+\tstruct cvmx_dtx_pip_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pip_ctl cvmx_dtx_pip_ctl_t;\n+\n+/**\n+ * cvmx_dtx_pip_dat#\n+ */\n+union cvmx_dtx_pip_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pip_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pip_datx_s cn70xx;\n+\tstruct cvmx_dtx_pip_datx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pip_datx cvmx_dtx_pip_datx_t;\n+\n+/**\n+ * cvmx_dtx_pip_ena#\n+ */\n+union cvmx_dtx_pip_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pip_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pip_enax_s cn70xx;\n+\tstruct cvmx_dtx_pip_enax_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pip_enax cvmx_dtx_pip_enax_t;\n+\n+/**\n+ * cvmx_dtx_pip_sel#\n+ */\n+union cvmx_dtx_pip_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pip_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_pip_selx_s cn70xx;\n+\tstruct cvmx_dtx_pip_selx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pip_selx cvmx_dtx_pip_selx_t;\n+\n+/**\n+ * cvmx_dtx_pki_pbe_bcst_rsp\n+ */\n+union cvmx_dtx_pki_pbe_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pbe_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pbe_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_pki_pbe_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_pki_pbe_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pbe_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pbe_bcst_rsp cvmx_dtx_pki_pbe_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_pki_pbe_ctl\n+ */\n+union cvmx_dtx_pki_pbe_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pbe_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pbe_ctl_s cn73xx;\n+\tstruct cvmx_dtx_pki_pbe_ctl_s cn78xx;\n+\tstruct cvmx_dtx_pki_pbe_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pbe_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pbe_ctl cvmx_dtx_pki_pbe_ctl_t;\n+\n+/**\n+ * cvmx_dtx_pki_pbe_dat#\n+ */\n+union cvmx_dtx_pki_pbe_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pbe_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pbe_datx_s cn73xx;\n+\tstruct cvmx_dtx_pki_pbe_datx_s cn78xx;\n+\tstruct cvmx_dtx_pki_pbe_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pbe_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pbe_datx cvmx_dtx_pki_pbe_datx_t;\n+\n+/**\n+ * cvmx_dtx_pki_pbe_ena#\n+ */\n+union cvmx_dtx_pki_pbe_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pbe_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pbe_enax_s cn73xx;\n+\tstruct cvmx_dtx_pki_pbe_enax_s cn78xx;\n+\tstruct cvmx_dtx_pki_pbe_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pbe_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pbe_enax cvmx_dtx_pki_pbe_enax_t;\n+\n+/**\n+ * cvmx_dtx_pki_pbe_sel#\n+ */\n+union cvmx_dtx_pki_pbe_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pbe_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pbe_selx_s cn73xx;\n+\tstruct cvmx_dtx_pki_pbe_selx_s cn78xx;\n+\tstruct cvmx_dtx_pki_pbe_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pbe_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pbe_selx cvmx_dtx_pki_pbe_selx_t;\n+\n+/**\n+ * cvmx_dtx_pki_pfe_bcst_rsp\n+ */\n+union cvmx_dtx_pki_pfe_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pfe_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pfe_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_pki_pfe_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_pki_pfe_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pfe_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pfe_bcst_rsp cvmx_dtx_pki_pfe_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_pki_pfe_ctl\n+ */\n+union cvmx_dtx_pki_pfe_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pfe_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pfe_ctl_s cn73xx;\n+\tstruct cvmx_dtx_pki_pfe_ctl_s cn78xx;\n+\tstruct cvmx_dtx_pki_pfe_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pfe_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pfe_ctl cvmx_dtx_pki_pfe_ctl_t;\n+\n+/**\n+ * cvmx_dtx_pki_pfe_dat#\n+ */\n+union cvmx_dtx_pki_pfe_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pfe_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pfe_datx_s cn73xx;\n+\tstruct cvmx_dtx_pki_pfe_datx_s cn78xx;\n+\tstruct cvmx_dtx_pki_pfe_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pfe_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pfe_datx cvmx_dtx_pki_pfe_datx_t;\n+\n+/**\n+ * cvmx_dtx_pki_pfe_ena#\n+ */\n+union cvmx_dtx_pki_pfe_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pfe_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pfe_enax_s cn73xx;\n+\tstruct cvmx_dtx_pki_pfe_enax_s cn78xx;\n+\tstruct cvmx_dtx_pki_pfe_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pfe_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pfe_enax cvmx_dtx_pki_pfe_enax_t;\n+\n+/**\n+ * cvmx_dtx_pki_pfe_sel#\n+ */\n+union cvmx_dtx_pki_pfe_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pfe_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pfe_selx_s cn73xx;\n+\tstruct cvmx_dtx_pki_pfe_selx_s cn78xx;\n+\tstruct cvmx_dtx_pki_pfe_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pfe_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pfe_selx cvmx_dtx_pki_pfe_selx_t;\n+\n+/**\n+ * cvmx_dtx_pki_pix_bcst_rsp\n+ */\n+union cvmx_dtx_pki_pix_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pix_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pix_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_pki_pix_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_pki_pix_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pix_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pix_bcst_rsp cvmx_dtx_pki_pix_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_pki_pix_ctl\n+ */\n+union cvmx_dtx_pki_pix_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pix_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pix_ctl_s cn73xx;\n+\tstruct cvmx_dtx_pki_pix_ctl_s cn78xx;\n+\tstruct cvmx_dtx_pki_pix_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pix_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pix_ctl cvmx_dtx_pki_pix_ctl_t;\n+\n+/**\n+ * cvmx_dtx_pki_pix_dat#\n+ */\n+union cvmx_dtx_pki_pix_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pix_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pix_datx_s cn73xx;\n+\tstruct cvmx_dtx_pki_pix_datx_s cn78xx;\n+\tstruct cvmx_dtx_pki_pix_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pix_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pix_datx cvmx_dtx_pki_pix_datx_t;\n+\n+/**\n+ * cvmx_dtx_pki_pix_ena#\n+ */\n+union cvmx_dtx_pki_pix_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pix_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pix_enax_s cn73xx;\n+\tstruct cvmx_dtx_pki_pix_enax_s cn78xx;\n+\tstruct cvmx_dtx_pki_pix_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pix_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pix_enax cvmx_dtx_pki_pix_enax_t;\n+\n+/**\n+ * cvmx_dtx_pki_pix_sel#\n+ */\n+union cvmx_dtx_pki_pix_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pki_pix_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_pki_pix_selx_s cn73xx;\n+\tstruct cvmx_dtx_pki_pix_selx_s cn78xx;\n+\tstruct cvmx_dtx_pki_pix_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_pki_pix_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pki_pix_selx cvmx_dtx_pki_pix_selx_t;\n+\n+/**\n+ * cvmx_dtx_pko_bcst_rsp\n+ */\n+union cvmx_dtx_pko_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pko_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pko_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_pko_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_pko_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_pko_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_pko_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_pko_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pko_bcst_rsp cvmx_dtx_pko_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_pko_ctl\n+ */\n+union cvmx_dtx_pko_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pko_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pko_ctl_s cn70xx;\n+\tstruct cvmx_dtx_pko_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_pko_ctl_s cn73xx;\n+\tstruct cvmx_dtx_pko_ctl_s cn78xx;\n+\tstruct cvmx_dtx_pko_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_pko_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pko_ctl cvmx_dtx_pko_ctl_t;\n+\n+/**\n+ * cvmx_dtx_pko_dat#\n+ */\n+union cvmx_dtx_pko_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pko_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pko_datx_s cn70xx;\n+\tstruct cvmx_dtx_pko_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_pko_datx_s cn73xx;\n+\tstruct cvmx_dtx_pko_datx_s cn78xx;\n+\tstruct cvmx_dtx_pko_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_pko_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pko_datx cvmx_dtx_pko_datx_t;\n+\n+/**\n+ * cvmx_dtx_pko_ena#\n+ */\n+union cvmx_dtx_pko_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pko_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pko_enax_s cn70xx;\n+\tstruct cvmx_dtx_pko_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_pko_enax_s cn73xx;\n+\tstruct cvmx_dtx_pko_enax_s cn78xx;\n+\tstruct cvmx_dtx_pko_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_pko_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pko_enax cvmx_dtx_pko_enax_t;\n+\n+/**\n+ * cvmx_dtx_pko_sel#\n+ */\n+union cvmx_dtx_pko_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pko_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_pko_selx_s cn70xx;\n+\tstruct cvmx_dtx_pko_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_pko_selx_s cn73xx;\n+\tstruct cvmx_dtx_pko_selx_s cn78xx;\n+\tstruct cvmx_dtx_pko_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_pko_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pko_selx cvmx_dtx_pko_selx_t;\n+\n+/**\n+ * cvmx_dtx_pnb#_bcst_rsp\n+ */\n+union cvmx_dtx_pnbx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pnbx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pnbx_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pnbx_bcst_rsp cvmx_dtx_pnbx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_pnb#_ctl\n+ */\n+union cvmx_dtx_pnbx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pnbx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pnbx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pnbx_ctl cvmx_dtx_pnbx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_pnb#_dat#\n+ */\n+union cvmx_dtx_pnbx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pnbx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pnbx_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pnbx_datx cvmx_dtx_pnbx_datx_t;\n+\n+/**\n+ * cvmx_dtx_pnb#_ena#\n+ */\n+union cvmx_dtx_pnbx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pnbx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pnbx_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pnbx_enax cvmx_dtx_pnbx_enax_t;\n+\n+/**\n+ * cvmx_dtx_pnb#_sel#\n+ */\n+union cvmx_dtx_pnbx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pnbx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_pnbx_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pnbx_selx cvmx_dtx_pnbx_selx_t;\n+\n+/**\n+ * cvmx_dtx_pnbd#_bcst_rsp\n+ */\n+union cvmx_dtx_pnbdx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pnbdx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pnbdx_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pnbdx_bcst_rsp cvmx_dtx_pnbdx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_pnbd#_ctl\n+ */\n+union cvmx_dtx_pnbdx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pnbdx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pnbdx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pnbdx_ctl cvmx_dtx_pnbdx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_pnbd#_dat#\n+ */\n+union cvmx_dtx_pnbdx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pnbdx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pnbdx_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pnbdx_datx cvmx_dtx_pnbdx_datx_t;\n+\n+/**\n+ * cvmx_dtx_pnbd#_ena#\n+ */\n+union cvmx_dtx_pnbdx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pnbdx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pnbdx_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pnbdx_enax cvmx_dtx_pnbdx_enax_t;\n+\n+/**\n+ * cvmx_dtx_pnbd#_sel#\n+ */\n+union cvmx_dtx_pnbdx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pnbdx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_pnbdx_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_pnbdx_selx cvmx_dtx_pnbdx_selx_t;\n+\n+/**\n+ * cvmx_dtx_pow_bcst_rsp\n+ */\n+union cvmx_dtx_pow_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pow_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pow_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_pow_bcst_rsp_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pow_bcst_rsp cvmx_dtx_pow_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_pow_ctl\n+ */\n+union cvmx_dtx_pow_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pow_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_pow_ctl_s cn70xx;\n+\tstruct cvmx_dtx_pow_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pow_ctl cvmx_dtx_pow_ctl_t;\n+\n+/**\n+ * cvmx_dtx_pow_dat#\n+ */\n+union cvmx_dtx_pow_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pow_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pow_datx_s cn70xx;\n+\tstruct cvmx_dtx_pow_datx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pow_datx cvmx_dtx_pow_datx_t;\n+\n+/**\n+ * cvmx_dtx_pow_ena#\n+ */\n+union cvmx_dtx_pow_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pow_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_pow_enax_s cn70xx;\n+\tstruct cvmx_dtx_pow_enax_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pow_enax cvmx_dtx_pow_enax_t;\n+\n+/**\n+ * cvmx_dtx_pow_sel#\n+ */\n+union cvmx_dtx_pow_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_pow_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_pow_selx_s cn70xx;\n+\tstruct cvmx_dtx_pow_selx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_dtx_pow_selx cvmx_dtx_pow_selx_t;\n+\n+/**\n+ * cvmx_dtx_prch_bcst_rsp\n+ */\n+union cvmx_dtx_prch_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_prch_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_prch_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_prch_bcst_rsp cvmx_dtx_prch_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_prch_ctl\n+ */\n+union cvmx_dtx_prch_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_prch_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_prch_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_prch_ctl cvmx_dtx_prch_ctl_t;\n+\n+/**\n+ * cvmx_dtx_prch_dat#\n+ */\n+union cvmx_dtx_prch_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_prch_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_prch_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_prch_datx cvmx_dtx_prch_datx_t;\n+\n+/**\n+ * cvmx_dtx_prch_ena#\n+ */\n+union cvmx_dtx_prch_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_prch_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_prch_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_prch_enax cvmx_dtx_prch_enax_t;\n+\n+/**\n+ * cvmx_dtx_prch_sel#\n+ */\n+union cvmx_dtx_prch_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_prch_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_prch_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_prch_selx cvmx_dtx_prch_selx_t;\n+\n+/**\n+ * cvmx_dtx_psm_bcst_rsp\n+ */\n+union cvmx_dtx_psm_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_psm_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_psm_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_psm_bcst_rsp cvmx_dtx_psm_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_psm_ctl\n+ */\n+union cvmx_dtx_psm_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_psm_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_psm_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_psm_ctl cvmx_dtx_psm_ctl_t;\n+\n+/**\n+ * cvmx_dtx_psm_dat#\n+ */\n+union cvmx_dtx_psm_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_psm_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_psm_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_psm_datx cvmx_dtx_psm_datx_t;\n+\n+/**\n+ * cvmx_dtx_psm_ena#\n+ */\n+union cvmx_dtx_psm_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_psm_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_psm_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_psm_enax cvmx_dtx_psm_enax_t;\n+\n+/**\n+ * cvmx_dtx_psm_sel#\n+ */\n+union cvmx_dtx_psm_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_psm_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_psm_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_psm_selx cvmx_dtx_psm_selx_t;\n+\n+/**\n+ * cvmx_dtx_rad_bcst_rsp\n+ */\n+union cvmx_dtx_rad_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rad_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_rad_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_rad_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_rad_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_rad_bcst_rsp cvmx_dtx_rad_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_rad_ctl\n+ */\n+union cvmx_dtx_rad_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rad_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_rad_ctl_s cn73xx;\n+\tstruct cvmx_dtx_rad_ctl_s cn78xx;\n+\tstruct cvmx_dtx_rad_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_rad_ctl cvmx_dtx_rad_ctl_t;\n+\n+/**\n+ * cvmx_dtx_rad_dat#\n+ */\n+union cvmx_dtx_rad_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rad_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_rad_datx_s cn73xx;\n+\tstruct cvmx_dtx_rad_datx_s cn78xx;\n+\tstruct cvmx_dtx_rad_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_rad_datx cvmx_dtx_rad_datx_t;\n+\n+/**\n+ * cvmx_dtx_rad_ena#\n+ */\n+union cvmx_dtx_rad_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rad_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_rad_enax_s cn73xx;\n+\tstruct cvmx_dtx_rad_enax_s cn78xx;\n+\tstruct cvmx_dtx_rad_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_rad_enax cvmx_dtx_rad_enax_t;\n+\n+/**\n+ * cvmx_dtx_rad_sel#\n+ */\n+union cvmx_dtx_rad_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rad_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_rad_selx_s cn73xx;\n+\tstruct cvmx_dtx_rad_selx_s cn78xx;\n+\tstruct cvmx_dtx_rad_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_rad_selx cvmx_dtx_rad_selx_t;\n+\n+/**\n+ * cvmx_dtx_rdec_bcst_rsp\n+ */\n+union cvmx_dtx_rdec_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rdec_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_rdec_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rdec_bcst_rsp cvmx_dtx_rdec_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_rdec_ctl\n+ */\n+union cvmx_dtx_rdec_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rdec_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_rdec_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rdec_ctl cvmx_dtx_rdec_ctl_t;\n+\n+/**\n+ * cvmx_dtx_rdec_dat#\n+ */\n+union cvmx_dtx_rdec_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rdec_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_rdec_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rdec_datx cvmx_dtx_rdec_datx_t;\n+\n+/**\n+ * cvmx_dtx_rdec_ena#\n+ */\n+union cvmx_dtx_rdec_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rdec_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_rdec_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rdec_enax cvmx_dtx_rdec_enax_t;\n+\n+/**\n+ * cvmx_dtx_rdec_sel#\n+ */\n+union cvmx_dtx_rdec_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rdec_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_rdec_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rdec_selx cvmx_dtx_rdec_selx_t;\n+\n+/**\n+ * cvmx_dtx_rfif_bcst_rsp\n+ */\n+union cvmx_dtx_rfif_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rfif_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_rfif_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rfif_bcst_rsp cvmx_dtx_rfif_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_rfif_ctl\n+ */\n+union cvmx_dtx_rfif_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rfif_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_rfif_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rfif_ctl cvmx_dtx_rfif_ctl_t;\n+\n+/**\n+ * cvmx_dtx_rfif_dat#\n+ */\n+union cvmx_dtx_rfif_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rfif_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_rfif_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rfif_datx cvmx_dtx_rfif_datx_t;\n+\n+/**\n+ * cvmx_dtx_rfif_ena#\n+ */\n+union cvmx_dtx_rfif_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rfif_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_rfif_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rfif_enax cvmx_dtx_rfif_enax_t;\n+\n+/**\n+ * cvmx_dtx_rfif_sel#\n+ */\n+union cvmx_dtx_rfif_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rfif_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_rfif_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rfif_selx cvmx_dtx_rfif_selx_t;\n+\n+/**\n+ * cvmx_dtx_rmap_bcst_rsp\n+ */\n+union cvmx_dtx_rmap_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rmap_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_rmap_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rmap_bcst_rsp cvmx_dtx_rmap_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_rmap_ctl\n+ */\n+union cvmx_dtx_rmap_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rmap_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_rmap_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rmap_ctl cvmx_dtx_rmap_ctl_t;\n+\n+/**\n+ * cvmx_dtx_rmap_dat#\n+ */\n+union cvmx_dtx_rmap_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rmap_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_rmap_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rmap_datx cvmx_dtx_rmap_datx_t;\n+\n+/**\n+ * cvmx_dtx_rmap_ena#\n+ */\n+union cvmx_dtx_rmap_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rmap_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_rmap_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rmap_enax cvmx_dtx_rmap_enax_t;\n+\n+/**\n+ * cvmx_dtx_rmap_sel#\n+ */\n+union cvmx_dtx_rmap_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rmap_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_rmap_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rmap_selx cvmx_dtx_rmap_selx_t;\n+\n+/**\n+ * cvmx_dtx_rnm_bcst_rsp\n+ */\n+union cvmx_dtx_rnm_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rnm_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_rnm_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_rnm_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_rnm_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_rnm_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rnm_bcst_rsp cvmx_dtx_rnm_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_rnm_ctl\n+ */\n+union cvmx_dtx_rnm_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rnm_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_rnm_ctl_s cn73xx;\n+\tstruct cvmx_dtx_rnm_ctl_s cn78xx;\n+\tstruct cvmx_dtx_rnm_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_rnm_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rnm_ctl cvmx_dtx_rnm_ctl_t;\n+\n+/**\n+ * cvmx_dtx_rnm_dat#\n+ */\n+union cvmx_dtx_rnm_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rnm_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_rnm_datx_s cn73xx;\n+\tstruct cvmx_dtx_rnm_datx_s cn78xx;\n+\tstruct cvmx_dtx_rnm_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_rnm_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rnm_datx cvmx_dtx_rnm_datx_t;\n+\n+/**\n+ * cvmx_dtx_rnm_ena#\n+ */\n+union cvmx_dtx_rnm_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rnm_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_rnm_enax_s cn73xx;\n+\tstruct cvmx_dtx_rnm_enax_s cn78xx;\n+\tstruct cvmx_dtx_rnm_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_rnm_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rnm_enax cvmx_dtx_rnm_enax_t;\n+\n+/**\n+ * cvmx_dtx_rnm_sel#\n+ */\n+union cvmx_dtx_rnm_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rnm_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_rnm_selx_s cn73xx;\n+\tstruct cvmx_dtx_rnm_selx_s cn78xx;\n+\tstruct cvmx_dtx_rnm_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_rnm_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rnm_selx cvmx_dtx_rnm_selx_t;\n+\n+/**\n+ * cvmx_dtx_rst_bcst_rsp\n+ */\n+union cvmx_dtx_rst_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rst_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_rst_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_rst_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_rst_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_rst_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_rst_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_rst_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rst_bcst_rsp cvmx_dtx_rst_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_rst_ctl\n+ */\n+union cvmx_dtx_rst_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rst_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_rst_ctl_s cn70xx;\n+\tstruct cvmx_dtx_rst_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_rst_ctl_s cn73xx;\n+\tstruct cvmx_dtx_rst_ctl_s cn78xx;\n+\tstruct cvmx_dtx_rst_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_rst_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rst_ctl cvmx_dtx_rst_ctl_t;\n+\n+/**\n+ * cvmx_dtx_rst_dat#\n+ */\n+union cvmx_dtx_rst_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rst_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_rst_datx_s cn70xx;\n+\tstruct cvmx_dtx_rst_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_rst_datx_s cn73xx;\n+\tstruct cvmx_dtx_rst_datx_s cn78xx;\n+\tstruct cvmx_dtx_rst_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_rst_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rst_datx cvmx_dtx_rst_datx_t;\n+\n+/**\n+ * cvmx_dtx_rst_ena#\n+ */\n+union cvmx_dtx_rst_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rst_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_rst_enax_s cn70xx;\n+\tstruct cvmx_dtx_rst_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_rst_enax_s cn73xx;\n+\tstruct cvmx_dtx_rst_enax_s cn78xx;\n+\tstruct cvmx_dtx_rst_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_rst_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rst_enax cvmx_dtx_rst_enax_t;\n+\n+/**\n+ * cvmx_dtx_rst_sel#\n+ */\n+union cvmx_dtx_rst_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_rst_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_rst_selx_s cn70xx;\n+\tstruct cvmx_dtx_rst_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_rst_selx_s cn73xx;\n+\tstruct cvmx_dtx_rst_selx_s cn78xx;\n+\tstruct cvmx_dtx_rst_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_rst_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_rst_selx cvmx_dtx_rst_selx_t;\n+\n+/**\n+ * cvmx_dtx_sata_bcst_rsp\n+ */\n+union cvmx_dtx_sata_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sata_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_sata_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_sata_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_sata_bcst_rsp_s cn73xx;\n+};\n+\n+typedef union cvmx_dtx_sata_bcst_rsp cvmx_dtx_sata_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_sata_ctl\n+ */\n+union cvmx_dtx_sata_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sata_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_sata_ctl_s cn70xx;\n+\tstruct cvmx_dtx_sata_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_sata_ctl_s cn73xx;\n+};\n+\n+typedef union cvmx_dtx_sata_ctl cvmx_dtx_sata_ctl_t;\n+\n+/**\n+ * cvmx_dtx_sata_dat#\n+ */\n+union cvmx_dtx_sata_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sata_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_sata_datx_s cn70xx;\n+\tstruct cvmx_dtx_sata_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_sata_datx_s cn73xx;\n+};\n+\n+typedef union cvmx_dtx_sata_datx cvmx_dtx_sata_datx_t;\n+\n+/**\n+ * cvmx_dtx_sata_ena#\n+ */\n+union cvmx_dtx_sata_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sata_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_sata_enax_s cn70xx;\n+\tstruct cvmx_dtx_sata_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_sata_enax_s cn73xx;\n+};\n+\n+typedef union cvmx_dtx_sata_enax cvmx_dtx_sata_enax_t;\n+\n+/**\n+ * cvmx_dtx_sata_sel#\n+ */\n+union cvmx_dtx_sata_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sata_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_sata_selx_s cn70xx;\n+\tstruct cvmx_dtx_sata_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_sata_selx_s cn73xx;\n+};\n+\n+typedef union cvmx_dtx_sata_selx cvmx_dtx_sata_selx_t;\n+\n+/**\n+ * cvmx_dtx_sli_bcst_rsp\n+ */\n+union cvmx_dtx_sli_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sli_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_sli_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_sli_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_sli_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_sli_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_sli_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_sli_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sli_bcst_rsp cvmx_dtx_sli_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_sli_ctl\n+ */\n+union cvmx_dtx_sli_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sli_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_sli_ctl_s cn70xx;\n+\tstruct cvmx_dtx_sli_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_sli_ctl_s cn73xx;\n+\tstruct cvmx_dtx_sli_ctl_s cn78xx;\n+\tstruct cvmx_dtx_sli_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_sli_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sli_ctl cvmx_dtx_sli_ctl_t;\n+\n+/**\n+ * cvmx_dtx_sli_dat#\n+ */\n+union cvmx_dtx_sli_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sli_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_sli_datx_s cn70xx;\n+\tstruct cvmx_dtx_sli_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_sli_datx_s cn73xx;\n+\tstruct cvmx_dtx_sli_datx_s cn78xx;\n+\tstruct cvmx_dtx_sli_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_sli_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sli_datx cvmx_dtx_sli_datx_t;\n+\n+/**\n+ * cvmx_dtx_sli_ena#\n+ */\n+union cvmx_dtx_sli_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sli_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_sli_enax_s cn70xx;\n+\tstruct cvmx_dtx_sli_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_sli_enax_s cn73xx;\n+\tstruct cvmx_dtx_sli_enax_s cn78xx;\n+\tstruct cvmx_dtx_sli_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_sli_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sli_enax cvmx_dtx_sli_enax_t;\n+\n+/**\n+ * cvmx_dtx_sli_sel#\n+ */\n+union cvmx_dtx_sli_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sli_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_sli_selx_s cn70xx;\n+\tstruct cvmx_dtx_sli_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_sli_selx_s cn73xx;\n+\tstruct cvmx_dtx_sli_selx_s cn78xx;\n+\tstruct cvmx_dtx_sli_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_sli_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sli_selx cvmx_dtx_sli_selx_t;\n+\n+/**\n+ * cvmx_dtx_spem_bcst_rsp\n+ */\n+union cvmx_dtx_spem_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_spem_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_spem_bcst_rsp_s cn73xx;\n+};\n+\n+typedef union cvmx_dtx_spem_bcst_rsp cvmx_dtx_spem_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_spem_ctl\n+ */\n+union cvmx_dtx_spem_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_spem_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_spem_ctl_s cn73xx;\n+};\n+\n+typedef union cvmx_dtx_spem_ctl cvmx_dtx_spem_ctl_t;\n+\n+/**\n+ * cvmx_dtx_spem_dat#\n+ */\n+union cvmx_dtx_spem_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_spem_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_spem_datx_s cn73xx;\n+};\n+\n+typedef union cvmx_dtx_spem_datx cvmx_dtx_spem_datx_t;\n+\n+/**\n+ * cvmx_dtx_spem_ena#\n+ */\n+union cvmx_dtx_spem_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_spem_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_spem_enax_s cn73xx;\n+};\n+\n+typedef union cvmx_dtx_spem_enax cvmx_dtx_spem_enax_t;\n+\n+/**\n+ * cvmx_dtx_spem_sel#\n+ */\n+union cvmx_dtx_spem_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_spem_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_spem_selx_s cn73xx;\n+};\n+\n+typedef union cvmx_dtx_spem_selx cvmx_dtx_spem_selx_t;\n+\n+/**\n+ * cvmx_dtx_srio#_bcst_rsp\n+ */\n+union cvmx_dtx_sriox_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sriox_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_sriox_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sriox_bcst_rsp cvmx_dtx_sriox_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_srio#_ctl\n+ */\n+union cvmx_dtx_sriox_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sriox_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_sriox_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sriox_ctl cvmx_dtx_sriox_ctl_t;\n+\n+/**\n+ * cvmx_dtx_srio#_dat#\n+ */\n+union cvmx_dtx_sriox_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sriox_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_sriox_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sriox_datx cvmx_dtx_sriox_datx_t;\n+\n+/**\n+ * cvmx_dtx_srio#_ena#\n+ */\n+union cvmx_dtx_sriox_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sriox_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_sriox_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sriox_enax cvmx_dtx_sriox_enax_t;\n+\n+/**\n+ * cvmx_dtx_srio#_sel#\n+ */\n+union cvmx_dtx_sriox_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sriox_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_sriox_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sriox_selx cvmx_dtx_sriox_selx_t;\n+\n+/**\n+ * cvmx_dtx_sso_bcst_rsp\n+ */\n+union cvmx_dtx_sso_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sso_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_sso_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_sso_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_sso_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_sso_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sso_bcst_rsp cvmx_dtx_sso_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_sso_ctl\n+ */\n+union cvmx_dtx_sso_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sso_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_sso_ctl_s cn73xx;\n+\tstruct cvmx_dtx_sso_ctl_s cn78xx;\n+\tstruct cvmx_dtx_sso_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_sso_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sso_ctl cvmx_dtx_sso_ctl_t;\n+\n+/**\n+ * cvmx_dtx_sso_dat#\n+ */\n+union cvmx_dtx_sso_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sso_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_sso_datx_s cn73xx;\n+\tstruct cvmx_dtx_sso_datx_s cn78xx;\n+\tstruct cvmx_dtx_sso_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_sso_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sso_datx cvmx_dtx_sso_datx_t;\n+\n+/**\n+ * cvmx_dtx_sso_ena#\n+ */\n+union cvmx_dtx_sso_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sso_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_sso_enax_s cn73xx;\n+\tstruct cvmx_dtx_sso_enax_s cn78xx;\n+\tstruct cvmx_dtx_sso_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_sso_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sso_enax cvmx_dtx_sso_enax_t;\n+\n+/**\n+ * cvmx_dtx_sso_sel#\n+ */\n+union cvmx_dtx_sso_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_sso_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_sso_selx_s cn73xx;\n+\tstruct cvmx_dtx_sso_selx_s cn78xx;\n+\tstruct cvmx_dtx_sso_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_sso_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_sso_selx cvmx_dtx_sso_selx_t;\n+\n+/**\n+ * cvmx_dtx_tdec_bcst_rsp\n+ */\n+union cvmx_dtx_tdec_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_tdec_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_tdec_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_tdec_bcst_rsp cvmx_dtx_tdec_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_tdec_ctl\n+ */\n+union cvmx_dtx_tdec_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_tdec_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_tdec_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_tdec_ctl cvmx_dtx_tdec_ctl_t;\n+\n+/**\n+ * cvmx_dtx_tdec_dat#\n+ */\n+union cvmx_dtx_tdec_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_tdec_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_tdec_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_tdec_datx cvmx_dtx_tdec_datx_t;\n+\n+/**\n+ * cvmx_dtx_tdec_ena#\n+ */\n+union cvmx_dtx_tdec_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_tdec_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_tdec_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_tdec_enax cvmx_dtx_tdec_enax_t;\n+\n+/**\n+ * cvmx_dtx_tdec_sel#\n+ */\n+union cvmx_dtx_tdec_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_tdec_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_tdec_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_tdec_selx cvmx_dtx_tdec_selx_t;\n+\n+/**\n+ * cvmx_dtx_tim_bcst_rsp\n+ */\n+union cvmx_dtx_tim_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_tim_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_tim_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_tim_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_tim_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_tim_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_tim_bcst_rsp_s cn78xxp1;\n+\tstruct cvmx_dtx_tim_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_tim_bcst_rsp cvmx_dtx_tim_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_tim_ctl\n+ */\n+union cvmx_dtx_tim_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_tim_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_tim_ctl_s cn70xx;\n+\tstruct cvmx_dtx_tim_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_tim_ctl_s cn73xx;\n+\tstruct cvmx_dtx_tim_ctl_s cn78xx;\n+\tstruct cvmx_dtx_tim_ctl_s cn78xxp1;\n+\tstruct cvmx_dtx_tim_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_tim_ctl cvmx_dtx_tim_ctl_t;\n+\n+/**\n+ * cvmx_dtx_tim_dat#\n+ */\n+union cvmx_dtx_tim_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_tim_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_tim_datx_s cn70xx;\n+\tstruct cvmx_dtx_tim_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_tim_datx_s cn73xx;\n+\tstruct cvmx_dtx_tim_datx_s cn78xx;\n+\tstruct cvmx_dtx_tim_datx_s cn78xxp1;\n+\tstruct cvmx_dtx_tim_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_tim_datx cvmx_dtx_tim_datx_t;\n+\n+/**\n+ * cvmx_dtx_tim_ena#\n+ */\n+union cvmx_dtx_tim_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_tim_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_tim_enax_s cn70xx;\n+\tstruct cvmx_dtx_tim_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_tim_enax_s cn73xx;\n+\tstruct cvmx_dtx_tim_enax_s cn78xx;\n+\tstruct cvmx_dtx_tim_enax_s cn78xxp1;\n+\tstruct cvmx_dtx_tim_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_tim_enax cvmx_dtx_tim_enax_t;\n+\n+/**\n+ * cvmx_dtx_tim_sel#\n+ */\n+union cvmx_dtx_tim_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_tim_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_tim_selx_s cn70xx;\n+\tstruct cvmx_dtx_tim_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_tim_selx_s cn73xx;\n+\tstruct cvmx_dtx_tim_selx_s cn78xx;\n+\tstruct cvmx_dtx_tim_selx_s cn78xxp1;\n+\tstruct cvmx_dtx_tim_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_tim_selx cvmx_dtx_tim_selx_t;\n+\n+/**\n+ * cvmx_dtx_ulfe_bcst_rsp\n+ */\n+union cvmx_dtx_ulfe_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ulfe_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ulfe_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_ulfe_bcst_rsp cvmx_dtx_ulfe_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_ulfe_ctl\n+ */\n+union cvmx_dtx_ulfe_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ulfe_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_ulfe_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_ulfe_ctl cvmx_dtx_ulfe_ctl_t;\n+\n+/**\n+ * cvmx_dtx_ulfe_dat#\n+ */\n+union cvmx_dtx_ulfe_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ulfe_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ulfe_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_ulfe_datx cvmx_dtx_ulfe_datx_t;\n+\n+/**\n+ * cvmx_dtx_ulfe_ena#\n+ */\n+union cvmx_dtx_ulfe_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ulfe_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_ulfe_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_ulfe_enax cvmx_dtx_ulfe_enax_t;\n+\n+/**\n+ * cvmx_dtx_ulfe_sel#\n+ */\n+union cvmx_dtx_ulfe_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_ulfe_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_ulfe_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_ulfe_selx cvmx_dtx_ulfe_selx_t;\n+\n+/**\n+ * cvmx_dtx_usbdrd#_bcst_rsp\n+ */\n+union cvmx_dtx_usbdrdx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_usbdrdx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_usbdrdx_bcst_rsp_s cn70xx;\n+\tstruct cvmx_dtx_usbdrdx_bcst_rsp_s cn70xxp1;\n+\tstruct cvmx_dtx_usbdrdx_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_usbdrdx_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_usbdrdx_bcst_rsp cvmx_dtx_usbdrdx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_usbdrd#_ctl\n+ */\n+union cvmx_dtx_usbdrdx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_usbdrdx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_usbdrdx_ctl_s cn70xx;\n+\tstruct cvmx_dtx_usbdrdx_ctl_s cn70xxp1;\n+\tstruct cvmx_dtx_usbdrdx_ctl_s cn73xx;\n+\tstruct cvmx_dtx_usbdrdx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_usbdrdx_ctl cvmx_dtx_usbdrdx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_usbdrd#_dat#\n+ */\n+union cvmx_dtx_usbdrdx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_usbdrdx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_usbdrdx_datx_s cn70xx;\n+\tstruct cvmx_dtx_usbdrdx_datx_s cn70xxp1;\n+\tstruct cvmx_dtx_usbdrdx_datx_s cn73xx;\n+\tstruct cvmx_dtx_usbdrdx_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_usbdrdx_datx cvmx_dtx_usbdrdx_datx_t;\n+\n+/**\n+ * cvmx_dtx_usbdrd#_ena#\n+ */\n+union cvmx_dtx_usbdrdx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_usbdrdx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_usbdrdx_enax_s cn70xx;\n+\tstruct cvmx_dtx_usbdrdx_enax_s cn70xxp1;\n+\tstruct cvmx_dtx_usbdrdx_enax_s cn73xx;\n+\tstruct cvmx_dtx_usbdrdx_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_usbdrdx_enax cvmx_dtx_usbdrdx_enax_t;\n+\n+/**\n+ * cvmx_dtx_usbdrd#_sel#\n+ */\n+union cvmx_dtx_usbdrdx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_usbdrdx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_usbdrdx_selx_s cn70xx;\n+\tstruct cvmx_dtx_usbdrdx_selx_s cn70xxp1;\n+\tstruct cvmx_dtx_usbdrdx_selx_s cn73xx;\n+\tstruct cvmx_dtx_usbdrdx_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_usbdrdx_selx cvmx_dtx_usbdrdx_selx_t;\n+\n+/**\n+ * cvmx_dtx_usbh#_bcst_rsp\n+ */\n+union cvmx_dtx_usbhx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_usbhx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_usbhx_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_usbhx_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_usbhx_bcst_rsp cvmx_dtx_usbhx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_usbh#_ctl\n+ */\n+union cvmx_dtx_usbhx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_usbhx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_usbhx_ctl_s cn78xx;\n+\tstruct cvmx_dtx_usbhx_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_usbhx_ctl cvmx_dtx_usbhx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_usbh#_dat#\n+ */\n+union cvmx_dtx_usbhx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_usbhx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_usbhx_datx_s cn78xx;\n+\tstruct cvmx_dtx_usbhx_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_usbhx_datx cvmx_dtx_usbhx_datx_t;\n+\n+/**\n+ * cvmx_dtx_usbh#_ena#\n+ */\n+union cvmx_dtx_usbhx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_usbhx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_usbhx_enax_s cn78xx;\n+\tstruct cvmx_dtx_usbhx_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_usbhx_enax cvmx_dtx_usbhx_enax_t;\n+\n+/**\n+ * cvmx_dtx_usbh#_sel#\n+ */\n+union cvmx_dtx_usbhx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_usbhx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_usbhx_selx_s cn78xx;\n+\tstruct cvmx_dtx_usbhx_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_usbhx_selx cvmx_dtx_usbhx_selx_t;\n+\n+/**\n+ * cvmx_dtx_vdec_bcst_rsp\n+ */\n+union cvmx_dtx_vdec_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_vdec_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_vdec_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_vdec_bcst_rsp cvmx_dtx_vdec_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_vdec_ctl\n+ */\n+union cvmx_dtx_vdec_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_vdec_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_vdec_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_vdec_ctl cvmx_dtx_vdec_ctl_t;\n+\n+/**\n+ * cvmx_dtx_vdec_dat#\n+ */\n+union cvmx_dtx_vdec_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_vdec_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_vdec_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_vdec_datx cvmx_dtx_vdec_datx_t;\n+\n+/**\n+ * cvmx_dtx_vdec_ena#\n+ */\n+union cvmx_dtx_vdec_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_vdec_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_vdec_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_vdec_enax cvmx_dtx_vdec_enax_t;\n+\n+/**\n+ * cvmx_dtx_vdec_sel#\n+ */\n+union cvmx_dtx_vdec_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_vdec_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_vdec_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_vdec_selx cvmx_dtx_vdec_selx_t;\n+\n+/**\n+ * cvmx_dtx_wpse_bcst_rsp\n+ */\n+union cvmx_dtx_wpse_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wpse_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_wpse_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wpse_bcst_rsp cvmx_dtx_wpse_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_wpse_ctl\n+ */\n+union cvmx_dtx_wpse_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wpse_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_wpse_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wpse_ctl cvmx_dtx_wpse_ctl_t;\n+\n+/**\n+ * cvmx_dtx_wpse_dat#\n+ */\n+union cvmx_dtx_wpse_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wpse_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_wpse_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wpse_datx cvmx_dtx_wpse_datx_t;\n+\n+/**\n+ * cvmx_dtx_wpse_ena#\n+ */\n+union cvmx_dtx_wpse_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wpse_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_wpse_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wpse_enax cvmx_dtx_wpse_enax_t;\n+\n+/**\n+ * cvmx_dtx_wpse_sel#\n+ */\n+union cvmx_dtx_wpse_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wpse_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_wpse_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wpse_selx cvmx_dtx_wpse_selx_t;\n+\n+/**\n+ * cvmx_dtx_wrce_bcst_rsp\n+ */\n+union cvmx_dtx_wrce_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrce_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_wrce_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrce_bcst_rsp cvmx_dtx_wrce_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_wrce_ctl\n+ */\n+union cvmx_dtx_wrce_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrce_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_wrce_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrce_ctl cvmx_dtx_wrce_ctl_t;\n+\n+/**\n+ * cvmx_dtx_wrce_dat#\n+ */\n+union cvmx_dtx_wrce_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrce_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_wrce_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrce_datx cvmx_dtx_wrce_datx_t;\n+\n+/**\n+ * cvmx_dtx_wrce_ena#\n+ */\n+union cvmx_dtx_wrce_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrce_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_wrce_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrce_enax cvmx_dtx_wrce_enax_t;\n+\n+/**\n+ * cvmx_dtx_wrce_sel#\n+ */\n+union cvmx_dtx_wrce_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrce_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_wrce_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrce_selx cvmx_dtx_wrce_selx_t;\n+\n+/**\n+ * cvmx_dtx_wrde_bcst_rsp\n+ */\n+union cvmx_dtx_wrde_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrde_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_wrde_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrde_bcst_rsp cvmx_dtx_wrde_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_wrde_ctl\n+ */\n+union cvmx_dtx_wrde_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrde_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_wrde_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrde_ctl cvmx_dtx_wrde_ctl_t;\n+\n+/**\n+ * cvmx_dtx_wrde_dat#\n+ */\n+union cvmx_dtx_wrde_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrde_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_wrde_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrde_datx cvmx_dtx_wrde_datx_t;\n+\n+/**\n+ * cvmx_dtx_wrde_ena#\n+ */\n+union cvmx_dtx_wrde_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrde_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_wrde_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrde_enax cvmx_dtx_wrde_enax_t;\n+\n+/**\n+ * cvmx_dtx_wrde_sel#\n+ */\n+union cvmx_dtx_wrde_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrde_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_wrde_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrde_selx cvmx_dtx_wrde_selx_t;\n+\n+/**\n+ * cvmx_dtx_wrse_bcst_rsp\n+ */\n+union cvmx_dtx_wrse_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrse_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_wrse_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrse_bcst_rsp cvmx_dtx_wrse_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_wrse_ctl\n+ */\n+union cvmx_dtx_wrse_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrse_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_wrse_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrse_ctl cvmx_dtx_wrse_ctl_t;\n+\n+/**\n+ * cvmx_dtx_wrse_dat#\n+ */\n+union cvmx_dtx_wrse_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrse_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_wrse_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrse_datx cvmx_dtx_wrse_datx_t;\n+\n+/**\n+ * cvmx_dtx_wrse_ena#\n+ */\n+union cvmx_dtx_wrse_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrse_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_wrse_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrse_enax cvmx_dtx_wrse_enax_t;\n+\n+/**\n+ * cvmx_dtx_wrse_sel#\n+ */\n+union cvmx_dtx_wrse_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wrse_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_wrse_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wrse_selx cvmx_dtx_wrse_selx_t;\n+\n+/**\n+ * cvmx_dtx_wtxe_bcst_rsp\n+ */\n+union cvmx_dtx_wtxe_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wtxe_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_wtxe_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wtxe_bcst_rsp cvmx_dtx_wtxe_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_wtxe_ctl\n+ */\n+union cvmx_dtx_wtxe_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wtxe_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_wtxe_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wtxe_ctl cvmx_dtx_wtxe_ctl_t;\n+\n+/**\n+ * cvmx_dtx_wtxe_dat#\n+ */\n+union cvmx_dtx_wtxe_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wtxe_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_wtxe_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wtxe_datx cvmx_dtx_wtxe_datx_t;\n+\n+/**\n+ * cvmx_dtx_wtxe_ena#\n+ */\n+union cvmx_dtx_wtxe_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wtxe_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_wtxe_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wtxe_enax cvmx_dtx_wtxe_enax_t;\n+\n+/**\n+ * cvmx_dtx_wtxe_sel#\n+ */\n+union cvmx_dtx_wtxe_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_wtxe_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_wtxe_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_wtxe_selx cvmx_dtx_wtxe_selx_t;\n+\n+/**\n+ * cvmx_dtx_xcv_bcst_rsp\n+ */\n+union cvmx_dtx_xcv_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_xcv_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_xcv_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_xcv_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_xcv_bcst_rsp cvmx_dtx_xcv_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_xcv_ctl\n+ */\n+union cvmx_dtx_xcv_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_xcv_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_xcv_ctl_s cn73xx;\n+\tstruct cvmx_dtx_xcv_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_xcv_ctl cvmx_dtx_xcv_ctl_t;\n+\n+/**\n+ * cvmx_dtx_xcv_dat#\n+ */\n+union cvmx_dtx_xcv_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_xcv_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_xcv_datx_s cn73xx;\n+\tstruct cvmx_dtx_xcv_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_xcv_datx cvmx_dtx_xcv_datx_t;\n+\n+/**\n+ * cvmx_dtx_xcv_ena#\n+ */\n+union cvmx_dtx_xcv_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_xcv_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_xcv_enax_s cn73xx;\n+\tstruct cvmx_dtx_xcv_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_xcv_enax cvmx_dtx_xcv_enax_t;\n+\n+/**\n+ * cvmx_dtx_xcv_sel#\n+ */\n+union cvmx_dtx_xcv_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_xcv_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_xcv_selx_s cn73xx;\n+\tstruct cvmx_dtx_xcv_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_xcv_selx cvmx_dtx_xcv_selx_t;\n+\n+/**\n+ * cvmx_dtx_xsx_bcst_rsp\n+ */\n+union cvmx_dtx_xsx_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_xsx_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_xsx_bcst_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_xsx_bcst_rsp cvmx_dtx_xsx_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_xsx_ctl\n+ */\n+union cvmx_dtx_xsx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_xsx_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_xsx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_xsx_ctl cvmx_dtx_xsx_ctl_t;\n+\n+/**\n+ * cvmx_dtx_xsx_dat#\n+ */\n+union cvmx_dtx_xsx_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_xsx_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_xsx_datx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_xsx_datx cvmx_dtx_xsx_datx_t;\n+\n+/**\n+ * cvmx_dtx_xsx_ena#\n+ */\n+union cvmx_dtx_xsx_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_xsx_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_xsx_enax_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_xsx_enax cvmx_dtx_xsx_enax_t;\n+\n+/**\n+ * cvmx_dtx_xsx_sel#\n+ */\n+union cvmx_dtx_xsx_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_xsx_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_xsx_selx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dtx_xsx_selx cvmx_dtx_xsx_selx_t;\n+\n+/**\n+ * cvmx_dtx_zip_bcst_rsp\n+ */\n+union cvmx_dtx_zip_bcst_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dtx_zip_bcst_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_dtx_zip_bcst_rsp_s cn73xx;\n+\tstruct cvmx_dtx_zip_bcst_rsp_s cn78xx;\n+\tstruct cvmx_dtx_zip_bcst_rsp_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_zip_bcst_rsp cvmx_dtx_zip_bcst_rsp_t;\n+\n+/**\n+ * cvmx_dtx_zip_ctl\n+ */\n+union cvmx_dtx_zip_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dtx_zip_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 echoen : 1;\n+\t\tu64 swap : 1;\n+\t} s;\n+\tstruct cvmx_dtx_zip_ctl_s cn73xx;\n+\tstruct cvmx_dtx_zip_ctl_s cn78xx;\n+\tstruct cvmx_dtx_zip_ctl_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_zip_ctl cvmx_dtx_zip_ctl_t;\n+\n+/**\n+ * cvmx_dtx_zip_dat#\n+ */\n+union cvmx_dtx_zip_datx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_zip_datx_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 raw : 36;\n+\t} s;\n+\tstruct cvmx_dtx_zip_datx_s cn73xx;\n+\tstruct cvmx_dtx_zip_datx_s cn78xx;\n+\tstruct cvmx_dtx_zip_datx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_zip_datx cvmx_dtx_zip_datx_t;\n+\n+/**\n+ * cvmx_dtx_zip_ena#\n+ */\n+union cvmx_dtx_zip_enax {\n+\tu64 u64;\n+\tstruct cvmx_dtx_zip_enax_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 ena : 36;\n+\t} s;\n+\tstruct cvmx_dtx_zip_enax_s cn73xx;\n+\tstruct cvmx_dtx_zip_enax_s cn78xx;\n+\tstruct cvmx_dtx_zip_enax_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_zip_enax cvmx_dtx_zip_enax_t;\n+\n+/**\n+ * cvmx_dtx_zip_sel#\n+ */\n+union cvmx_dtx_zip_selx {\n+\tu64 u64;\n+\tstruct cvmx_dtx_zip_selx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 value : 24;\n+\t} s;\n+\tstruct cvmx_dtx_zip_selx_s cn73xx;\n+\tstruct cvmx_dtx_zip_selx_s cn78xx;\n+\tstruct cvmx_dtx_zip_selx_s cn78xxp1;\n+};\n+\n+typedef union cvmx_dtx_zip_selx cvmx_dtx_zip_selx_t;\n+\n+#endif\n", "prefixes": [ "v1", "09/50" ] }