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{
    "id": 1415044,
    "url": "http://patchwork.ozlabs.org/api/patches/1415044/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-29-sr@denx.de/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20201211160612.1498780-29-sr@denx.de>",
    "list_archive_url": null,
    "date": "2020-12-11T16:05:50",
    "name": "[v1,28/50] mips: octeon: Add cvmx-sli-defs.h header file",
    "commit_ref": "9505a7cee5dace32d60291ef584eaef46da6eba5",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "c68bfdcfd2961c261159b208a794be3aec029e18",
    "submitter": {
        "id": 13,
        "url": "http://patchwork.ozlabs.org/api/people/13/?format=api",
        "name": "Stefan Roese",
        "email": "sr@denx.de"
    },
    "delegate": {
        "id": 4307,
        "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api",
        "username": "danielschwierzeck",
        "first_name": "Daniel",
        "last_name": "Schwierzeck",
        "email": "daniel.schwierzeck@googlemail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-29-sr@denx.de/mbox/",
    "series": [
        {
            "id": 220054,
            "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054",
            "date": "2020-12-11T16:05:23",
            "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1415044/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1415044/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Stefan Roese <sr@denx.de>",
        "To": "u-boot@lists.denx.de",
        "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com",
        "Subject": "[PATCH v1 28/50] mips: octeon: Add cvmx-sli-defs.h header file",
        "Date": "Fri, 11 Dec 2020 17:05:50 +0100",
        "Message-Id": "<20201211160612.1498780-29-sr@denx.de>",
        "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>",
        "References": "<20201211160612.1498780-1-sr@denx.de>",
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    "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-sli-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-sli-defs.h  | 6548 +++++++++++++++++\n 1 file changed, 6548 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sli-defs.h",
    "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-sli-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-sli-defs.h\nnew file mode 100644\nindex 0000000000..221ed1bcde\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-sli-defs.h\n@@ -0,0 +1,6548 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon sli.\n+ */\n+\n+#ifndef __CVMX_SLI_DEFS_H__\n+#define __CVMX_SLI_DEFS_H__\n+\n+#define CVMX_SLI_BIST_STATUS CVMX_SLI_BIST_STATUS_FUNC()\n+static inline u64 CVMX_SLI_BIST_STATUS_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000580ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000580ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000028580ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000028580ull;\n+\t}\n+\treturn 0x0000000000028580ull;\n+}\n+\n+#define CVMX_SLI_CIU_INT_ENB (0x00011F0000027110ull)\n+#define CVMX_SLI_CIU_INT_SUM (0x00011F0000027100ull)\n+static inline u64 CVMX_SLI_CTL_PORTX(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000050ull + (offset) * 16;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000010050ull + (offset) * 16;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000050ull + (offset) * 16;\n+\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000000000006E0ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000286E0ull + (offset) * 16;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000286E0ull + (offset) * 16;\n+\t}\n+\treturn 0x00000000000286E0ull + (offset) * 16;\n+}\n+\n+#define CVMX_SLI_CTL_STATUS CVMX_SLI_CTL_STATUS_FUNC()\n+static inline u64 CVMX_SLI_CTL_STATUS_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000570ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000570ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000028570ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000028570ull;\n+\t}\n+\treturn 0x0000000000028570ull;\n+}\n+\n+#define CVMX_SLI_DATA_OUT_CNT CVMX_SLI_DATA_OUT_CNT_FUNC()\n+static inline u64 CVMX_SLI_DATA_OUT_CNT_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000005F0ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000000000005F0ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000285F0ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000285F0ull;\n+\t}\n+\treturn 0x00000000000285F0ull;\n+}\n+\n+#define CVMX_SLI_DBG_DATA   (0x0000000000000310ull)\n+#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)\n+static inline u64 CVMX_SLI_DMAX_CNT(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000400ull + (offset) * 16;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000400ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000028400ull + (offset) * 16;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000028400ull + (offset) * 16;\n+\t}\n+\treturn 0x0000000000028400ull + (offset) * 16;\n+}\n+\n+static inline u64 CVMX_SLI_DMAX_INT_LEVEL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000003E0ull + (offset) * 16;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000000000003E0ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000283E0ull + (offset) * 16;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000283E0ull + (offset) * 16;\n+\t}\n+\treturn 0x00000000000283E0ull + (offset) * 16;\n+}\n+\n+static inline u64 CVMX_SLI_DMAX_TIM(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000420ull + (offset) * 16;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000420ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000028420ull + (offset) * 16;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000028420ull + (offset) * 16;\n+\t}\n+\treturn 0x0000000000028420ull + (offset) * 16;\n+}\n+\n+#define CVMX_SLI_INT_ENB_CIU\t       (0x0000000000003CD0ull)\n+#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 3) * 16)\n+#define CVMX_SLI_INT_SUM\t       (0x0000000000000330ull)\n+#define CVMX_SLI_LAST_WIN_RDATA0       (0x0000000000000600ull)\n+#define CVMX_SLI_LAST_WIN_RDATA1       (0x0000000000000610ull)\n+#define CVMX_SLI_LAST_WIN_RDATA2       (0x00000000000006C0ull)\n+#define CVMX_SLI_LAST_WIN_RDATA3       (0x00000000000006D0ull)\n+#define CVMX_SLI_MACX_PFX_DMA_VF_INT(offset, block_id)                                             \\\n+\t(0x0000000000027280ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)\n+#define CVMX_SLI_MACX_PFX_DMA_VF_INT_ENB(offset, block_id)                                         \\\n+\t(0x0000000000027500ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)\n+#define CVMX_SLI_MACX_PFX_FLR_VF_INT(offset, block_id)                                             \\\n+\t(0x0000000000027400ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)\n+#define CVMX_SLI_MACX_PFX_INT_ENB(offset, block_id)                                                \\\n+\t(0x0000000000027080ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)\n+#define CVMX_SLI_MACX_PFX_INT_SUM(offset, block_id)                                                \\\n+\t(0x0000000000027000ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)\n+#define CVMX_SLI_MACX_PFX_MBOX_INT(offset, block_id)                                               \\\n+\t(0x0000000000027380ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)\n+#define CVMX_SLI_MACX_PFX_PKT_VF_INT(offset, block_id)                                             \\\n+\t(0x0000000000027300ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)\n+#define CVMX_SLI_MACX_PFX_PKT_VF_INT_ENB(offset, block_id)                                         \\\n+\t(0x0000000000027580ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)\n+#define CVMX_SLI_MACX_PFX_PP_VF_INT(offset, block_id)                                              \\\n+\t(0x0000000000027200ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)\n+#define CVMX_SLI_MACX_PFX_PP_VF_INT_ENB(offset, block_id)                                          \\\n+\t(0x0000000000027480ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)\n+#define CVMX_SLI_MAC_CREDIT_CNT CVMX_SLI_MAC_CREDIT_CNT_FUNC()\n+static inline u64 CVMX_SLI_MAC_CREDIT_CNT_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000003D70ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000003D70ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000023D70ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000023D70ull;\n+\t}\n+\treturn 0x0000000000023D70ull;\n+}\n+\n+#define CVMX_SLI_MAC_CREDIT_CNT2 CVMX_SLI_MAC_CREDIT_CNT2_FUNC()\n+static inline u64 CVMX_SLI_MAC_CREDIT_CNT2_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000013E10ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000003E10ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000023E10ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000023E10ull;\n+\t}\n+\treturn 0x0000000000023E10ull;\n+}\n+\n+#define CVMX_SLI_MAC_NUMBER CVMX_SLI_MAC_NUMBER_FUNC()\n+static inline u64 CVMX_SLI_MAC_NUMBER_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000003E00ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000003E00ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000020050ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000020050ull;\n+\t}\n+\treturn 0x0000000000020050ull;\n+}\n+\n+#define CVMX_SLI_MEM_ACCESS_CTL CVMX_SLI_MEM_ACCESS_CTL_FUNC()\n+static inline u64 CVMX_SLI_MEM_ACCESS_CTL_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000002F0ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000000000002F0ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000282F0ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000282F0ull;\n+\t}\n+\treturn 0x00000000000282F0ull;\n+}\n+\n+static inline u64 CVMX_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000000E0ull + (offset) * 16 - 16 * 12;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000000000000E0ull + (offset) * 16 - 16 * 12;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000280E0ull + (offset) * 16 - 16 * 12;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000280E0ull + (offset) * 16 - 16 * 12;\n+\t}\n+\treturn 0x00000000000280E0ull + (offset) * 16 - 16 * 12;\n+}\n+\n+#define CVMX_SLI_MEM_CTL CVMX_SLI_MEM_CTL_FUNC()\n+static inline u64 CVMX_SLI_MEM_CTL_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000000000005E0ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000285E0ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000285E0ull;\n+\t}\n+\treturn 0x00000000000285E0ull;\n+}\n+\n+#define CVMX_SLI_MEM_INT_SUM CVMX_SLI_MEM_INT_SUM_FUNC()\n+static inline u64 CVMX_SLI_MEM_INT_SUM_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000000000005D0ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000285D0ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000285D0ull;\n+\t}\n+\treturn 0x00000000000285D0ull;\n+}\n+\n+static inline u64 CVMX_SLI_MSIXX_TABLE_ADDR(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000006000ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000000000ull + (offset) * 16;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000000ull + (offset) * 16;\n+\t}\n+\treturn 0x0000000000000000ull + (offset) * 16;\n+}\n+\n+static inline u64 CVMX_SLI_MSIXX_TABLE_DATA(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000006008ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000000008ull + (offset) * 16;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000008ull + (offset) * 16;\n+\t}\n+\treturn 0x0000000000000008ull + (offset) * 16;\n+}\n+\n+#define CVMX_SLI_MSIX_MACX_PF_TABLE_ADDR(offset) (0x0000000000007C00ull + ((offset) & 3) * 16)\n+#define CVMX_SLI_MSIX_MACX_PF_TABLE_DATA(offset) (0x0000000000007C08ull + ((offset) & 3) * 16)\n+#define CVMX_SLI_MSIX_PBA0\t\t\t CVMX_SLI_MSIX_PBA0_FUNC()\n+static inline u64 CVMX_SLI_MSIX_PBA0_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000007000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000001000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000001000ull;\n+\t}\n+\treturn 0x0000000000001000ull;\n+}\n+\n+#define CVMX_SLI_MSIX_PBA1 CVMX_SLI_MSIX_PBA1_FUNC()\n+static inline u64 CVMX_SLI_MSIX_PBA1_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000007010ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000001008ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000001008ull;\n+\t}\n+\treturn 0x0000000000001008ull;\n+}\n+\n+#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)\n+#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)\n+#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)\n+#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)\n+#define CVMX_SLI_MSI_RCV0 CVMX_SLI_MSI_RCV0_FUNC()\n+static inline u64 CVMX_SLI_MSI_RCV0_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000003C10ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000003C10ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000023C10ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000023C10ull;\n+\t}\n+\treturn 0x0000000000023C10ull;\n+}\n+\n+#define CVMX_SLI_MSI_RCV1 CVMX_SLI_MSI_RCV1_FUNC()\n+static inline u64 CVMX_SLI_MSI_RCV1_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000003C20ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000003C20ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000023C20ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000023C20ull;\n+\t}\n+\treturn 0x0000000000023C20ull;\n+}\n+\n+#define CVMX_SLI_MSI_RCV2 CVMX_SLI_MSI_RCV2_FUNC()\n+static inline u64 CVMX_SLI_MSI_RCV2_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000003C30ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000003C30ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000023C30ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000023C30ull;\n+\t}\n+\treturn 0x0000000000023C30ull;\n+}\n+\n+#define CVMX_SLI_MSI_RCV3 CVMX_SLI_MSI_RCV3_FUNC()\n+static inline u64 CVMX_SLI_MSI_RCV3_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000003C40ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000003C40ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000023C40ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000023C40ull;\n+\t}\n+\treturn 0x0000000000023C40ull;\n+}\n+\n+#define CVMX_SLI_MSI_RD_MAP CVMX_SLI_MSI_RD_MAP_FUNC()\n+static inline u64 CVMX_SLI_MSI_RD_MAP_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000003CA0ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000003CA0ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000023CA0ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000023CA0ull;\n+\t}\n+\treturn 0x0000000000023CA0ull;\n+}\n+\n+#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)\n+#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)\n+#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)\n+#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)\n+#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)\n+#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)\n+#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)\n+#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)\n+#define CVMX_SLI_MSI_WR_MAP   CVMX_SLI_MSI_WR_MAP_FUNC()\n+static inline u64 CVMX_SLI_MSI_WR_MAP_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000003C90ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000003C90ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000023C90ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000023C90ull;\n+\t}\n+\treturn 0x0000000000023C90ull;\n+}\n+\n+#define CVMX_SLI_NQM_RSP_ERR_SND_DBG (0x00011F0000028800ull)\n+#define CVMX_SLI_PCIE_MSI_RCV\t     CVMX_SLI_PCIE_MSI_RCV_FUNC()\n+static inline u64 CVMX_SLI_PCIE_MSI_RCV_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000003CB0ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000003CB0ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000023CB0ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000023CB0ull;\n+\t}\n+\treturn 0x0000000000023CB0ull;\n+}\n+\n+#define CVMX_SLI_PCIE_MSI_RCV_B1 CVMX_SLI_PCIE_MSI_RCV_B1_FUNC()\n+static inline u64 CVMX_SLI_PCIE_MSI_RCV_B1_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000650ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000650ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000028650ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000028650ull;\n+\t}\n+\treturn 0x0000000000028650ull;\n+}\n+\n+#define CVMX_SLI_PCIE_MSI_RCV_B2 CVMX_SLI_PCIE_MSI_RCV_B2_FUNC()\n+static inline u64 CVMX_SLI_PCIE_MSI_RCV_B2_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000660ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000660ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000028660ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000028660ull;\n+\t}\n+\treturn 0x0000000000028660ull;\n+}\n+\n+#define CVMX_SLI_PCIE_MSI_RCV_B3 CVMX_SLI_PCIE_MSI_RCV_B3_FUNC()\n+static inline u64 CVMX_SLI_PCIE_MSI_RCV_B3_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000670ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000670ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000028670ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000028670ull;\n+\t}\n+\treturn 0x0000000000028670ull;\n+}\n+\n+static inline u64 CVMX_SLI_PKTX_CNTS(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000002400ull + (offset) * 16;\n+\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000002400ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000100B0ull + (offset) * 0x20000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000100B0ull + (offset) * 0x20000ull;\n+\t}\n+\treturn 0x00000000000100B0ull + (offset) * 0x20000ull;\n+}\n+\n+#define CVMX_SLI_PKTX_ERROR_INFO(offset) (0x00000000000100C0ull + ((offset) & 63) * 0x20000ull)\n+static inline u64 CVMX_SLI_PKTX_INPUT_CONTROL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000004000ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000010000ull + (offset) * 0x20000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000010000ull + (offset) * 0x20000ull;\n+\t}\n+\treturn 0x0000000000010000ull + (offset) * 0x20000ull;\n+}\n+\n+static inline u64 CVMX_SLI_PKTX_INSTR_BADDR(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000002800ull + (offset) * 16;\n+\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000002800ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000010010ull + (offset) * 0x20000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000010010ull + (offset) * 0x20000ull;\n+\t}\n+\treturn 0x0000000000010010ull + (offset) * 0x20000ull;\n+}\n+\n+static inline u64 CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000002C00ull + (offset) * 16;\n+\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000002C00ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000010020ull + (offset) * 0x20000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000010020ull + (offset) * 0x20000ull;\n+\t}\n+\treturn 0x0000000000010020ull + (offset) * 0x20000ull;\n+}\n+\n+static inline u64 CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000003000ull + (offset) * 16;\n+\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000003000ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000010030ull + (offset) * 0x20000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000010030ull + (offset) * 0x20000ull;\n+\t}\n+\treturn 0x0000000000010030ull + (offset) * 0x20000ull;\n+}\n+\n+#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)\n+static inline u64 CVMX_SLI_PKTX_INT_LEVELS(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000004400ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000100A0ull + (offset) * 0x20000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000100A0ull + (offset) * 0x20000ull;\n+\t}\n+\treturn 0x00000000000100A0ull + (offset) * 0x20000ull;\n+}\n+\n+#define CVMX_SLI_PKTX_IN_BP(offset)    (0x0000000000003800ull + ((offset) & 31) * 16)\n+#define CVMX_SLI_PKTX_MBOX_INT(offset) (0x0000000000010210ull + ((offset) & 63) * 0x20000ull)\n+static inline u64 CVMX_SLI_PKTX_OUTPUT_CONTROL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000004800ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000010050ull + (offset) * 0x20000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000010050ull + (offset) * 0x20000ull;\n+\t}\n+\treturn 0x0000000000010050ull + (offset) * 0x20000ull;\n+}\n+\n+static inline u64 CVMX_SLI_PKTX_OUT_SIZE(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000C00ull + (offset) * 16;\n+\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000C00ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000010060ull + (offset) * 0x20000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000010060ull + (offset) * 0x20000ull;\n+\t}\n+\treturn 0x0000000000010060ull + (offset) * 0x20000ull;\n+}\n+\n+#define CVMX_SLI_PKTX_PF_VF_MBOX_SIGX(offset, block_id)                                            \\\n+\t(0x0000000000010200ull + (((offset) & 1) + ((block_id) & 63) * 0x4000ull) * 8)\n+static inline u64 CVMX_SLI_PKTX_SLIST_BADDR(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000001400ull + (offset) * 16;\n+\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000001400ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000010070ull + (offset) * 0x20000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000010070ull + (offset) * 0x20000ull;\n+\t}\n+\treturn 0x0000000000010070ull + (offset) * 0x20000ull;\n+}\n+\n+static inline u64 CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000001800ull + (offset) * 16;\n+\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000001800ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000010080ull + (offset) * 0x20000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000010080ull + (offset) * 0x20000ull;\n+\t}\n+\treturn 0x0000000000010080ull + (offset) * 0x20000ull;\n+}\n+\n+static inline u64 CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000001C00ull + (offset) * 16;\n+\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000001C00ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000010090ull + (offset) * 0x20000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000010090ull + (offset) * 0x20000ull;\n+\t}\n+\treturn 0x0000000000010090ull + (offset) * 0x20000ull;\n+}\n+\n+#define CVMX_SLI_PKTX_VF_INT_SUM(offset) (0x00000000000100D0ull + ((offset) & 63) * 0x20000ull)\n+#define CVMX_SLI_PKTX_VF_SIG(offset)\t (0x0000000000004C00ull + ((offset) & 63) * 16)\n+#define CVMX_SLI_PKT_BIST_STATUS\t (0x0000000000029220ull)\n+#define CVMX_SLI_PKT_CNT_INT\t\t CVMX_SLI_PKT_CNT_INT_FUNC()\n+static inline u64 CVMX_SLI_PKT_CNT_INT_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000001130ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000001130ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000029130ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000029130ull;\n+\t}\n+\treturn 0x0000000000029130ull;\n+}\n+\n+#define CVMX_SLI_PKT_CNT_INT_ENB   (0x0000000000001150ull)\n+#define CVMX_SLI_PKT_CTL\t   (0x0000000000001220ull)\n+#define CVMX_SLI_PKT_DATA_OUT_ES   (0x00000000000010B0ull)\n+#define CVMX_SLI_PKT_DATA_OUT_NS   (0x00000000000010A0ull)\n+#define CVMX_SLI_PKT_DATA_OUT_ROR  (0x0000000000001090ull)\n+#define CVMX_SLI_PKT_DPADDR\t   (0x0000000000001080ull)\n+#define CVMX_SLI_PKT_GBL_CONTROL   (0x0000000000029210ull)\n+#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)\n+#define CVMX_SLI_PKT_INSTR_ENB\t   (0x0000000000001000ull)\n+#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)\n+#define CVMX_SLI_PKT_INSTR_SIZE\t   (0x0000000000001020ull)\n+#define CVMX_SLI_PKT_INT\t   CVMX_SLI_PKT_INT_FUNC()\n+static inline u64 CVMX_SLI_PKT_INT_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000001160ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000029160ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000029160ull;\n+\t}\n+\treturn 0x0000000000029160ull;\n+}\n+\n+#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)\n+#define CVMX_SLI_PKT_IN_BP\t(0x0000000000001210ull)\n+static inline u64 CVMX_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000002000ull + (offset) * 16;\n+\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000002000ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000010040ull + (offset) * 0x20000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000010040ull + (offset) * 0x20000ull;\n+\t}\n+\treturn 0x0000000000010040ull + (offset) * 0x20000ull;\n+}\n+\n+#define CVMX_SLI_PKT_IN_INSTR_COUNTS CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC()\n+static inline u64 CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000001200ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000001200ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000029200ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000029200ull;\n+\t}\n+\treturn 0x0000000000029200ull;\n+}\n+\n+#define CVMX_SLI_PKT_IN_INT CVMX_SLI_PKT_IN_INT_FUNC()\n+static inline u64 CVMX_SLI_PKT_IN_INT_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000001150ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000029150ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000029150ull;\n+\t}\n+\treturn 0x0000000000029150ull;\n+}\n+\n+#define CVMX_SLI_PKT_IN_JABBER\t  (0x0000000000029170ull)\n+#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)\n+#define CVMX_SLI_PKT_IPTR\t  (0x0000000000001070ull)\n+#define CVMX_SLI_PKT_MAC0_SIG0\t  (0x0000000000001300ull)\n+#define CVMX_SLI_PKT_MAC0_SIG1\t  (0x0000000000001310ull)\n+#define CVMX_SLI_PKT_MAC1_SIG0\t  (0x0000000000001320ull)\n+#define CVMX_SLI_PKT_MAC1_SIG1\t  (0x0000000000001330ull)\n+#define CVMX_SLI_PKT_MACX_PFX_RINFO(offset, block_id)                                              \\\n+\t(0x0000000000029030ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)\n+#define CVMX_SLI_PKT_MACX_RINFO(offset) (0x0000000000001030ull + ((offset) & 3) * 16)\n+#define CVMX_SLI_PKT_MEM_CTL\t\tCVMX_SLI_PKT_MEM_CTL_FUNC()\n+static inline u64 CVMX_SLI_PKT_MEM_CTL_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000001120ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000029120ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000029120ull;\n+\t}\n+\treturn 0x0000000000029120ull;\n+}\n+\n+#define CVMX_SLI_PKT_OUTPUT_WMARK CVMX_SLI_PKT_OUTPUT_WMARK_FUNC()\n+static inline u64 CVMX_SLI_PKT_OUTPUT_WMARK_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000001180ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000001180ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000029180ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000029180ull;\n+\t}\n+\treturn 0x0000000000029180ull;\n+}\n+\n+#define CVMX_SLI_PKT_OUT_BMODE\t    (0x00000000000010D0ull)\n+#define CVMX_SLI_PKT_OUT_BP_EN\t    (0x0000000000001240ull)\n+#define CVMX_SLI_PKT_OUT_BP_EN2_W1C (0x0000000000029290ull)\n+#define CVMX_SLI_PKT_OUT_BP_EN2_W1S (0x0000000000029270ull)\n+#define CVMX_SLI_PKT_OUT_BP_EN_W1C  (0x0000000000029280ull)\n+#define CVMX_SLI_PKT_OUT_BP_EN_W1S  (0x0000000000029260ull)\n+#define CVMX_SLI_PKT_OUT_ENB\t    (0x0000000000001010ull)\n+#define CVMX_SLI_PKT_PCIE_PORT\t    (0x00000000000010E0ull)\n+#define CVMX_SLI_PKT_PKIND_VALID    (0x0000000000029190ull)\n+#define CVMX_SLI_PKT_PORT_IN_RST    (0x00000000000011F0ull)\n+#define CVMX_SLI_PKT_RING_RST\t    CVMX_SLI_PKT_RING_RST_FUNC()\n+static inline u64 CVMX_SLI_PKT_RING_RST_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000000000011E0ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000291E0ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000291E0ull;\n+\t}\n+\treturn 0x00000000000291E0ull;\n+}\n+\n+#define CVMX_SLI_PKT_SLIST_ES  (0x0000000000001050ull)\n+#define CVMX_SLI_PKT_SLIST_NS  (0x0000000000001040ull)\n+#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)\n+#define CVMX_SLI_PKT_TIME_INT  CVMX_SLI_PKT_TIME_INT_FUNC()\n+static inline u64 CVMX_SLI_PKT_TIME_INT_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000001140ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000001140ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000029140ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000029140ull;\n+\t}\n+\treturn 0x0000000000029140ull;\n+}\n+\n+#define CVMX_SLI_PKT_TIME_INT_ENB    (0x0000000000001160ull)\n+#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)\n+#define CVMX_SLI_PP_PKT_CSR_CONTROL  (0x00011F00000282D0ull)\n+#define CVMX_SLI_S2C_END_MERGE\t     CVMX_SLI_S2C_END_MERGE_FUNC()\n+static inline u64 CVMX_SLI_S2C_END_MERGE_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011F0000015000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011F0000025000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011F0000025000ull;\n+\t}\n+\treturn 0x00011F0000025000ull;\n+}\n+\n+static inline u64 CVMX_SLI_S2M_PORTX_CTL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000003D80ull + (offset) * 16;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000003D80ull + (offset) * 16;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000013D80ull + (offset) * 16;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000003D80ull + (offset) * 16;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000023D80ull + (offset) * 16;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000023D80ull + (offset) * 16;\n+\t}\n+\treturn 0x0000000000023D80ull + (offset) * 16;\n+}\n+\n+#define CVMX_SLI_SCRATCH_1 CVMX_SLI_SCRATCH_1_FUNC()\n+static inline u64 CVMX_SLI_SCRATCH_1_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000003C0ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000000000003C0ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000283C0ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000283C0ull;\n+\t}\n+\treturn 0x00000000000283C0ull;\n+}\n+\n+#define CVMX_SLI_SCRATCH_2 CVMX_SLI_SCRATCH_2_FUNC()\n+static inline u64 CVMX_SLI_SCRATCH_2_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000003D0ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000000000003D0ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000283D0ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000283D0ull;\n+\t}\n+\treturn 0x00000000000283D0ull;\n+}\n+\n+#define CVMX_SLI_STATE1 CVMX_SLI_STATE1_FUNC()\n+static inline u64 CVMX_SLI_STATE1_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000620ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000620ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000028620ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000028620ull;\n+\t}\n+\treturn 0x0000000000028620ull;\n+}\n+\n+#define CVMX_SLI_STATE2 CVMX_SLI_STATE2_FUNC()\n+static inline u64 CVMX_SLI_STATE2_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000630ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000630ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000028630ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000028630ull;\n+\t}\n+\treturn 0x0000000000028630ull;\n+}\n+\n+#define CVMX_SLI_STATE3 CVMX_SLI_STATE3_FUNC()\n+static inline u64 CVMX_SLI_STATE3_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000640ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000640ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000028640ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000028640ull;\n+\t}\n+\treturn 0x0000000000028640ull;\n+}\n+\n+#define CVMX_SLI_TX_PIPE    (0x0000000000001230ull)\n+#define CVMX_SLI_WINDOW_CTL CVMX_SLI_WINDOW_CTL_FUNC()\n+static inline u64 CVMX_SLI_WINDOW_CTL_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000002E0ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000000000002E0ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000000000282E0ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000282E0ull;\n+\t}\n+\treturn 0x00000000000282E0ull;\n+}\n+\n+#define CVMX_SLI_WIN_RD_ADDR CVMX_SLI_WIN_RD_ADDR_FUNC()\n+static inline u64 CVMX_SLI_WIN_RD_ADDR_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000010ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000010ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000020010ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000020010ull;\n+\t}\n+\treturn 0x0000000000020010ull;\n+}\n+\n+#define CVMX_SLI_WIN_RD_DATA CVMX_SLI_WIN_RD_DATA_FUNC()\n+static inline u64 CVMX_SLI_WIN_RD_DATA_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000040ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000040ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000020040ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000020040ull;\n+\t}\n+\treturn 0x0000000000020040ull;\n+}\n+\n+#define CVMX_SLI_WIN_WR_ADDR CVMX_SLI_WIN_WR_ADDR_FUNC()\n+static inline u64 CVMX_SLI_WIN_WR_ADDR_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000020000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000020000ull;\n+\t}\n+\treturn 0x0000000000020000ull;\n+}\n+\n+#define CVMX_SLI_WIN_WR_DATA CVMX_SLI_WIN_WR_DATA_FUNC()\n+static inline u64 CVMX_SLI_WIN_WR_DATA_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000020ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000020ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000020020ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000020020ull;\n+\t}\n+\treturn 0x0000000000020020ull;\n+}\n+\n+#define CVMX_SLI_WIN_WR_MASK CVMX_SLI_WIN_WR_MASK_FUNC()\n+static inline u64 CVMX_SLI_WIN_WR_MASK_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000030ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000000000000030ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000000000020030ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000020030ull;\n+\t}\n+\treturn 0x0000000000020030ull;\n+}\n+\n+/**\n+ * cvmx_sli_bist_status\n+ *\n+ * This register contains results from BIST runs of MAC's memories: 0 = pass (or BIST in\n+ * progress/never run), 1 = fail.\n+ */\n+union cvmx_sli_bist_status {\n+\tu64 u64;\n+\tstruct cvmx_sli_bist_status_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 ncb_req : 1;\n+\t\tu64 n2p0_c : 1;\n+\t\tu64 n2p0_o : 1;\n+\t\tu64 n2p1_c : 1;\n+\t\tu64 n2p1_o : 1;\n+\t\tu64 cpl_p0 : 1;\n+\t\tu64 cpl_p1 : 1;\n+\t\tu64 reserved_19_24 : 6;\n+\t\tu64 p2n0_c0 : 1;\n+\t\tu64 p2n0_c1 : 1;\n+\t\tu64 p2n0_n : 1;\n+\t\tu64 p2n0_p0 : 1;\n+\t\tu64 p2n0_p1 : 1;\n+\t\tu64 p2n1_c0 : 1;\n+\t\tu64 p2n1_c1 : 1;\n+\t\tu64 p2n1_n : 1;\n+\t\tu64 p2n1_p0 : 1;\n+\t\tu64 p2n1_p1 : 1;\n+\t\tu64 reserved_6_8 : 3;\n+\t\tu64 dsi1_1 : 1;\n+\t\tu64 dsi1_0 : 1;\n+\t\tu64 dsi0_1 : 1;\n+\t\tu64 dsi0_0 : 1;\n+\t\tu64 msi : 1;\n+\t\tu64 ncb_cmd : 1;\n+\t} s;\n+\tstruct cvmx_sli_bist_status_cn61xx {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 n2p0_c : 1;\n+\t\tu64 n2p0_o : 1;\n+\t\tu64 reserved_27_28 : 2;\n+\t\tu64 cpl_p0 : 1;\n+\t\tu64 cpl_p1 : 1;\n+\t\tu64 reserved_19_24 : 6;\n+\t\tu64 p2n0_c0 : 1;\n+\t\tu64 p2n0_c1 : 1;\n+\t\tu64 p2n0_n : 1;\n+\t\tu64 p2n0_p0 : 1;\n+\t\tu64 p2n0_p1 : 1;\n+\t\tu64 p2n1_c0 : 1;\n+\t\tu64 p2n1_c1 : 1;\n+\t\tu64 p2n1_n : 1;\n+\t\tu64 p2n1_p0 : 1;\n+\t\tu64 p2n1_p1 : 1;\n+\t\tu64 reserved_6_8 : 3;\n+\t\tu64 dsi1_1 : 1;\n+\t\tu64 dsi1_0 : 1;\n+\t\tu64 dsi0_1 : 1;\n+\t\tu64 dsi0_0 : 1;\n+\t\tu64 msi : 1;\n+\t\tu64 ncb_cmd : 1;\n+\t} cn61xx;\n+\tstruct cvmx_sli_bist_status_cn63xx {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 n2p0_c : 1;\n+\t\tu64 n2p0_o : 1;\n+\t\tu64 n2p1_c : 1;\n+\t\tu64 n2p1_o : 1;\n+\t\tu64 cpl_p0 : 1;\n+\t\tu64 cpl_p1 : 1;\n+\t\tu64 reserved_19_24 : 6;\n+\t\tu64 p2n0_c0 : 1;\n+\t\tu64 p2n0_c1 : 1;\n+\t\tu64 p2n0_n : 1;\n+\t\tu64 p2n0_p0 : 1;\n+\t\tu64 p2n0_p1 : 1;\n+\t\tu64 p2n1_c0 : 1;\n+\t\tu64 p2n1_c1 : 1;\n+\t\tu64 p2n1_n : 1;\n+\t\tu64 p2n1_p0 : 1;\n+\t\tu64 p2n1_p1 : 1;\n+\t\tu64 reserved_6_8 : 3;\n+\t\tu64 dsi1_1 : 1;\n+\t\tu64 dsi1_0 : 1;\n+\t\tu64 dsi0_1 : 1;\n+\t\tu64 dsi0_0 : 1;\n+\t\tu64 msi : 1;\n+\t\tu64 ncb_cmd : 1;\n+\t} cn63xx;\n+\tstruct cvmx_sli_bist_status_cn63xx cn63xxp1;\n+\tstruct cvmx_sli_bist_status_cn61xx cn66xx;\n+\tstruct cvmx_sli_bist_status_s cn68xx;\n+\tstruct cvmx_sli_bist_status_s cn68xxp1;\n+\tstruct cvmx_sli_bist_status_cn70xx {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 n2p0_c : 1;\n+\t\tu64 n2p0_o : 1;\n+\t\tu64 reserved_27_28 : 2;\n+\t\tu64 cpl_p0 : 1;\n+\t\tu64 cpl_p1 : 1;\n+\t\tu64 reserved_19_24 : 6;\n+\t\tu64 p2n0_c0 : 1;\n+\t\tu64 reserved_17_17 : 1;\n+\t\tu64 p2n0_n : 1;\n+\t\tu64 p2n0_p0 : 1;\n+\t\tu64 reserved_14_14 : 1;\n+\t\tu64 p2n1_c0 : 1;\n+\t\tu64 reserved_12_12 : 1;\n+\t\tu64 p2n1_n : 1;\n+\t\tu64 p2n1_p0 : 1;\n+\t\tu64 reserved_6_9 : 4;\n+\t\tu64 dsi1_1 : 1;\n+\t\tu64 dsi1_0 : 1;\n+\t\tu64 dsi0_1 : 1;\n+\t\tu64 dsi0_0 : 1;\n+\t\tu64 msi : 1;\n+\t\tu64 ncb_cmd : 1;\n+\t} cn70xx;\n+\tstruct cvmx_sli_bist_status_cn70xx cn70xxp1;\n+\tstruct cvmx_sli_bist_status_s cn73xx;\n+\tstruct cvmx_sli_bist_status_s cn78xx;\n+\tstruct cvmx_sli_bist_status_s cn78xxp1;\n+\tstruct cvmx_sli_bist_status_cn61xx cnf71xx;\n+\tstruct cvmx_sli_bist_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_bist_status cvmx_sli_bist_status_t;\n+\n+/**\n+ * cvmx_sli_ciu_int_enb\n+ *\n+ * Interrupt enable register for a given SLI_CIU_INT_SUM register.\n+ *\n+ */\n+union cvmx_sli_ciu_int_enb {\n+\tu64 u64;\n+\tstruct cvmx_sli_ciu_int_enb_s {\n+\t\tu64 reserved_51_63 : 13;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 m3p0_pppf_err : 1;\n+\t\tu64 m3p0_pktpf_err : 1;\n+\t\tu64 m3p0_dmapf_err : 1;\n+\t\tu64 m2p0_pppf_err : 1;\n+\t\tu64 m2p0_ppvf_err : 1;\n+\t\tu64 m2p0_pktpf_err : 1;\n+\t\tu64 m2p0_pktvf_err : 1;\n+\t\tu64 m2p0_dmapf_err : 1;\n+\t\tu64 m2p0_dmavf_err : 1;\n+\t\tu64 m1p0_pppf_err : 1;\n+\t\tu64 m1p0_pktpf_err : 1;\n+\t\tu64 m1p0_dmapf_err : 1;\n+\t\tu64 m0p1_pppf_err : 1;\n+\t\tu64 m0p1_ppvf_err : 1;\n+\t\tu64 m0p1_pktpf_err : 1;\n+\t\tu64 m0p1_pktvf_err : 1;\n+\t\tu64 m0p1_dmapf_err : 1;\n+\t\tu64 m0p1_dmavf_err : 1;\n+\t\tu64 m0p0_pppf_err : 1;\n+\t\tu64 m0p0_ppvf_err : 1;\n+\t\tu64 m0p0_pktpf_err : 1;\n+\t\tu64 m0p0_pktvf_err : 1;\n+\t\tu64 m0p0_dmapf_err : 1;\n+\t\tu64 m0p0_dmavf_err : 1;\n+\t\tu64 m2v0_flr : 1;\n+\t\tu64 m2p0_flr : 1;\n+\t\tu64 reserved_5_8 : 4;\n+\t\tu64 m0v1_flr : 1;\n+\t\tu64 m0p1_flr : 1;\n+\t\tu64 m0v0_flr : 1;\n+\t\tu64 m0p0_flr : 1;\n+\t\tu64 rml_to : 1;\n+\t} s;\n+\tstruct cvmx_sli_ciu_int_enb_s cn73xx;\n+\tstruct cvmx_sli_ciu_int_enb_s cn78xx;\n+\tstruct cvmx_sli_ciu_int_enb_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_ciu_int_enb cvmx_sli_ciu_int_enb_t;\n+\n+/**\n+ * cvmx_sli_ciu_int_sum\n+ *\n+ * The fields in this register are set when an interrupt condition occurs; write 1 to clear.\n+ * A bit set in this register will send and interrupt to CIU\n+ */\n+union cvmx_sli_ciu_int_sum {\n+\tu64 u64;\n+\tstruct cvmx_sli_ciu_int_sum_s {\n+\t\tu64 reserved_51_63 : 13;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 m3p0_pppf_err : 1;\n+\t\tu64 m3p0_pktpf_err : 1;\n+\t\tu64 m3p0_dmapf_err : 1;\n+\t\tu64 m2p0_pppf_err : 1;\n+\t\tu64 m2p0_ppvf_err : 1;\n+\t\tu64 m2p0_pktpf_err : 1;\n+\t\tu64 m2p0_pktvf_err : 1;\n+\t\tu64 m2p0_dmapf_err : 1;\n+\t\tu64 m2p0_dmavf_err : 1;\n+\t\tu64 m1p0_pppf_err : 1;\n+\t\tu64 m1p0_pktpf_err : 1;\n+\t\tu64 m1p0_dmapf_err : 1;\n+\t\tu64 m0p1_pppf_err : 1;\n+\t\tu64 m0p1_ppvf_err : 1;\n+\t\tu64 m0p1_pktpf_err : 1;\n+\t\tu64 m0p1_pktvf_err : 1;\n+\t\tu64 m0p1_dmapf_err : 1;\n+\t\tu64 m0p1_dmavf_err : 1;\n+\t\tu64 m0p0_pppf_err : 1;\n+\t\tu64 m0p0_ppvf_err : 1;\n+\t\tu64 m0p0_pktpf_err : 1;\n+\t\tu64 m0p0_pktvf_err : 1;\n+\t\tu64 m0p0_dmapf_err : 1;\n+\t\tu64 m0p0_dmavf_err : 1;\n+\t\tu64 m2v0_flr : 1;\n+\t\tu64 m2p0_flr : 1;\n+\t\tu64 reserved_5_8 : 4;\n+\t\tu64 m0v1_flr : 1;\n+\t\tu64 m0p1_flr : 1;\n+\t\tu64 m0v0_flr : 1;\n+\t\tu64 m0p0_flr : 1;\n+\t\tu64 rml_to : 1;\n+\t} s;\n+\tstruct cvmx_sli_ciu_int_sum_s cn73xx;\n+\tstruct cvmx_sli_ciu_int_sum_s cn78xx;\n+\tstruct cvmx_sli_ciu_int_sum_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_ciu_int_sum cvmx_sli_ciu_int_sum_t;\n+\n+/**\n+ * cvmx_sli_ctl_port#\n+ *\n+ * These registers contains control information for access to ports. Indexed by SLI_PORT_E.\n+ * Note: SLI_CTL_PORT0 controls PF0.\n+ */\n+union cvmx_sli_ctl_portx {\n+\tu64 u64;\n+\tstruct cvmx_sli_ctl_portx_s {\n+\t\tu64 reserved_22_63 : 42;\n+\t\tu64 intd : 1;\n+\t\tu64 intc : 1;\n+\t\tu64 intb : 1;\n+\t\tu64 inta : 1;\n+\t\tu64 dis_port : 1;\n+\t\tu64 waitl_com : 1;\n+\t\tu64 intd_map : 2;\n+\t\tu64 intc_map : 2;\n+\t\tu64 intb_map : 2;\n+\t\tu64 inta_map : 2;\n+\t\tu64 ctlp_ro : 1;\n+\t\tu64 reserved_6_6 : 1;\n+\t\tu64 ptlp_ro : 1;\n+\t\tu64 reserved_1_4 : 4;\n+\t\tu64 wait_com : 1;\n+\t} s;\n+\tstruct cvmx_sli_ctl_portx_s cn61xx;\n+\tstruct cvmx_sli_ctl_portx_s cn63xx;\n+\tstruct cvmx_sli_ctl_portx_s cn63xxp1;\n+\tstruct cvmx_sli_ctl_portx_s cn66xx;\n+\tstruct cvmx_sli_ctl_portx_s cn68xx;\n+\tstruct cvmx_sli_ctl_portx_s cn68xxp1;\n+\tstruct cvmx_sli_ctl_portx_cn70xx {\n+\t\tu64 reserved_22_63 : 42;\n+\t\tu64 intd : 1;\n+\t\tu64 intc : 1;\n+\t\tu64 intb : 1;\n+\t\tu64 inta : 1;\n+\t\tu64 dis_port : 1;\n+\t\tu64 waitl_com : 1;\n+\t\tu64 intd_map : 2;\n+\t\tu64 intc_map : 2;\n+\t\tu64 intb_map : 2;\n+\t\tu64 inta_map : 2;\n+\t\tu64 ctlp_ro : 1;\n+\t\tu64 reserved_6_6 : 1;\n+\t\tu64 ptlp_ro : 1;\n+\t\tu64 reserved_4_1 : 4;\n+\t\tu64 wait_com : 1;\n+\t} cn70xx;\n+\tstruct cvmx_sli_ctl_portx_cn70xx cn70xxp1;\n+\tstruct cvmx_sli_ctl_portx_cn73xx {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 dis_port : 1;\n+\t\tu64 waitl_com : 1;\n+\t\tu64 reserved_8_15 : 8;\n+\t\tu64 ctlp_ro : 1;\n+\t\tu64 reserved_6_6 : 1;\n+\t\tu64 ptlp_ro : 1;\n+\t\tu64 reserved_1_4 : 4;\n+\t\tu64 wait_com : 1;\n+\t} cn73xx;\n+\tstruct cvmx_sli_ctl_portx_cn73xx cn78xx;\n+\tstruct cvmx_sli_ctl_portx_cn73xx cn78xxp1;\n+\tstruct cvmx_sli_ctl_portx_s cnf71xx;\n+\tstruct cvmx_sli_ctl_portx_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sli_ctl_portx cvmx_sli_ctl_portx_t;\n+\n+/**\n+ * cvmx_sli_ctl_status\n+ *\n+ * This register contains control and status for SLI. Write operations to this register are not\n+ * ordered with write/read operations to the MAC memory space. To ensure that a write has\n+ * completed, software must read the register before making an access (i.e. MAC memory space)\n+ * that requires the value of this register to be updated.\n+ */\n+union cvmx_sli_ctl_status {\n+\tu64 u64;\n+\tstruct cvmx_sli_ctl_status_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 m2s1_ncbi : 4;\n+\t\tu64 m2s0_ncbi : 4;\n+\t\tu64 oci_id : 4;\n+\t\tu64 p1_ntags : 6;\n+\t\tu64 p0_ntags : 6;\n+\t\tu64 chip_rev : 8;\n+\t} s;\n+\tstruct cvmx_sli_ctl_status_cn61xx {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 p0_ntags : 6;\n+\t\tu64 chip_rev : 8;\n+\t} cn61xx;\n+\tstruct cvmx_sli_ctl_status_cn63xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 p1_ntags : 6;\n+\t\tu64 p0_ntags : 6;\n+\t\tu64 chip_rev : 8;\n+\t} cn63xx;\n+\tstruct cvmx_sli_ctl_status_cn63xx cn63xxp1;\n+\tstruct cvmx_sli_ctl_status_cn61xx cn66xx;\n+\tstruct cvmx_sli_ctl_status_cn63xx cn68xx;\n+\tstruct cvmx_sli_ctl_status_cn63xx cn68xxp1;\n+\tstruct cvmx_sli_ctl_status_cn63xx cn70xx;\n+\tstruct cvmx_sli_ctl_status_cn63xx cn70xxp1;\n+\tstruct cvmx_sli_ctl_status_cn73xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 m2s1_ncbi : 4;\n+\t\tu64 m2s0_ncbi : 4;\n+\t\tu64 reserved_20_23 : 4;\n+\t\tu64 p1_ntags : 6;\n+\t\tu64 p0_ntags : 6;\n+\t\tu64 chip_rev : 8;\n+\t} cn73xx;\n+\tstruct cvmx_sli_ctl_status_s cn78xx;\n+\tstruct cvmx_sli_ctl_status_s cn78xxp1;\n+\tstruct cvmx_sli_ctl_status_cn61xx cnf71xx;\n+\tstruct cvmx_sli_ctl_status_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sli_ctl_status cvmx_sli_ctl_status_t;\n+\n+/**\n+ * cvmx_sli_data_out_cnt\n+ *\n+ * This register contains the EXEC data out FIFO count and the data unload counter.\n+ *\n+ */\n+union cvmx_sli_data_out_cnt {\n+\tu64 u64;\n+\tstruct cvmx_sli_data_out_cnt_s {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 p1_ucnt : 16;\n+\t\tu64 p1_fcnt : 6;\n+\t\tu64 p0_ucnt : 16;\n+\t\tu64 p0_fcnt : 6;\n+\t} s;\n+\tstruct cvmx_sli_data_out_cnt_s cn61xx;\n+\tstruct cvmx_sli_data_out_cnt_s cn63xx;\n+\tstruct cvmx_sli_data_out_cnt_s cn63xxp1;\n+\tstruct cvmx_sli_data_out_cnt_s cn66xx;\n+\tstruct cvmx_sli_data_out_cnt_s cn68xx;\n+\tstruct cvmx_sli_data_out_cnt_s cn68xxp1;\n+\tstruct cvmx_sli_data_out_cnt_s cn70xx;\n+\tstruct cvmx_sli_data_out_cnt_s cn70xxp1;\n+\tstruct cvmx_sli_data_out_cnt_s cn73xx;\n+\tstruct cvmx_sli_data_out_cnt_s cn78xx;\n+\tstruct cvmx_sli_data_out_cnt_s cn78xxp1;\n+\tstruct cvmx_sli_data_out_cnt_s cnf71xx;\n+\tstruct cvmx_sli_data_out_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_data_out_cnt cvmx_sli_data_out_cnt_t;\n+\n+/**\n+ * cvmx_sli_dbg_data\n+ *\n+ * SLI_DBG_DATA = SLI Debug Data Register\n+ *\n+ * Value returned on the debug-data lines from the RSLs\n+ */\n+union cvmx_sli_dbg_data {\n+\tu64 u64;\n+\tstruct cvmx_sli_dbg_data_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 dsel_ext : 1;\n+\t\tu64 data : 17;\n+\t} s;\n+\tstruct cvmx_sli_dbg_data_s cn61xx;\n+\tstruct cvmx_sli_dbg_data_s cn63xx;\n+\tstruct cvmx_sli_dbg_data_s cn63xxp1;\n+\tstruct cvmx_sli_dbg_data_s cn66xx;\n+\tstruct cvmx_sli_dbg_data_s cn68xx;\n+\tstruct cvmx_sli_dbg_data_s cn68xxp1;\n+\tstruct cvmx_sli_dbg_data_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_dbg_data cvmx_sli_dbg_data_t;\n+\n+/**\n+ * cvmx_sli_dbg_select\n+ *\n+ * SLI_DBG_SELECT = Debug Select Register\n+ *\n+ * Contains the debug select value last written to the RSLs.\n+ */\n+union cvmx_sli_dbg_select {\n+\tu64 u64;\n+\tstruct cvmx_sli_dbg_select_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 adbg_sel : 1;\n+\t\tu64 dbg_sel : 32;\n+\t} s;\n+\tstruct cvmx_sli_dbg_select_s cn61xx;\n+\tstruct cvmx_sli_dbg_select_s cn63xx;\n+\tstruct cvmx_sli_dbg_select_s cn63xxp1;\n+\tstruct cvmx_sli_dbg_select_s cn66xx;\n+\tstruct cvmx_sli_dbg_select_s cn68xx;\n+\tstruct cvmx_sli_dbg_select_s cn68xxp1;\n+\tstruct cvmx_sli_dbg_select_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_dbg_select cvmx_sli_dbg_select_t;\n+\n+/**\n+ * cvmx_sli_dma#_cnt\n+ *\n+ * These registers contain the DMA count values.\n+ *\n+ */\n+union cvmx_sli_dmax_cnt {\n+\tu64 u64;\n+\tstruct cvmx_sli_dmax_cnt_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_sli_dmax_cnt_s cn61xx;\n+\tstruct cvmx_sli_dmax_cnt_s cn63xx;\n+\tstruct cvmx_sli_dmax_cnt_s cn63xxp1;\n+\tstruct cvmx_sli_dmax_cnt_s cn66xx;\n+\tstruct cvmx_sli_dmax_cnt_s cn68xx;\n+\tstruct cvmx_sli_dmax_cnt_s cn68xxp1;\n+\tstruct cvmx_sli_dmax_cnt_s cn70xx;\n+\tstruct cvmx_sli_dmax_cnt_s cn70xxp1;\n+\tstruct cvmx_sli_dmax_cnt_s cn73xx;\n+\tstruct cvmx_sli_dmax_cnt_s cn78xx;\n+\tstruct cvmx_sli_dmax_cnt_s cn78xxp1;\n+\tstruct cvmx_sli_dmax_cnt_s cnf71xx;\n+\tstruct cvmx_sli_dmax_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_dmax_cnt cvmx_sli_dmax_cnt_t;\n+\n+/**\n+ * cvmx_sli_dma#_int_level\n+ *\n+ * These registers contain the thresholds for DMA count and timer interrupts.\n+ *\n+ */\n+union cvmx_sli_dmax_int_level {\n+\tu64 u64;\n+\tstruct cvmx_sli_dmax_int_level_s {\n+\t\tu64 time : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_sli_dmax_int_level_s cn61xx;\n+\tstruct cvmx_sli_dmax_int_level_s cn63xx;\n+\tstruct cvmx_sli_dmax_int_level_s cn63xxp1;\n+\tstruct cvmx_sli_dmax_int_level_s cn66xx;\n+\tstruct cvmx_sli_dmax_int_level_s cn68xx;\n+\tstruct cvmx_sli_dmax_int_level_s cn68xxp1;\n+\tstruct cvmx_sli_dmax_int_level_s cn70xx;\n+\tstruct cvmx_sli_dmax_int_level_s cn70xxp1;\n+\tstruct cvmx_sli_dmax_int_level_s cn73xx;\n+\tstruct cvmx_sli_dmax_int_level_s cn78xx;\n+\tstruct cvmx_sli_dmax_int_level_s cn78xxp1;\n+\tstruct cvmx_sli_dmax_int_level_s cnf71xx;\n+\tstruct cvmx_sli_dmax_int_level_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_dmax_int_level cvmx_sli_dmax_int_level_t;\n+\n+/**\n+ * cvmx_sli_dma#_tim\n+ *\n+ * These registers contain the DMA timer values.\n+ *\n+ */\n+union cvmx_sli_dmax_tim {\n+\tu64 u64;\n+\tstruct cvmx_sli_dmax_tim_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 tim : 32;\n+\t} s;\n+\tstruct cvmx_sli_dmax_tim_s cn61xx;\n+\tstruct cvmx_sli_dmax_tim_s cn63xx;\n+\tstruct cvmx_sli_dmax_tim_s cn63xxp1;\n+\tstruct cvmx_sli_dmax_tim_s cn66xx;\n+\tstruct cvmx_sli_dmax_tim_s cn68xx;\n+\tstruct cvmx_sli_dmax_tim_s cn68xxp1;\n+\tstruct cvmx_sli_dmax_tim_s cn70xx;\n+\tstruct cvmx_sli_dmax_tim_s cn70xxp1;\n+\tstruct cvmx_sli_dmax_tim_s cn73xx;\n+\tstruct cvmx_sli_dmax_tim_s cn78xx;\n+\tstruct cvmx_sli_dmax_tim_s cn78xxp1;\n+\tstruct cvmx_sli_dmax_tim_s cnf71xx;\n+\tstruct cvmx_sli_dmax_tim_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_dmax_tim cvmx_sli_dmax_tim_t;\n+\n+/**\n+ * cvmx_sli_int_enb_ciu\n+ *\n+ * Used to enable the various interrupting conditions of SLI\n+ *\n+ */\n+union cvmx_sli_int_enb_ciu {\n+\tu64 u64;\n+\tstruct cvmx_sli_int_enb_ciu_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 pipe_err : 1;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 sprt3_err : 1;\n+\t\tu64 sprt2_err : 1;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 pin_bp : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_29_31 : 3;\n+\t\tu64 mio_int2 : 1;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 reserved_18_19 : 2;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} s;\n+\tstruct cvmx_sli_int_enb_ciu_cn61xx {\n+\t\tu64 reserved_61_63 : 3;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 sprt3_err : 1;\n+\t\tu64 sprt2_err : 1;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 pin_bp : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_28_31 : 4;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 reserved_18_19 : 2;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} cn61xx;\n+\tstruct cvmx_sli_int_enb_ciu_cn63xx {\n+\t\tu64 reserved_61_63 : 3;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 reserved_58_59 : 2;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 pin_bp : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_18_31 : 14;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} cn63xx;\n+\tstruct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;\n+\tstruct cvmx_sli_int_enb_ciu_cn61xx cn66xx;\n+\tstruct cvmx_sli_int_enb_ciu_cn68xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 pipe_err : 1;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 reserved_58_59 : 2;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 reserved_51_51 : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_18_31 : 14;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} cn68xx;\n+\tstruct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;\n+\tstruct cvmx_sli_int_enb_ciu_cn70xx {\n+\t\tu64 reserved_63_61 : 3;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 sprt3_err : 1;\n+\t\tu64 sprt2_err : 1;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 pin_bp : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_47_38 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_31_29 : 3;\n+\t\tu64 mio_int2 : 1;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 reserved_19_18 : 2;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_7_6 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} cn70xx;\n+\tstruct cvmx_sli_int_enb_ciu_cn70xx cn70xxp1;\n+\tstruct cvmx_sli_int_enb_ciu_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_sli_int_enb_ciu cvmx_sli_int_enb_ciu_t;\n+\n+/**\n+ * cvmx_sli_int_enb_port#\n+ *\n+ * When a field in this register is set, and a corresponding interrupt condition asserts in\n+ * SLI_INT_SUM, an interrupt is generated. Interrupts can be sent to PCIe0 or PCIe1.\n+ */\n+union cvmx_sli_int_enb_portx {\n+\tu64 u64;\n+\tstruct cvmx_sli_int_enb_portx_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 pipe_err : 1;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 sprt3_err : 1;\n+\t\tu64 sprt2_err : 1;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 pin_bp : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_30_31 : 2;\n+\t\tu64 mac2_int : 1;\n+\t\tu64 reserved_28_28 : 1;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 mac1_int : 1;\n+\t\tu64 mac0_int : 1;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 mio_int3 : 1;\n+\t\tu64 reserved_6_6 : 1;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} s;\n+\tstruct cvmx_sli_int_enb_portx_cn61xx {\n+\t\tu64 reserved_61_63 : 3;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 sprt3_err : 1;\n+\t\tu64 sprt2_err : 1;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 pin_bp : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_28_31 : 4;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 mac1_int : 1;\n+\t\tu64 mac0_int : 1;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} cn61xx;\n+\tstruct cvmx_sli_int_enb_portx_cn63xx {\n+\t\tu64 reserved_61_63 : 3;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 reserved_58_59 : 2;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 pin_bp : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_20_31 : 12;\n+\t\tu64 mac1_int : 1;\n+\t\tu64 mac0_int : 1;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} cn63xx;\n+\tstruct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;\n+\tstruct cvmx_sli_int_enb_portx_cn61xx cn66xx;\n+\tstruct cvmx_sli_int_enb_portx_cn68xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 pipe_err : 1;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 reserved_58_59 : 2;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 reserved_51_51 : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_20_31 : 12;\n+\t\tu64 mac1_int : 1;\n+\t\tu64 mac0_int : 1;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} cn68xx;\n+\tstruct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;\n+\tstruct cvmx_sli_int_enb_portx_cn70xx {\n+\t\tu64 reserved_63_61 : 3;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 sprt3_err : 1;\n+\t\tu64 sprt2_err : 1;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 pin_bp : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_47_38 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_31_30 : 2;\n+\t\tu64 mac2_int : 1;\n+\t\tu64 mio_int2 : 1;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 mac1_int : 1;\n+\t\tu64 mac0_int : 1;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_7_6 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} cn70xx;\n+\tstruct cvmx_sli_int_enb_portx_cn70xx cn70xxp1;\n+\tstruct cvmx_sli_int_enb_portx_cn78xxp1 {\n+\t\tu64 reserved_60_63 : 4;\n+\t\tu64 sprt3_err : 1;\n+\t\tu64 sprt2_err : 1;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 reserved_50_51 : 2;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_29_31 : 3;\n+\t\tu64 vf_err : 1;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 reserved_18_19 : 2;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 mio_int3 : 1;\n+\t\tu64 mio_int2 : 1;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 reserved_1_3 : 3;\n+\t\tu64 rml_to : 1;\n+\t} cn78xxp1;\n+\tstruct cvmx_sli_int_enb_portx_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_sli_int_enb_portx cvmx_sli_int_enb_portx_t;\n+\n+/**\n+ * cvmx_sli_int_sum\n+ *\n+ * The fields in this register are set when an interrupt condition occurs; write 1 to clear. All\n+ * fields of the register are valid when a PF reads the register. Not available to VFs, and\n+ * writes by the\n+ * VF do not modify the register.\n+ */\n+union cvmx_sli_int_sum {\n+\tu64 u64;\n+\tstruct cvmx_sli_int_sum_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 pipe_err : 1;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 sprt3_err : 1;\n+\t\tu64 sprt2_err : 1;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 pin_bp : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_30_31 : 2;\n+\t\tu64 mac2_int : 1;\n+\t\tu64 reserved_28_28 : 1;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 mac1_int : 1;\n+\t\tu64 mac0_int : 1;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 mio_int3 : 1;\n+\t\tu64 reserved_6_6 : 1;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} s;\n+\tstruct cvmx_sli_int_sum_cn61xx {\n+\t\tu64 reserved_61_63 : 3;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 sprt3_err : 1;\n+\t\tu64 sprt2_err : 1;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 pin_bp : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_28_31 : 4;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 mac1_int : 1;\n+\t\tu64 mac0_int : 1;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} cn61xx;\n+\tstruct cvmx_sli_int_sum_cn63xx {\n+\t\tu64 reserved_61_63 : 3;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 reserved_58_59 : 2;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 pin_bp : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_20_31 : 12;\n+\t\tu64 mac1_int : 1;\n+\t\tu64 mac0_int : 1;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} cn63xx;\n+\tstruct cvmx_sli_int_sum_cn63xx cn63xxp1;\n+\tstruct cvmx_sli_int_sum_cn61xx cn66xx;\n+\tstruct cvmx_sli_int_sum_cn68xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 pipe_err : 1;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 reserved_58_59 : 2;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 reserved_51_51 : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_20_31 : 12;\n+\t\tu64 mac1_int : 1;\n+\t\tu64 mac0_int : 1;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} cn68xx;\n+\tstruct cvmx_sli_int_sum_cn68xx cn68xxp1;\n+\tstruct cvmx_sli_int_sum_cn70xx {\n+\t\tu64 reserved_61_63 : 3;\n+\t\tu64 ill_pad : 1;\n+\t\tu64 sprt3_err : 1;\n+\t\tu64 sprt2_err : 1;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 pin_bp : 1;\n+\t\tu64 pout_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_30_31 : 2;\n+\t\tu64 mac2_int : 1;\n+\t\tu64 mio_int2 : 1;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 mac1_int : 1;\n+\t\tu64 mac0_int : 1;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 iob2big : 1;\n+\t\tu64 bar0_to : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 rml_to : 1;\n+\t} cn70xx;\n+\tstruct cvmx_sli_int_sum_cn70xx cn70xxp1;\n+\tstruct cvmx_sli_int_sum_cn78xxp1 {\n+\t\tu64 reserved_60_63 : 4;\n+\t\tu64 sprt3_err : 1;\n+\t\tu64 sprt2_err : 1;\n+\t\tu64 sprt1_err : 1;\n+\t\tu64 sprt0_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 reserved_50_51 : 2;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_29_31 : 3;\n+\t\tu64 vf_err : 1;\n+\t\tu64 m3_un_wi : 1;\n+\t\tu64 m3_un_b0 : 1;\n+\t\tu64 m3_up_wi : 1;\n+\t\tu64 m3_up_b0 : 1;\n+\t\tu64 m2_un_wi : 1;\n+\t\tu64 m2_un_b0 : 1;\n+\t\tu64 m2_up_wi : 1;\n+\t\tu64 m2_up_b0 : 1;\n+\t\tu64 reserved_18_19 : 2;\n+\t\tu64 mio_int1 : 1;\n+\t\tu64 mio_int0 : 1;\n+\t\tu64 m1_un_wi : 1;\n+\t\tu64 m1_un_b0 : 1;\n+\t\tu64 m1_up_wi : 1;\n+\t\tu64 m1_up_b0 : 1;\n+\t\tu64 m0_un_wi : 1;\n+\t\tu64 m0_un_b0 : 1;\n+\t\tu64 m0_up_wi : 1;\n+\t\tu64 m0_up_b0 : 1;\n+\t\tu64 mio_int3 : 1;\n+\t\tu64 mio_int2 : 1;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 reserved_1_3 : 3;\n+\t\tu64 rml_to : 1;\n+\t} cn78xxp1;\n+\tstruct cvmx_sli_int_sum_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_sli_int_sum cvmx_sli_int_sum_t;\n+\n+/**\n+ * cvmx_sli_last_win_rdata0\n+ *\n+ * The data from the last initiated window read by MAC 0.\n+ *\n+ */\n+union cvmx_sli_last_win_rdata0 {\n+\tu64 u64;\n+\tstruct cvmx_sli_last_win_rdata0_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_sli_last_win_rdata0_s cn61xx;\n+\tstruct cvmx_sli_last_win_rdata0_s cn63xx;\n+\tstruct cvmx_sli_last_win_rdata0_s cn63xxp1;\n+\tstruct cvmx_sli_last_win_rdata0_s cn66xx;\n+\tstruct cvmx_sli_last_win_rdata0_s cn68xx;\n+\tstruct cvmx_sli_last_win_rdata0_s cn68xxp1;\n+\tstruct cvmx_sli_last_win_rdata0_s cn70xx;\n+\tstruct cvmx_sli_last_win_rdata0_s cn70xxp1;\n+\tstruct cvmx_sli_last_win_rdata0_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_last_win_rdata0 cvmx_sli_last_win_rdata0_t;\n+\n+/**\n+ * cvmx_sli_last_win_rdata1\n+ *\n+ * The data from the last initiated window read by MAC 1.\n+ *\n+ */\n+union cvmx_sli_last_win_rdata1 {\n+\tu64 u64;\n+\tstruct cvmx_sli_last_win_rdata1_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_sli_last_win_rdata1_s cn61xx;\n+\tstruct cvmx_sli_last_win_rdata1_s cn63xx;\n+\tstruct cvmx_sli_last_win_rdata1_s cn63xxp1;\n+\tstruct cvmx_sli_last_win_rdata1_s cn66xx;\n+\tstruct cvmx_sli_last_win_rdata1_s cn68xx;\n+\tstruct cvmx_sli_last_win_rdata1_s cn68xxp1;\n+\tstruct cvmx_sli_last_win_rdata1_s cn70xx;\n+\tstruct cvmx_sli_last_win_rdata1_s cn70xxp1;\n+\tstruct cvmx_sli_last_win_rdata1_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_last_win_rdata1 cvmx_sli_last_win_rdata1_t;\n+\n+/**\n+ * cvmx_sli_last_win_rdata2\n+ *\n+ * The data from the last initiated window read by MAC 2.\n+ *\n+ */\n+union cvmx_sli_last_win_rdata2 {\n+\tu64 u64;\n+\tstruct cvmx_sli_last_win_rdata2_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_sli_last_win_rdata2_s cn61xx;\n+\tstruct cvmx_sli_last_win_rdata2_s cn66xx;\n+\tstruct cvmx_sli_last_win_rdata2_s cn70xx;\n+\tstruct cvmx_sli_last_win_rdata2_s cn70xxp1;\n+\tstruct cvmx_sli_last_win_rdata2_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_last_win_rdata2 cvmx_sli_last_win_rdata2_t;\n+\n+/**\n+ * cvmx_sli_last_win_rdata3\n+ *\n+ * The data from the last initiated window read by MAC 3.\n+ *\n+ */\n+union cvmx_sli_last_win_rdata3 {\n+\tu64 u64;\n+\tstruct cvmx_sli_last_win_rdata3_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_sli_last_win_rdata3_s cn61xx;\n+\tstruct cvmx_sli_last_win_rdata3_s cn66xx;\n+\tstruct cvmx_sli_last_win_rdata3_s cn70xx;\n+\tstruct cvmx_sli_last_win_rdata3_s cn70xxp1;\n+\tstruct cvmx_sli_last_win_rdata3_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_last_win_rdata3 cvmx_sli_last_win_rdata3_t;\n+\n+/**\n+ * cvmx_sli_mac#_pf#_dma_vf_int\n+ *\n+ * When an error response is received for a VF DMA transaction read, the appropriate VF indexed\n+ * bit is set.  The appropriate PF should read the appropriate register.\n+ * Indexed by (MAC index) SLI_PORT_E.\n+ * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.\n+ */\n+union cvmx_sli_macx_pfx_dma_vf_int {\n+\tu64 u64;\n+\tstruct cvmx_sli_macx_pfx_dma_vf_int_s {\n+\t\tu64 vf_int : 64;\n+\t} s;\n+\tstruct cvmx_sli_macx_pfx_dma_vf_int_s cn73xx;\n+\tstruct cvmx_sli_macx_pfx_dma_vf_int_s cn78xx;\n+\tstruct cvmx_sli_macx_pfx_dma_vf_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_macx_pfx_dma_vf_int cvmx_sli_macx_pfx_dma_vf_int_t;\n+\n+/**\n+ * cvmx_sli_mac#_pf#_dma_vf_int_enb\n+ *\n+ * Indexed by (MAC index) SLI_PORT_E.\n+ * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.\n+ */\n+union cvmx_sli_macx_pfx_dma_vf_int_enb {\n+\tu64 u64;\n+\tstruct cvmx_sli_macx_pfx_dma_vf_int_enb_s {\n+\t\tu64 vf_int_enb : 64;\n+\t} s;\n+\tstruct cvmx_sli_macx_pfx_dma_vf_int_enb_s cn73xx;\n+\tstruct cvmx_sli_macx_pfx_dma_vf_int_enb_s cn78xx;\n+\tstruct cvmx_sli_macx_pfx_dma_vf_int_enb_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_macx_pfx_dma_vf_int_enb cvmx_sli_macx_pfx_dma_vf_int_enb_t;\n+\n+/**\n+ * cvmx_sli_mac#_pf#_flr_vf_int\n+ *\n+ * Indexed by (MAC index) SLI_PORT_E.\n+ * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.\n+ */\n+union cvmx_sli_macx_pfx_flr_vf_int {\n+\tu64 u64;\n+\tstruct cvmx_sli_macx_pfx_flr_vf_int_s {\n+\t\tu64 vf_int : 64;\n+\t} s;\n+\tstruct cvmx_sli_macx_pfx_flr_vf_int_s cn73xx;\n+\tstruct cvmx_sli_macx_pfx_flr_vf_int_s cn78xx;\n+\tstruct cvmx_sli_macx_pfx_flr_vf_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_macx_pfx_flr_vf_int cvmx_sli_macx_pfx_flr_vf_int_t;\n+\n+/**\n+ * cvmx_sli_mac#_pf#_int_enb\n+ *\n+ * Interrupt enable register for a given PF SLI_MAC()_PF()_INT_SUM register.\n+ * Indexed by (MAC index) SLI_PORT_E.\n+ */\n+union cvmx_sli_macx_pfx_int_enb {\n+\tu64 u64;\n+\tstruct cvmx_sli_macx_pfx_int_enb_s {\n+\t\tu64 pppf_err : 1;\n+\t\tu64 ppvf_err : 1;\n+\t\tu64 pktpf_err : 1;\n+\t\tu64 pktvf_err : 1;\n+\t\tu64 dmapf_err : 1;\n+\t\tu64 dmavf_err : 1;\n+\t\tu64 vf_mbox : 1;\n+\t\tu64 reserved_38_56 : 19;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_12_31 : 20;\n+\t\tu64 un_wi : 1;\n+\t\tu64 un_b0 : 1;\n+\t\tu64 up_wi : 1;\n+\t\tu64 up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 mio_int : 1;\n+\t\tu64 rml_to : 1;\n+\t} s;\n+\tstruct cvmx_sli_macx_pfx_int_enb_s cn73xx;\n+\tstruct cvmx_sli_macx_pfx_int_enb_s cn78xx;\n+\tstruct cvmx_sli_macx_pfx_int_enb_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_macx_pfx_int_enb cvmx_sli_macx_pfx_int_enb_t;\n+\n+/**\n+ * cvmx_sli_mac#_pf#_int_sum\n+ *\n+ * Interrupt summary register for a given PF. Indexed (MAC index) by SLI_PORT_E.\n+ * The fields in this register are set when an interrupt condition occurs; write 1 to clear.\n+ */\n+union cvmx_sli_macx_pfx_int_sum {\n+\tu64 u64;\n+\tstruct cvmx_sli_macx_pfx_int_sum_s {\n+\t\tu64 pppf_err : 1;\n+\t\tu64 ppvf_err : 1;\n+\t\tu64 pktpf_err : 1;\n+\t\tu64 pktvf_err : 1;\n+\t\tu64 dmapf_err : 1;\n+\t\tu64 dmavf_err : 1;\n+\t\tu64 vf_mbox : 1;\n+\t\tu64 reserved_38_56 : 19;\n+\t\tu64 dtime : 2;\n+\t\tu64 dcnt : 2;\n+\t\tu64 dmafi : 2;\n+\t\tu64 reserved_12_31 : 20;\n+\t\tu64 un_wi : 1;\n+\t\tu64 un_b0 : 1;\n+\t\tu64 up_wi : 1;\n+\t\tu64 up_b0 : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ptime : 1;\n+\t\tu64 pcnt : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 mio_int : 1;\n+\t\tu64 rml_to : 1;\n+\t} s;\n+\tstruct cvmx_sli_macx_pfx_int_sum_s cn73xx;\n+\tstruct cvmx_sli_macx_pfx_int_sum_s cn78xx;\n+\tstruct cvmx_sli_macx_pfx_int_sum_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_macx_pfx_int_sum cvmx_sli_macx_pfx_int_sum_t;\n+\n+/**\n+ * cvmx_sli_mac#_pf#_mbox_int\n+ *\n+ * When a VF to PF MBOX write occurs the appropriate bit is set.\n+ * Indexed by (MAC index) SLI_PORT_E.\n+ * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.\n+ */\n+union cvmx_sli_macx_pfx_mbox_int {\n+\tu64 u64;\n+\tstruct cvmx_sli_macx_pfx_mbox_int_s {\n+\t\tu64 vf_int : 64;\n+\t} s;\n+\tstruct cvmx_sli_macx_pfx_mbox_int_s cn73xx;\n+\tstruct cvmx_sli_macx_pfx_mbox_int_s cn78xx;\n+\tstruct cvmx_sli_macx_pfx_mbox_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_macx_pfx_mbox_int cvmx_sli_macx_pfx_mbox_int_t;\n+\n+/**\n+ * cvmx_sli_mac#_pf#_pkt_vf_int\n+ *\n+ * When an error response is received for a VF PP transaction read, a doorbell\n+ * overflow for a ring associated with a VF occurs or an illegal memory access from a VF occurs,\n+ * the appropriate VF indexed bit is set.  The appropriate PF should read the appropriate\n+ * register.\n+ * Indexed by (MAC index) SLI_PORT_E.\n+ * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.\n+ */\n+union cvmx_sli_macx_pfx_pkt_vf_int {\n+\tu64 u64;\n+\tstruct cvmx_sli_macx_pfx_pkt_vf_int_s {\n+\t\tu64 vf_int : 64;\n+\t} s;\n+\tstruct cvmx_sli_macx_pfx_pkt_vf_int_s cn73xx;\n+\tstruct cvmx_sli_macx_pfx_pkt_vf_int_s cn78xx;\n+\tstruct cvmx_sli_macx_pfx_pkt_vf_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_macx_pfx_pkt_vf_int cvmx_sli_macx_pfx_pkt_vf_int_t;\n+\n+/**\n+ * cvmx_sli_mac#_pf#_pkt_vf_int_enb\n+ *\n+ * Indexed by (MAC index) SLI_PORT_E.\n+ * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.\n+ */\n+union cvmx_sli_macx_pfx_pkt_vf_int_enb {\n+\tu64 u64;\n+\tstruct cvmx_sli_macx_pfx_pkt_vf_int_enb_s {\n+\t\tu64 vf_int_enb : 64;\n+\t} s;\n+\tstruct cvmx_sli_macx_pfx_pkt_vf_int_enb_s cn73xx;\n+\tstruct cvmx_sli_macx_pfx_pkt_vf_int_enb_s cn78xx;\n+\tstruct cvmx_sli_macx_pfx_pkt_vf_int_enb_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_macx_pfx_pkt_vf_int_enb cvmx_sli_macx_pfx_pkt_vf_int_enb_t;\n+\n+/**\n+ * cvmx_sli_mac#_pf#_pp_vf_int\n+ *\n+ * When an error response is received for a VF PP transaction read, the appropriate VF indexed\n+ * bit is set.  The appropriate PF should read the appropriate register.\n+ * Indexed by (MAC index) SLI_PORT_E.\n+ * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.\n+ */\n+union cvmx_sli_macx_pfx_pp_vf_int {\n+\tu64 u64;\n+\tstruct cvmx_sli_macx_pfx_pp_vf_int_s {\n+\t\tu64 vf_int : 64;\n+\t} s;\n+\tstruct cvmx_sli_macx_pfx_pp_vf_int_s cn73xx;\n+\tstruct cvmx_sli_macx_pfx_pp_vf_int_s cn78xx;\n+\tstruct cvmx_sli_macx_pfx_pp_vf_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_macx_pfx_pp_vf_int cvmx_sli_macx_pfx_pp_vf_int_t;\n+\n+/**\n+ * cvmx_sli_mac#_pf#_pp_vf_int_enb\n+ *\n+ * Indexed by (MAC index) SLI_PORT_E.\n+ * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.\n+ */\n+union cvmx_sli_macx_pfx_pp_vf_int_enb {\n+\tu64 u64;\n+\tstruct cvmx_sli_macx_pfx_pp_vf_int_enb_s {\n+\t\tu64 vf_int_enb : 64;\n+\t} s;\n+\tstruct cvmx_sli_macx_pfx_pp_vf_int_enb_s cn73xx;\n+\tstruct cvmx_sli_macx_pfx_pp_vf_int_enb_s cn78xx;\n+\tstruct cvmx_sli_macx_pfx_pp_vf_int_enb_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_macx_pfx_pp_vf_int_enb cvmx_sli_macx_pfx_pp_vf_int_enb_t;\n+\n+/**\n+ * cvmx_sli_mac_credit_cnt\n+ *\n+ * This register contains the number of credits for the MAC port FIFOs used by the SLI. This\n+ * value needs to be set before S2M traffic flow starts. A write operation to this register\n+ * causes the credit counts in the SLI for the MAC ports to be reset to the value in this\n+ * register if the corresponding disable bit in this register is set to 0.\n+ */\n+union cvmx_sli_mac_credit_cnt {\n+\tu64 u64;\n+\tstruct cvmx_sli_mac_credit_cnt_s {\n+\t\tu64 reserved_54_63 : 10;\n+\t\tu64 p1_c_d : 1;\n+\t\tu64 p1_n_d : 1;\n+\t\tu64 p1_p_d : 1;\n+\t\tu64 p0_c_d : 1;\n+\t\tu64 p0_n_d : 1;\n+\t\tu64 p0_p_d : 1;\n+\t\tu64 p1_ccnt : 8;\n+\t\tu64 p1_ncnt : 8;\n+\t\tu64 p1_pcnt : 8;\n+\t\tu64 p0_ccnt : 8;\n+\t\tu64 p0_ncnt : 8;\n+\t\tu64 p0_pcnt : 8;\n+\t} s;\n+\tstruct cvmx_sli_mac_credit_cnt_s cn61xx;\n+\tstruct cvmx_sli_mac_credit_cnt_s cn63xx;\n+\tstruct cvmx_sli_mac_credit_cnt_cn63xxp1 {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 p1_ccnt : 8;\n+\t\tu64 p1_ncnt : 8;\n+\t\tu64 p1_pcnt : 8;\n+\t\tu64 p0_ccnt : 8;\n+\t\tu64 p0_ncnt : 8;\n+\t\tu64 p0_pcnt : 8;\n+\t} cn63xxp1;\n+\tstruct cvmx_sli_mac_credit_cnt_s cn66xx;\n+\tstruct cvmx_sli_mac_credit_cnt_s cn68xx;\n+\tstruct cvmx_sli_mac_credit_cnt_s cn68xxp1;\n+\tstruct cvmx_sli_mac_credit_cnt_s cn70xx;\n+\tstruct cvmx_sli_mac_credit_cnt_s cn70xxp1;\n+\tstruct cvmx_sli_mac_credit_cnt_s cn73xx;\n+\tstruct cvmx_sli_mac_credit_cnt_s cn78xx;\n+\tstruct cvmx_sli_mac_credit_cnt_s cn78xxp1;\n+\tstruct cvmx_sli_mac_credit_cnt_s cnf71xx;\n+\tstruct cvmx_sli_mac_credit_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_mac_credit_cnt cvmx_sli_mac_credit_cnt_t;\n+\n+/**\n+ * cvmx_sli_mac_credit_cnt2\n+ *\n+ * This register contains the number of credits for the MAC port FIFOs (for MACs 2 and 3) used by\n+ * the SLI. This value must be set before S2M traffic flow starts. A write to this register\n+ * causes the credit counts in the SLI for the MAC ports to be reset to the value in this\n+ * register.\n+ */\n+union cvmx_sli_mac_credit_cnt2 {\n+\tu64 u64;\n+\tstruct cvmx_sli_mac_credit_cnt2_s {\n+\t\tu64 reserved_54_63 : 10;\n+\t\tu64 p3_c_d : 1;\n+\t\tu64 p3_n_d : 1;\n+\t\tu64 p3_p_d : 1;\n+\t\tu64 p2_c_d : 1;\n+\t\tu64 p2_n_d : 1;\n+\t\tu64 p2_p_d : 1;\n+\t\tu64 p3_ccnt : 8;\n+\t\tu64 p3_ncnt : 8;\n+\t\tu64 p3_pcnt : 8;\n+\t\tu64 p2_ccnt : 8;\n+\t\tu64 p2_ncnt : 8;\n+\t\tu64 p2_pcnt : 8;\n+\t} s;\n+\tstruct cvmx_sli_mac_credit_cnt2_s cn61xx;\n+\tstruct cvmx_sli_mac_credit_cnt2_s cn66xx;\n+\tstruct cvmx_sli_mac_credit_cnt2_s cn70xx;\n+\tstruct cvmx_sli_mac_credit_cnt2_s cn70xxp1;\n+\tstruct cvmx_sli_mac_credit_cnt2_s cn73xx;\n+\tstruct cvmx_sli_mac_credit_cnt2_s cn78xx;\n+\tstruct cvmx_sli_mac_credit_cnt2_s cn78xxp1;\n+\tstruct cvmx_sli_mac_credit_cnt2_s cnf71xx;\n+\tstruct cvmx_sli_mac_credit_cnt2_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_mac_credit_cnt2 cvmx_sli_mac_credit_cnt2_t;\n+\n+/**\n+ * cvmx_sli_mac_number\n+ *\n+ * When read from a MAC port, this register returns the MAC's port number, otherwise returns zero.\n+ *\n+ */\n+union cvmx_sli_mac_number {\n+\tu64 u64;\n+\tstruct cvmx_sli_mac_number_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 a_mode : 1;\n+\t\tu64 num : 8;\n+\t} s;\n+\tstruct cvmx_sli_mac_number_s cn61xx;\n+\tstruct cvmx_sli_mac_number_cn63xx {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 num : 8;\n+\t} cn63xx;\n+\tstruct cvmx_sli_mac_number_s cn66xx;\n+\tstruct cvmx_sli_mac_number_cn63xx cn68xx;\n+\tstruct cvmx_sli_mac_number_cn63xx cn68xxp1;\n+\tstruct cvmx_sli_mac_number_s cn70xx;\n+\tstruct cvmx_sli_mac_number_s cn70xxp1;\n+\tstruct cvmx_sli_mac_number_s cn73xx;\n+\tstruct cvmx_sli_mac_number_s cn78xx;\n+\tstruct cvmx_sli_mac_number_s cn78xxp1;\n+\tstruct cvmx_sli_mac_number_s cnf71xx;\n+\tstruct cvmx_sli_mac_number_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_mac_number cvmx_sli_mac_number_t;\n+\n+/**\n+ * cvmx_sli_mem_access_ctl\n+ *\n+ * This register contains control signals for access to the MAC address space.\n+ *\n+ */\n+union cvmx_sli_mem_access_ctl {\n+\tu64 u64;\n+\tstruct cvmx_sli_mem_access_ctl_s {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 max_word : 4;\n+\t\tu64 timer : 10;\n+\t} s;\n+\tstruct cvmx_sli_mem_access_ctl_s cn61xx;\n+\tstruct cvmx_sli_mem_access_ctl_s cn63xx;\n+\tstruct cvmx_sli_mem_access_ctl_s cn63xxp1;\n+\tstruct cvmx_sli_mem_access_ctl_s cn66xx;\n+\tstruct cvmx_sli_mem_access_ctl_s cn68xx;\n+\tstruct cvmx_sli_mem_access_ctl_s cn68xxp1;\n+\tstruct cvmx_sli_mem_access_ctl_s cn70xx;\n+\tstruct cvmx_sli_mem_access_ctl_s cn70xxp1;\n+\tstruct cvmx_sli_mem_access_ctl_s cn73xx;\n+\tstruct cvmx_sli_mem_access_ctl_s cn78xx;\n+\tstruct cvmx_sli_mem_access_ctl_s cn78xxp1;\n+\tstruct cvmx_sli_mem_access_ctl_s cnf71xx;\n+\tstruct cvmx_sli_mem_access_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_mem_access_ctl cvmx_sli_mem_access_ctl_t;\n+\n+/**\n+ * cvmx_sli_mem_access_subid#\n+ *\n+ * These registers contains address index and control bits for access to memory from cores.\n+ *\n+ */\n+union cvmx_sli_mem_access_subidx {\n+\tu64 u64;\n+\tstruct cvmx_sli_mem_access_subidx_s {\n+\t\tu64 reserved_60_63 : 4;\n+\t\tu64 pvf : 16;\n+\t\tu64 reserved_43_43 : 1;\n+\t\tu64 zero : 1;\n+\t\tu64 port : 3;\n+\t\tu64 nmerge : 1;\n+\t\tu64 esr : 2;\n+\t\tu64 esw : 2;\n+\t\tu64 wtype : 2;\n+\t\tu64 rtype : 2;\n+\t\tu64 reserved_0_29 : 30;\n+\t} s;\n+\tstruct cvmx_sli_mem_access_subidx_cn61xx {\n+\t\tu64 reserved_43_63 : 21;\n+\t\tu64 zero : 1;\n+\t\tu64 port : 3;\n+\t\tu64 nmerge : 1;\n+\t\tu64 esr : 2;\n+\t\tu64 esw : 2;\n+\t\tu64 wtype : 2;\n+\t\tu64 rtype : 2;\n+\t\tu64 ba : 30;\n+\t} cn61xx;\n+\tstruct cvmx_sli_mem_access_subidx_cn61xx cn63xx;\n+\tstruct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;\n+\tstruct cvmx_sli_mem_access_subidx_cn61xx cn66xx;\n+\tstruct cvmx_sli_mem_access_subidx_cn68xx {\n+\t\tu64 reserved_43_63 : 21;\n+\t\tu64 zero : 1;\n+\t\tu64 port : 3;\n+\t\tu64 nmerge : 1;\n+\t\tu64 esr : 2;\n+\t\tu64 esw : 2;\n+\t\tu64 wtype : 2;\n+\t\tu64 rtype : 2;\n+\t\tu64 ba : 28;\n+\t\tu64 reserved_0_1 : 2;\n+\t} cn68xx;\n+\tstruct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;\n+\tstruct cvmx_sli_mem_access_subidx_cn61xx cn70xx;\n+\tstruct cvmx_sli_mem_access_subidx_cn61xx cn70xxp1;\n+\tstruct cvmx_sli_mem_access_subidx_cn73xx {\n+\t\tu64 reserved_60_63 : 4;\n+\t\tu64 pvf : 16;\n+\t\tu64 reserved_43_43 : 1;\n+\t\tu64 zero : 1;\n+\t\tu64 port : 3;\n+\t\tu64 nmerge : 1;\n+\t\tu64 esr : 2;\n+\t\tu64 esw : 2;\n+\t\tu64 wtype : 2;\n+\t\tu64 rtype : 2;\n+\t\tu64 ba : 30;\n+\t} cn73xx;\n+\tstruct cvmx_sli_mem_access_subidx_cn73xx cn78xx;\n+\tstruct cvmx_sli_mem_access_subidx_cn61xx cn78xxp1;\n+\tstruct cvmx_sli_mem_access_subidx_cn61xx cnf71xx;\n+\tstruct cvmx_sli_mem_access_subidx_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sli_mem_access_subidx cvmx_sli_mem_access_subidx_t;\n+\n+/**\n+ * cvmx_sli_mem_ctl\n+ *\n+ * This register controls the ECC of the SLI memories.\n+ *\n+ */\n+union cvmx_sli_mem_ctl {\n+\tu64 u64;\n+\tstruct cvmx_sli_mem_ctl_s {\n+\t\tu64 reserved_27_63 : 37;\n+\t\tu64 tlpn1_fs : 2;\n+\t\tu64 tlpn1_ecc : 1;\n+\t\tu64 tlpp1_fs : 2;\n+\t\tu64 tlpp1_ecc : 1;\n+\t\tu64 tlpc1_fs : 2;\n+\t\tu64 tlpc1_ecc : 1;\n+\t\tu64 tlpn0_fs : 2;\n+\t\tu64 tlpn0_ecc : 1;\n+\t\tu64 tlpp0_fs : 2;\n+\t\tu64 tlpp0_ecc : 1;\n+\t\tu64 tlpc0_fs : 2;\n+\t\tu64 tlpc0_ecc : 1;\n+\t\tu64 nppr_fs : 2;\n+\t\tu64 nppr_ecc : 1;\n+\t\tu64 cpl1_fs : 2;\n+\t\tu64 cpl1_ecc : 1;\n+\t\tu64 cpl0_fs : 2;\n+\t\tu64 cpl0_ecc : 1;\n+\t} s;\n+\tstruct cvmx_sli_mem_ctl_s cn73xx;\n+\tstruct cvmx_sli_mem_ctl_s cn78xx;\n+\tstruct cvmx_sli_mem_ctl_s cn78xxp1;\n+\tstruct cvmx_sli_mem_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_mem_ctl cvmx_sli_mem_ctl_t;\n+\n+/**\n+ * cvmx_sli_mem_int_sum\n+ *\n+ * Set when an interrupt condition occurs; write one to clear.\n+ *\n+ */\n+union cvmx_sli_mem_int_sum {\n+\tu64 u64;\n+\tstruct cvmx_sli_mem_int_sum_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 tlpn1_dbe : 1;\n+\t\tu64 tlpn1_sbe : 1;\n+\t\tu64 tlpp1_dbe : 1;\n+\t\tu64 tlpp1_sbe : 1;\n+\t\tu64 tlpc1_dbe : 1;\n+\t\tu64 tlpc1_sbe : 1;\n+\t\tu64 tlpn0_dbe : 1;\n+\t\tu64 tlpn0_sbe : 1;\n+\t\tu64 tlpp0_dbe : 1;\n+\t\tu64 tlpp0_sbe : 1;\n+\t\tu64 tlpc0_dbe : 1;\n+\t\tu64 tlpc0_sbe : 1;\n+\t\tu64 nppr_dbe : 1;\n+\t\tu64 nppr_sbe : 1;\n+\t\tu64 cpl1_dbe : 1;\n+\t\tu64 cpl1_sbe : 1;\n+\t\tu64 cpl0_dbe : 1;\n+\t\tu64 cpl0_sbe : 1;\n+\t} s;\n+\tstruct cvmx_sli_mem_int_sum_s cn73xx;\n+\tstruct cvmx_sli_mem_int_sum_s cn78xx;\n+\tstruct cvmx_sli_mem_int_sum_s cn78xxp1;\n+\tstruct cvmx_sli_mem_int_sum_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_mem_int_sum cvmx_sli_mem_int_sum_t;\n+\n+/**\n+ * cvmx_sli_msi_enb0\n+ *\n+ * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV0.\n+ *\n+ */\n+union cvmx_sli_msi_enb0 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_enb0_s {\n+\t\tu64 enb : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_enb0_s cn61xx;\n+\tstruct cvmx_sli_msi_enb0_s cn63xx;\n+\tstruct cvmx_sli_msi_enb0_s cn63xxp1;\n+\tstruct cvmx_sli_msi_enb0_s cn66xx;\n+\tstruct cvmx_sli_msi_enb0_s cn68xx;\n+\tstruct cvmx_sli_msi_enb0_s cn68xxp1;\n+\tstruct cvmx_sli_msi_enb0_s cn70xx;\n+\tstruct cvmx_sli_msi_enb0_s cn70xxp1;\n+\tstruct cvmx_sli_msi_enb0_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_msi_enb0 cvmx_sli_msi_enb0_t;\n+\n+/**\n+ * cvmx_sli_msi_enb1\n+ *\n+ * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV1.\n+ *\n+ */\n+union cvmx_sli_msi_enb1 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_enb1_s {\n+\t\tu64 enb : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_enb1_s cn61xx;\n+\tstruct cvmx_sli_msi_enb1_s cn63xx;\n+\tstruct cvmx_sli_msi_enb1_s cn63xxp1;\n+\tstruct cvmx_sli_msi_enb1_s cn66xx;\n+\tstruct cvmx_sli_msi_enb1_s cn68xx;\n+\tstruct cvmx_sli_msi_enb1_s cn68xxp1;\n+\tstruct cvmx_sli_msi_enb1_s cn70xx;\n+\tstruct cvmx_sli_msi_enb1_s cn70xxp1;\n+\tstruct cvmx_sli_msi_enb1_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_msi_enb1 cvmx_sli_msi_enb1_t;\n+\n+/**\n+ * cvmx_sli_msi_enb2\n+ *\n+ * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV2.\n+ *\n+ */\n+union cvmx_sli_msi_enb2 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_enb2_s {\n+\t\tu64 enb : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_enb2_s cn61xx;\n+\tstruct cvmx_sli_msi_enb2_s cn63xx;\n+\tstruct cvmx_sli_msi_enb2_s cn63xxp1;\n+\tstruct cvmx_sli_msi_enb2_s cn66xx;\n+\tstruct cvmx_sli_msi_enb2_s cn68xx;\n+\tstruct cvmx_sli_msi_enb2_s cn68xxp1;\n+\tstruct cvmx_sli_msi_enb2_s cn70xx;\n+\tstruct cvmx_sli_msi_enb2_s cn70xxp1;\n+\tstruct cvmx_sli_msi_enb2_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_msi_enb2 cvmx_sli_msi_enb2_t;\n+\n+/**\n+ * cvmx_sli_msi_enb3\n+ *\n+ * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV3.\n+ *\n+ */\n+union cvmx_sli_msi_enb3 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_enb3_s {\n+\t\tu64 enb : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_enb3_s cn61xx;\n+\tstruct cvmx_sli_msi_enb3_s cn63xx;\n+\tstruct cvmx_sli_msi_enb3_s cn63xxp1;\n+\tstruct cvmx_sli_msi_enb3_s cn66xx;\n+\tstruct cvmx_sli_msi_enb3_s cn68xx;\n+\tstruct cvmx_sli_msi_enb3_s cn68xxp1;\n+\tstruct cvmx_sli_msi_enb3_s cn70xx;\n+\tstruct cvmx_sli_msi_enb3_s cn70xxp1;\n+\tstruct cvmx_sli_msi_enb3_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_msi_enb3 cvmx_sli_msi_enb3_t;\n+\n+/**\n+ * cvmx_sli_msi_rcv0\n+ *\n+ * This register contains bits <63:0> of the 256 bits of MSI interrupts.\n+ *\n+ */\n+union cvmx_sli_msi_rcv0 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_rcv0_s {\n+\t\tu64 intr : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_rcv0_s cn61xx;\n+\tstruct cvmx_sli_msi_rcv0_s cn63xx;\n+\tstruct cvmx_sli_msi_rcv0_s cn63xxp1;\n+\tstruct cvmx_sli_msi_rcv0_s cn66xx;\n+\tstruct cvmx_sli_msi_rcv0_s cn68xx;\n+\tstruct cvmx_sli_msi_rcv0_s cn68xxp1;\n+\tstruct cvmx_sli_msi_rcv0_s cn70xx;\n+\tstruct cvmx_sli_msi_rcv0_s cn70xxp1;\n+\tstruct cvmx_sli_msi_rcv0_s cn73xx;\n+\tstruct cvmx_sli_msi_rcv0_s cn78xx;\n+\tstruct cvmx_sli_msi_rcv0_s cn78xxp1;\n+\tstruct cvmx_sli_msi_rcv0_s cnf71xx;\n+\tstruct cvmx_sli_msi_rcv0_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_msi_rcv0 cvmx_sli_msi_rcv0_t;\n+\n+/**\n+ * cvmx_sli_msi_rcv1\n+ *\n+ * This register contains bits <127:64> of the 256 bits of MSI interrupts.\n+ *\n+ */\n+union cvmx_sli_msi_rcv1 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_rcv1_s {\n+\t\tu64 intr : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_rcv1_s cn61xx;\n+\tstruct cvmx_sli_msi_rcv1_s cn63xx;\n+\tstruct cvmx_sli_msi_rcv1_s cn63xxp1;\n+\tstruct cvmx_sli_msi_rcv1_s cn66xx;\n+\tstruct cvmx_sli_msi_rcv1_s cn68xx;\n+\tstruct cvmx_sli_msi_rcv1_s cn68xxp1;\n+\tstruct cvmx_sli_msi_rcv1_s cn70xx;\n+\tstruct cvmx_sli_msi_rcv1_s cn70xxp1;\n+\tstruct cvmx_sli_msi_rcv1_s cn73xx;\n+\tstruct cvmx_sli_msi_rcv1_s cn78xx;\n+\tstruct cvmx_sli_msi_rcv1_s cn78xxp1;\n+\tstruct cvmx_sli_msi_rcv1_s cnf71xx;\n+\tstruct cvmx_sli_msi_rcv1_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_msi_rcv1 cvmx_sli_msi_rcv1_t;\n+\n+/**\n+ * cvmx_sli_msi_rcv2\n+ *\n+ * This register contains bits <191:128> of the 256 bits of MSI interrupts.\n+ *\n+ */\n+union cvmx_sli_msi_rcv2 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_rcv2_s {\n+\t\tu64 intr : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_rcv2_s cn61xx;\n+\tstruct cvmx_sli_msi_rcv2_s cn63xx;\n+\tstruct cvmx_sli_msi_rcv2_s cn63xxp1;\n+\tstruct cvmx_sli_msi_rcv2_s cn66xx;\n+\tstruct cvmx_sli_msi_rcv2_s cn68xx;\n+\tstruct cvmx_sli_msi_rcv2_s cn68xxp1;\n+\tstruct cvmx_sli_msi_rcv2_s cn70xx;\n+\tstruct cvmx_sli_msi_rcv2_s cn70xxp1;\n+\tstruct cvmx_sli_msi_rcv2_s cn73xx;\n+\tstruct cvmx_sli_msi_rcv2_s cn78xx;\n+\tstruct cvmx_sli_msi_rcv2_s cn78xxp1;\n+\tstruct cvmx_sli_msi_rcv2_s cnf71xx;\n+\tstruct cvmx_sli_msi_rcv2_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_msi_rcv2 cvmx_sli_msi_rcv2_t;\n+\n+/**\n+ * cvmx_sli_msi_rcv3\n+ *\n+ * This register contains bits <255:192> of the 256 bits of MSI interrupts.\n+ *\n+ */\n+union cvmx_sli_msi_rcv3 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_rcv3_s {\n+\t\tu64 intr : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_rcv3_s cn61xx;\n+\tstruct cvmx_sli_msi_rcv3_s cn63xx;\n+\tstruct cvmx_sli_msi_rcv3_s cn63xxp1;\n+\tstruct cvmx_sli_msi_rcv3_s cn66xx;\n+\tstruct cvmx_sli_msi_rcv3_s cn68xx;\n+\tstruct cvmx_sli_msi_rcv3_s cn68xxp1;\n+\tstruct cvmx_sli_msi_rcv3_s cn70xx;\n+\tstruct cvmx_sli_msi_rcv3_s cn70xxp1;\n+\tstruct cvmx_sli_msi_rcv3_s cn73xx;\n+\tstruct cvmx_sli_msi_rcv3_s cn78xx;\n+\tstruct cvmx_sli_msi_rcv3_s cn78xxp1;\n+\tstruct cvmx_sli_msi_rcv3_s cnf71xx;\n+\tstruct cvmx_sli_msi_rcv3_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_msi_rcv3 cvmx_sli_msi_rcv3_t;\n+\n+/**\n+ * cvmx_sli_msi_rd_map\n+ *\n+ * This register is used to read the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV\n+ * registers.\n+ */\n+union cvmx_sli_msi_rd_map {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_rd_map_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 rd_int : 8;\n+\t\tu64 msi_int : 8;\n+\t} s;\n+\tstruct cvmx_sli_msi_rd_map_s cn61xx;\n+\tstruct cvmx_sli_msi_rd_map_s cn63xx;\n+\tstruct cvmx_sli_msi_rd_map_s cn63xxp1;\n+\tstruct cvmx_sli_msi_rd_map_s cn66xx;\n+\tstruct cvmx_sli_msi_rd_map_s cn68xx;\n+\tstruct cvmx_sli_msi_rd_map_s cn68xxp1;\n+\tstruct cvmx_sli_msi_rd_map_s cn70xx;\n+\tstruct cvmx_sli_msi_rd_map_s cn70xxp1;\n+\tstruct cvmx_sli_msi_rd_map_s cn73xx;\n+\tstruct cvmx_sli_msi_rd_map_s cn78xx;\n+\tstruct cvmx_sli_msi_rd_map_s cn78xxp1;\n+\tstruct cvmx_sli_msi_rd_map_s cnf71xx;\n+\tstruct cvmx_sli_msi_rd_map_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_msi_rd_map cvmx_sli_msi_rd_map_t;\n+\n+/**\n+ * cvmx_sli_msi_w1c_enb0\n+ *\n+ * Used to clear bits in SLI_MSI_ENB0.\n+ *\n+ */\n+union cvmx_sli_msi_w1c_enb0 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_w1c_enb0_s {\n+\t\tu64 clr : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_w1c_enb0_s cn61xx;\n+\tstruct cvmx_sli_msi_w1c_enb0_s cn63xx;\n+\tstruct cvmx_sli_msi_w1c_enb0_s cn63xxp1;\n+\tstruct cvmx_sli_msi_w1c_enb0_s cn66xx;\n+\tstruct cvmx_sli_msi_w1c_enb0_s cn68xx;\n+\tstruct cvmx_sli_msi_w1c_enb0_s cn68xxp1;\n+\tstruct cvmx_sli_msi_w1c_enb0_s cn70xx;\n+\tstruct cvmx_sli_msi_w1c_enb0_s cn70xxp1;\n+\tstruct cvmx_sli_msi_w1c_enb0_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_msi_w1c_enb0 cvmx_sli_msi_w1c_enb0_t;\n+\n+/**\n+ * cvmx_sli_msi_w1c_enb1\n+ *\n+ * Used to clear bits in SLI_MSI_ENB1.\n+ *\n+ */\n+union cvmx_sli_msi_w1c_enb1 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_w1c_enb1_s {\n+\t\tu64 clr : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_w1c_enb1_s cn61xx;\n+\tstruct cvmx_sli_msi_w1c_enb1_s cn63xx;\n+\tstruct cvmx_sli_msi_w1c_enb1_s cn63xxp1;\n+\tstruct cvmx_sli_msi_w1c_enb1_s cn66xx;\n+\tstruct cvmx_sli_msi_w1c_enb1_s cn68xx;\n+\tstruct cvmx_sli_msi_w1c_enb1_s cn68xxp1;\n+\tstruct cvmx_sli_msi_w1c_enb1_s cn70xx;\n+\tstruct cvmx_sli_msi_w1c_enb1_s cn70xxp1;\n+\tstruct cvmx_sli_msi_w1c_enb1_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_msi_w1c_enb1 cvmx_sli_msi_w1c_enb1_t;\n+\n+/**\n+ * cvmx_sli_msi_w1c_enb2\n+ *\n+ * Used to clear bits in SLI_MSI_ENB2.\n+ *\n+ */\n+union cvmx_sli_msi_w1c_enb2 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_w1c_enb2_s {\n+\t\tu64 clr : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_w1c_enb2_s cn61xx;\n+\tstruct cvmx_sli_msi_w1c_enb2_s cn63xx;\n+\tstruct cvmx_sli_msi_w1c_enb2_s cn63xxp1;\n+\tstruct cvmx_sli_msi_w1c_enb2_s cn66xx;\n+\tstruct cvmx_sli_msi_w1c_enb2_s cn68xx;\n+\tstruct cvmx_sli_msi_w1c_enb2_s cn68xxp1;\n+\tstruct cvmx_sli_msi_w1c_enb2_s cn70xx;\n+\tstruct cvmx_sli_msi_w1c_enb2_s cn70xxp1;\n+\tstruct cvmx_sli_msi_w1c_enb2_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_msi_w1c_enb2 cvmx_sli_msi_w1c_enb2_t;\n+\n+/**\n+ * cvmx_sli_msi_w1c_enb3\n+ *\n+ * Used to clear bits in SLI_MSI_ENB3.\n+ *\n+ */\n+union cvmx_sli_msi_w1c_enb3 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_w1c_enb3_s {\n+\t\tu64 clr : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_w1c_enb3_s cn61xx;\n+\tstruct cvmx_sli_msi_w1c_enb3_s cn63xx;\n+\tstruct cvmx_sli_msi_w1c_enb3_s cn63xxp1;\n+\tstruct cvmx_sli_msi_w1c_enb3_s cn66xx;\n+\tstruct cvmx_sli_msi_w1c_enb3_s cn68xx;\n+\tstruct cvmx_sli_msi_w1c_enb3_s cn68xxp1;\n+\tstruct cvmx_sli_msi_w1c_enb3_s cn70xx;\n+\tstruct cvmx_sli_msi_w1c_enb3_s cn70xxp1;\n+\tstruct cvmx_sli_msi_w1c_enb3_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_msi_w1c_enb3 cvmx_sli_msi_w1c_enb3_t;\n+\n+/**\n+ * cvmx_sli_msi_w1s_enb0\n+ *\n+ * Used to set bits in SLI_MSI_ENB0.\n+ *\n+ */\n+union cvmx_sli_msi_w1s_enb0 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_w1s_enb0_s {\n+\t\tu64 set : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_w1s_enb0_s cn61xx;\n+\tstruct cvmx_sli_msi_w1s_enb0_s cn63xx;\n+\tstruct cvmx_sli_msi_w1s_enb0_s cn63xxp1;\n+\tstruct cvmx_sli_msi_w1s_enb0_s cn66xx;\n+\tstruct cvmx_sli_msi_w1s_enb0_s cn68xx;\n+\tstruct cvmx_sli_msi_w1s_enb0_s cn68xxp1;\n+\tstruct cvmx_sli_msi_w1s_enb0_s cn70xx;\n+\tstruct cvmx_sli_msi_w1s_enb0_s cn70xxp1;\n+\tstruct cvmx_sli_msi_w1s_enb0_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_msi_w1s_enb0 cvmx_sli_msi_w1s_enb0_t;\n+\n+/**\n+ * cvmx_sli_msi_w1s_enb1\n+ *\n+ * SLI_MSI_W1S_ENB0 = SLI MSI Write 1 To Set Enable1\n+ * Used to set bits in SLI_MSI_ENB1.\n+ */\n+union cvmx_sli_msi_w1s_enb1 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_w1s_enb1_s {\n+\t\tu64 set : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_w1s_enb1_s cn61xx;\n+\tstruct cvmx_sli_msi_w1s_enb1_s cn63xx;\n+\tstruct cvmx_sli_msi_w1s_enb1_s cn63xxp1;\n+\tstruct cvmx_sli_msi_w1s_enb1_s cn66xx;\n+\tstruct cvmx_sli_msi_w1s_enb1_s cn68xx;\n+\tstruct cvmx_sli_msi_w1s_enb1_s cn68xxp1;\n+\tstruct cvmx_sli_msi_w1s_enb1_s cn70xx;\n+\tstruct cvmx_sli_msi_w1s_enb1_s cn70xxp1;\n+\tstruct cvmx_sli_msi_w1s_enb1_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_msi_w1s_enb1 cvmx_sli_msi_w1s_enb1_t;\n+\n+/**\n+ * cvmx_sli_msi_w1s_enb2\n+ *\n+ * Used to set bits in SLI_MSI_ENB2.\n+ *\n+ */\n+union cvmx_sli_msi_w1s_enb2 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_w1s_enb2_s {\n+\t\tu64 set : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_w1s_enb2_s cn61xx;\n+\tstruct cvmx_sli_msi_w1s_enb2_s cn63xx;\n+\tstruct cvmx_sli_msi_w1s_enb2_s cn63xxp1;\n+\tstruct cvmx_sli_msi_w1s_enb2_s cn66xx;\n+\tstruct cvmx_sli_msi_w1s_enb2_s cn68xx;\n+\tstruct cvmx_sli_msi_w1s_enb2_s cn68xxp1;\n+\tstruct cvmx_sli_msi_w1s_enb2_s cn70xx;\n+\tstruct cvmx_sli_msi_w1s_enb2_s cn70xxp1;\n+\tstruct cvmx_sli_msi_w1s_enb2_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_msi_w1s_enb2 cvmx_sli_msi_w1s_enb2_t;\n+\n+/**\n+ * cvmx_sli_msi_w1s_enb3\n+ *\n+ * Used to set bits in SLI_MSI_ENB3.\n+ *\n+ */\n+union cvmx_sli_msi_w1s_enb3 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_w1s_enb3_s {\n+\t\tu64 set : 64;\n+\t} s;\n+\tstruct cvmx_sli_msi_w1s_enb3_s cn61xx;\n+\tstruct cvmx_sli_msi_w1s_enb3_s cn63xx;\n+\tstruct cvmx_sli_msi_w1s_enb3_s cn63xxp1;\n+\tstruct cvmx_sli_msi_w1s_enb3_s cn66xx;\n+\tstruct cvmx_sli_msi_w1s_enb3_s cn68xx;\n+\tstruct cvmx_sli_msi_w1s_enb3_s cn68xxp1;\n+\tstruct cvmx_sli_msi_w1s_enb3_s cn70xx;\n+\tstruct cvmx_sli_msi_w1s_enb3_s cn70xxp1;\n+\tstruct cvmx_sli_msi_w1s_enb3_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_msi_w1s_enb3 cvmx_sli_msi_w1s_enb3_t;\n+\n+/**\n+ * cvmx_sli_msi_wr_map\n+ *\n+ * This register is used to write the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV\n+ * registers. At reset, the mapping function is one-to-one, that is MSI_INT 1 maps to CIU_INT 1,\n+ * 2 to 2, 3 to 3, etc.\n+ */\n+union cvmx_sli_msi_wr_map {\n+\tu64 u64;\n+\tstruct cvmx_sli_msi_wr_map_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 ciu_int : 8;\n+\t\tu64 msi_int : 8;\n+\t} s;\n+\tstruct cvmx_sli_msi_wr_map_s cn61xx;\n+\tstruct cvmx_sli_msi_wr_map_s cn63xx;\n+\tstruct cvmx_sli_msi_wr_map_s cn63xxp1;\n+\tstruct cvmx_sli_msi_wr_map_s cn66xx;\n+\tstruct cvmx_sli_msi_wr_map_s cn68xx;\n+\tstruct cvmx_sli_msi_wr_map_s cn68xxp1;\n+\tstruct cvmx_sli_msi_wr_map_s cn70xx;\n+\tstruct cvmx_sli_msi_wr_map_s cn70xxp1;\n+\tstruct cvmx_sli_msi_wr_map_s cn73xx;\n+\tstruct cvmx_sli_msi_wr_map_s cn78xx;\n+\tstruct cvmx_sli_msi_wr_map_s cn78xxp1;\n+\tstruct cvmx_sli_msi_wr_map_s cnf71xx;\n+\tstruct cvmx_sli_msi_wr_map_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_msi_wr_map cvmx_sli_msi_wr_map_t;\n+\n+/**\n+ * cvmx_sli_msix#_table_addr\n+ *\n+ * The MSI-X table cannot be burst read or written.\n+ *\n+ * The combination of all MSI-X Tables contain (64 + 4) entries - one per\n+ * ring plus one per PF. (i.e. 64 plus one per valid SLI_MAC()_PF()_INT_SUM\n+ * present.)\n+ *\n+ * The MSI-X table for an individual PF has SLI_PKT_MAC()_PF()_RINFO[TRS]\n+ * entries for the rings associated to the PF (up to 64 max) plus one\n+ * more table entry for SLI_MAC()_PF()_INT_SUM. The\n+ * SLI_MAC()_PF()_INT_SUM-related MSI-X table entry is\n+ * always entry SLI_MSIX(SLI_PKT_MAC()_PF()_RINFO[TRS])_TABLE_ADDR and\n+ * always present and valid. All earlier SLI_MSIX()_TABLE_ADDR entries\n+ * correspond to rings. When SLI_PKT_MAC()_PF()_RINFO[NVFS]=0, SR-IOV\n+ * virtual functions cannot be used, and all SLI_PKT_MAC()_PF()_RINFO[TRS]+1\n+ * entries in the PF MSI-X table are present and valid for use by the PF.\n+ * When SLI_PKT_MAC()_PF()_RINFO[NVFS]!=0, SR-IOV virtual functions may\n+ * be used, and the first\n+ *   SLI_PKT_MAC()_PF()_RINFO[NVFS]*SLI_PKT_MAC()_PF()_RINFO[RPVF]\n+ * entries of the PF MSI-X table are present but not valid, and\n+ * should never be accessed by the PF.\n+ *\n+ * The MSI-X table for an individual VF has SLI_PKT_MAC()_PF()_RINFO[RPVF]\n+ * entries (up to 8 max), all valid, one per ring that the VF owns.\n+ */\n+union cvmx_sli_msixx_table_addr {\n+\tu64 u64;\n+\tstruct cvmx_sli_msixx_table_addr_s {\n+\t\tu64 addr : 64;\n+\t} s;\n+\tstruct cvmx_sli_msixx_table_addr_s cn73xx;\n+\tstruct cvmx_sli_msixx_table_addr_s cn78xx;\n+\tstruct cvmx_sli_msixx_table_addr_s cn78xxp1;\n+\tstruct cvmx_sli_msixx_table_addr_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_msixx_table_addr cvmx_sli_msixx_table_addr_t;\n+\n+/**\n+ * cvmx_sli_msix#_table_data\n+ *\n+ * The MSI-X table cannot be burst read or written. VF/PF access is the same as\n+ * described for the SLI_MSIX()_TABLE_ADDR.\n+ */\n+union cvmx_sli_msixx_table_data {\n+\tu64 u64;\n+\tstruct cvmx_sli_msixx_table_data_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 vector_ctl : 1;\n+\t\tu64 data : 32;\n+\t} s;\n+\tstruct cvmx_sli_msixx_table_data_s cn73xx;\n+\tstruct cvmx_sli_msixx_table_data_s cn78xx;\n+\tstruct cvmx_sli_msixx_table_data_s cn78xxp1;\n+\tstruct cvmx_sli_msixx_table_data_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_msixx_table_data cvmx_sli_msixx_table_data_t;\n+\n+/**\n+ * cvmx_sli_msix_mac#_pf_table_addr\n+ *\n+ * These registers shadow the four physical MSIX PF ERR entries.\n+ * Each MAC sees its entry at its own TRS offset.\n+ */\n+union cvmx_sli_msix_macx_pf_table_addr {\n+\tu64 u64;\n+\tstruct cvmx_sli_msix_macx_pf_table_addr_s {\n+\t\tu64 addr : 64;\n+\t} s;\n+\tstruct cvmx_sli_msix_macx_pf_table_addr_s cn78xxp1;\n+};\n+\n+typedef union cvmx_sli_msix_macx_pf_table_addr cvmx_sli_msix_macx_pf_table_addr_t;\n+\n+/**\n+ * cvmx_sli_msix_mac#_pf_table_data\n+ *\n+ * These registers shadow four physical MSIX PF ERR entries.\n+ * Each MAC sees its entry at its own TRS offset.\n+ */\n+union cvmx_sli_msix_macx_pf_table_data {\n+\tu64 u64;\n+\tstruct cvmx_sli_msix_macx_pf_table_data_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 vector_ctl : 1;\n+\t\tu64 data : 32;\n+\t} s;\n+\tstruct cvmx_sli_msix_macx_pf_table_data_s cn78xxp1;\n+};\n+\n+typedef union cvmx_sli_msix_macx_pf_table_data cvmx_sli_msix_macx_pf_table_data_t;\n+\n+/**\n+ * cvmx_sli_msix_pba0\n+ *\n+ * The MSI-X pending bit array cannot be burst read.\n+ * In SR-IOV mode, a VF will find its pending completion interrupts in bit\n+ * positions [(RPVF-1):0]. If RPVF<64, bits [63:RPVF] are returned as zero.\n+ *\n+ * Each VF can read their own pending completion interrupts based on the ring/VF\n+ * configuration. Therefore, a VF sees the PBA as smaller than what is shown below\n+ * (unless it owns all 64 entries).  Unassigned bits will return zeros.\n+ *\n+ * <pre>\n+ *    RPVF  Interrupts per VF   Pending bits returned\n+ *    ----  -----------------   ---------------------\n+ *      0            0          0\n+ *      1            1          MSG_PND0\n+ *      2            2          MSG_PND1  - MSG_PND0\n+ *      4            4          MSG_PND3  - MSG_PND0\n+ *      8            8          MSG_PND7  - MSG_PND0\n+ * </pre>\n+ *\n+ * If SLI_PKT_MAC()_PF()_RINFO[TRS]=63 (i.e. 64 total DPI Packet Rings configured), a PF will\n+ * find its pending completion interrupts in bit positions [63:0]. When\n+ * SLI_PKT_MAC()_PF()_RINFO[TRS]=63,\n+ * the PF will find its PCIe error interrupt in SLI_MSIX_PBA1, bit position 0.\n+ *\n+ * If SLI_PKT_MAC()_PF()_RINFO[TRS]<63 (i.e. 0, 1, 2, 4, or 8 rings configured), a PF will find\n+ * its ring pending completion interrupts in bit positions [TNR:0]. It will find its PCIe\n+ * error interrupt in bit position [(TNR+1)]. Bits [63:(TNR+2)] are returned as zero.\n+ * When SLI_PKT_MAC()_PF()_RINFO[TRS]<63, SLI_MSIX_PBA1 is not used and returns zeros.\n+ *\n+ * If SR-IOV Mode is off there is no virtual function support, but the PF can configure up to 65\n+ * entries (up to 64 DPI Packet Rings plus 1 PF ring) for itself.\n+ */\n+union cvmx_sli_msix_pba0 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msix_pba0_s {\n+\t\tu64 msg_pnd : 64;\n+\t} s;\n+\tstruct cvmx_sli_msix_pba0_s cn73xx;\n+\tstruct cvmx_sli_msix_pba0_s cn78xx;\n+\tstruct cvmx_sli_msix_pba0_s cn78xxp1;\n+\tstruct cvmx_sli_msix_pba0_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_msix_pba0 cvmx_sli_msix_pba0_t;\n+\n+/**\n+ * cvmx_sli_msix_pba1\n+ *\n+ * The MSI-X pending bit array cannot be burst read.\n+ *\n+ * PF_PND is assigned to PCIe related errors. The error bit can only be found in PBA1 when\n+ * SLI_PKT_MAC()_PF()_RINFO[TRS]=63 (i.e. 64 total DPI Packet Rings configured).\n+ *\n+ * This register is accessible by the PF. A read by a particular PF only\n+ * returns its own pending status. That is, any PF can read this register, but the hardware\n+ * ensures\n+ * that the PF only sees its own status.\n+ */\n+union cvmx_sli_msix_pba1 {\n+\tu64 u64;\n+\tstruct cvmx_sli_msix_pba1_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 pf_pnd : 1;\n+\t} s;\n+\tstruct cvmx_sli_msix_pba1_s cn73xx;\n+\tstruct cvmx_sli_msix_pba1_s cn78xx;\n+\tstruct cvmx_sli_msix_pba1_s cn78xxp1;\n+\tstruct cvmx_sli_msix_pba1_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_msix_pba1 cvmx_sli_msix_pba1_t;\n+\n+/**\n+ * cvmx_sli_nqm_rsp_err_snd_dbg\n+ *\n+ * This register is for diagnostic use only.\n+ *\n+ */\n+union cvmx_sli_nqm_rsp_err_snd_dbg {\n+\tu64 u64;\n+\tstruct cvmx_sli_nqm_rsp_err_snd_dbg_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 vf_index : 12;\n+\t} s;\n+\tstruct cvmx_sli_nqm_rsp_err_snd_dbg_s cn73xx;\n+\tstruct cvmx_sli_nqm_rsp_err_snd_dbg_s cn78xx;\n+\tstruct cvmx_sli_nqm_rsp_err_snd_dbg_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_nqm_rsp_err_snd_dbg cvmx_sli_nqm_rsp_err_snd_dbg_t;\n+\n+/**\n+ * cvmx_sli_pcie_msi_rcv\n+ *\n+ * This is the register where MSI write operations are directed from the MAC.\n+ *\n+ */\n+union cvmx_sli_pcie_msi_rcv {\n+\tu64 u64;\n+\tstruct cvmx_sli_pcie_msi_rcv_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 intr : 8;\n+\t} s;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cn61xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cn63xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cn63xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cn66xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cn68xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cn68xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cn70xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cn70xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cn73xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cn78xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cn78xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cnf71xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pcie_msi_rcv cvmx_sli_pcie_msi_rcv_t;\n+\n+/**\n+ * cvmx_sli_pcie_msi_rcv_b1\n+ *\n+ * This register is where MSI write operations are directed from the MAC. This register can be\n+ * used by the PCIe and SRIO MACs.\n+ */\n+union cvmx_sli_pcie_msi_rcv_b1 {\n+\tu64 u64;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 intr : 8;\n+\t\tu64 reserved_0_7 : 8;\n+\t} s;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cn70xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cn70xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cn73xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cn78xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cn78xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cnf71xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b1_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pcie_msi_rcv_b1 cvmx_sli_pcie_msi_rcv_b1_t;\n+\n+/**\n+ * cvmx_sli_pcie_msi_rcv_b2\n+ *\n+ * This register is where MSI write operations are directed from the MAC.  This register can be\n+ * used by PCIe and SRIO MACs.\n+ */\n+union cvmx_sli_pcie_msi_rcv_b2 {\n+\tu64 u64;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 intr : 8;\n+\t\tu64 reserved_0_15 : 16;\n+\t} s;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cn70xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cn70xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cn73xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cn78xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cn78xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cnf71xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b2_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pcie_msi_rcv_b2 cvmx_sli_pcie_msi_rcv_b2_t;\n+\n+/**\n+ * cvmx_sli_pcie_msi_rcv_b3\n+ *\n+ * This register is where MSI write operations are directed from the MAC. This register can be\n+ * used by PCIe and SRIO MACs.\n+ */\n+union cvmx_sli_pcie_msi_rcv_b3 {\n+\tu64 u64;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 intr : 8;\n+\t\tu64 reserved_0_23 : 24;\n+\t} s;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cn70xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cn70xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cn73xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cn78xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cn78xxp1;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cnf71xx;\n+\tstruct cvmx_sli_pcie_msi_rcv_b3_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pcie_msi_rcv_b3 cvmx_sli_pcie_msi_rcv_b3_t;\n+\n+/**\n+ * cvmx_sli_pkt#_cnts\n+ *\n+ * This register contains the counters for output rings.\n+ *\n+ */\n+union cvmx_sli_pktx_cnts {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_cnts_s {\n+\t\tu64 po_int : 1;\n+\t\tu64 pi_int : 1;\n+\t\tu64 mbox_int : 1;\n+\t\tu64 resend : 1;\n+\t\tu64 reserved_54_59 : 6;\n+\t\tu64 timer : 22;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_sli_pktx_cnts_cn61xx {\n+\t\tu64 reserved_54_63 : 10;\n+\t\tu64 timer : 22;\n+\t\tu64 cnt : 32;\n+\t} cn61xx;\n+\tstruct cvmx_sli_pktx_cnts_cn61xx cn63xx;\n+\tstruct cvmx_sli_pktx_cnts_cn61xx cn63xxp1;\n+\tstruct cvmx_sli_pktx_cnts_cn61xx cn66xx;\n+\tstruct cvmx_sli_pktx_cnts_cn61xx cn68xx;\n+\tstruct cvmx_sli_pktx_cnts_cn61xx cn68xxp1;\n+\tstruct cvmx_sli_pktx_cnts_cn70xx {\n+\t\tu64 reserved_63_54 : 10;\n+\t\tu64 timer : 22;\n+\t\tu64 cnt : 32;\n+\t} cn70xx;\n+\tstruct cvmx_sli_pktx_cnts_cn70xx cn70xxp1;\n+\tstruct cvmx_sli_pktx_cnts_s cn73xx;\n+\tstruct cvmx_sli_pktx_cnts_s cn78xx;\n+\tstruct cvmx_sli_pktx_cnts_cn78xxp1 {\n+\t\tu64 po_int : 1;\n+\t\tu64 pi_int : 1;\n+\t\tu64 reserved_61_54 : 8;\n+\t\tu64 timer : 22;\n+\t\tu64 cnt : 32;\n+\t} cn78xxp1;\n+\tstruct cvmx_sli_pktx_cnts_cn61xx cnf71xx;\n+\tstruct cvmx_sli_pktx_cnts_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_cnts cvmx_sli_pktx_cnts_t;\n+\n+/**\n+ * cvmx_sli_pkt#_error_info\n+ *\n+ * The fields in this register are set when an error conditions occur and can be cleared.\n+ * These fields are for information purpose only and do NOT generate interrupts.\n+ */\n+union cvmx_sli_pktx_error_info {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_error_info_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 osize_err : 1;\n+\t\tu64 nobdell_err : 1;\n+\t\tu64 pins_err : 1;\n+\t\tu64 pop_err : 1;\n+\t\tu64 pdi_err : 1;\n+\t\tu64 pgl_err : 1;\n+\t\tu64 psldbof : 1;\n+\t\tu64 pidbof : 1;\n+\t} s;\n+\tstruct cvmx_sli_pktx_error_info_s cn73xx;\n+\tstruct cvmx_sli_pktx_error_info_s cn78xx;\n+\tstruct cvmx_sli_pktx_error_info_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_error_info cvmx_sli_pktx_error_info_t;\n+\n+/**\n+ * cvmx_sli_pkt#_in_bp\n+ *\n+ * \"SLI_PKT[0..31]_IN_BP = SLI Packet ring# Input Backpressure\n+ * The counters and thresholds for input packets to apply backpressure to processing of the\n+ * packets.\"\n+ */\n+union cvmx_sli_pktx_in_bp {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_in_bp_s {\n+\t\tu64 wmark : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_sli_pktx_in_bp_s cn61xx;\n+\tstruct cvmx_sli_pktx_in_bp_s cn63xx;\n+\tstruct cvmx_sli_pktx_in_bp_s cn63xxp1;\n+\tstruct cvmx_sli_pktx_in_bp_s cn66xx;\n+\tstruct cvmx_sli_pktx_in_bp_s cn70xx;\n+\tstruct cvmx_sli_pktx_in_bp_s cn70xxp1;\n+\tstruct cvmx_sli_pktx_in_bp_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pktx_in_bp cvmx_sli_pktx_in_bp_t;\n+\n+/**\n+ * cvmx_sli_pkt#_input_control\n+ *\n+ * This register is the control for read operations for gather list and instructions.\n+ *\n+ */\n+union cvmx_sli_pktx_input_control {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_input_control_s {\n+\t\tu64 reserved_55_63 : 9;\n+\t\tu64 rpvf : 7;\n+\t\tu64 reserved_31_47 : 17;\n+\t\tu64 mac_num : 2;\n+\t\tu64 quiet : 1;\n+\t\tu64 reserved_27_27 : 1;\n+\t\tu64 rdsize : 2;\n+\t\tu64 is_64b : 1;\n+\t\tu64 rst : 1;\n+\t\tu64 enb : 1;\n+\t\tu64 pbp_dhi : 13;\n+\t\tu64 d_nsr : 1;\n+\t\tu64 d_esr : 2;\n+\t\tu64 d_ror : 1;\n+\t\tu64 use_csr : 1;\n+\t\tu64 nsr : 1;\n+\t\tu64 esr : 2;\n+\t\tu64 ror : 1;\n+\t} s;\n+\tstruct cvmx_sli_pktx_input_control_cn73xx {\n+\t\tu64 reserved_55_63 : 9;\n+\t\tu64 rpvf : 7;\n+\t\tu64 pvf_num : 16;\n+\t\tu64 reserved_31_31 : 1;\n+\t\tu64 mac_num : 2;\n+\t\tu64 quiet : 1;\n+\t\tu64 reserved_27_27 : 1;\n+\t\tu64 rdsize : 2;\n+\t\tu64 is_64b : 1;\n+\t\tu64 rst : 1;\n+\t\tu64 enb : 1;\n+\t\tu64 pbp_dhi : 13;\n+\t\tu64 d_nsr : 1;\n+\t\tu64 d_esr : 2;\n+\t\tu64 d_ror : 1;\n+\t\tu64 use_csr : 1;\n+\t\tu64 nsr : 1;\n+\t\tu64 esr : 2;\n+\t\tu64 ror : 1;\n+\t} cn73xx;\n+\tstruct cvmx_sli_pktx_input_control_cn73xx cn78xx;\n+\tstruct cvmx_sli_pktx_input_control_cn78xxp1 {\n+\t\tu64 reserved_39_63 : 25;\n+\t\tu64 vf_num : 7;\n+\t\tu64 reserved_31_31 : 1;\n+\t\tu64 mac_num : 2;\n+\t\tu64 reserved_27_28 : 2;\n+\t\tu64 rdsize : 2;\n+\t\tu64 is_64b : 1;\n+\t\tu64 rst : 1;\n+\t\tu64 enb : 1;\n+\t\tu64 pbp_dhi : 13;\n+\t\tu64 d_nsr : 1;\n+\t\tu64 d_esr : 2;\n+\t\tu64 d_ror : 1;\n+\t\tu64 use_csr : 1;\n+\t\tu64 nsr : 1;\n+\t\tu64 esr : 2;\n+\t\tu64 ror : 1;\n+\t} cn78xxp1;\n+\tstruct cvmx_sli_pktx_input_control_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_input_control cvmx_sli_pktx_input_control_t;\n+\n+/**\n+ * cvmx_sli_pkt#_instr_baddr\n+ *\n+ * This register contains the start-of-instruction for input packets. The address must be\n+ * addressed-aligned to the size of the instruction.\n+ */\n+union cvmx_sli_pktx_instr_baddr {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_instr_baddr_s {\n+\t\tu64 addr : 61;\n+\t\tu64 reserved_0_2 : 3;\n+\t} s;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cn61xx;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cn63xx;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cn63xxp1;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cn66xx;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cn68xx;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cn68xxp1;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cn70xx;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cn70xxp1;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cn73xx;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cn78xx;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cn78xxp1;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cnf71xx;\n+\tstruct cvmx_sli_pktx_instr_baddr_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_instr_baddr cvmx_sli_pktx_instr_baddr_t;\n+\n+/**\n+ * cvmx_sli_pkt#_instr_baoff_dbell\n+ *\n+ * This register contains the doorbell and base address offset for the next read.\n+ *\n+ */\n+union cvmx_sli_pktx_instr_baoff_dbell {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s {\n+\t\tu64 aoff : 32;\n+\t\tu64 dbell : 32;\n+\t} s;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cn70xx;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cn70xxp1;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cn73xx;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cn78xx;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cn78xxp1;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx;\n+\tstruct cvmx_sli_pktx_instr_baoff_dbell_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_instr_baoff_dbell cvmx_sli_pktx_instr_baoff_dbell_t;\n+\n+/**\n+ * cvmx_sli_pkt#_instr_fifo_rsize\n+ *\n+ * This register contains the FIFO field and ring size for instructions.\n+ *\n+ */\n+union cvmx_sli_pktx_instr_fifo_rsize {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s {\n+\t\tu64 max : 9;\n+\t\tu64 rrp : 9;\n+\t\tu64 wrp : 9;\n+\t\tu64 fcnt : 5;\n+\t\tu64 rsize : 32;\n+\t} s;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cn70xx;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cn70xxp1;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cn73xx;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cn78xx;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cn78xxp1;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx;\n+\tstruct cvmx_sli_pktx_instr_fifo_rsize_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_instr_fifo_rsize cvmx_sli_pktx_instr_fifo_rsize_t;\n+\n+/**\n+ * cvmx_sli_pkt#_instr_header\n+ *\n+ * \"SLI_PKT[0..31]_INSTR_HEADER = SLI Packet ring# Instruction Header.\n+ * VAlues used to build input packet header.\"\n+ */\n+union cvmx_sli_pktx_instr_header {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_instr_header_s {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 pbp : 1;\n+\t\tu64 reserved_38_42 : 5;\n+\t\tu64 rparmode : 2;\n+\t\tu64 reserved_35_35 : 1;\n+\t\tu64 rskp_len : 7;\n+\t\tu64 rngrpext : 2;\n+\t\tu64 rnqos : 1;\n+\t\tu64 rngrp : 1;\n+\t\tu64 rntt : 1;\n+\t\tu64 rntag : 1;\n+\t\tu64 use_ihdr : 1;\n+\t\tu64 reserved_16_20 : 5;\n+\t\tu64 par_mode : 2;\n+\t\tu64 reserved_13_13 : 1;\n+\t\tu64 skp_len : 7;\n+\t\tu64 ngrpext : 2;\n+\t\tu64 nqos : 1;\n+\t\tu64 ngrp : 1;\n+\t\tu64 ntt : 1;\n+\t\tu64 ntag : 1;\n+\t} s;\n+\tstruct cvmx_sli_pktx_instr_header_cn61xx {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 pbp : 1;\n+\t\tu64 reserved_38_42 : 5;\n+\t\tu64 rparmode : 2;\n+\t\tu64 reserved_35_35 : 1;\n+\t\tu64 rskp_len : 7;\n+\t\tu64 reserved_26_27 : 2;\n+\t\tu64 rnqos : 1;\n+\t\tu64 rngrp : 1;\n+\t\tu64 rntt : 1;\n+\t\tu64 rntag : 1;\n+\t\tu64 use_ihdr : 1;\n+\t\tu64 reserved_16_20 : 5;\n+\t\tu64 par_mode : 2;\n+\t\tu64 reserved_13_13 : 1;\n+\t\tu64 skp_len : 7;\n+\t\tu64 reserved_4_5 : 2;\n+\t\tu64 nqos : 1;\n+\t\tu64 ngrp : 1;\n+\t\tu64 ntt : 1;\n+\t\tu64 ntag : 1;\n+\t} cn61xx;\n+\tstruct cvmx_sli_pktx_instr_header_cn61xx cn63xx;\n+\tstruct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;\n+\tstruct cvmx_sli_pktx_instr_header_cn61xx cn66xx;\n+\tstruct cvmx_sli_pktx_instr_header_s cn68xx;\n+\tstruct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;\n+\tstruct cvmx_sli_pktx_instr_header_cn70xx {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 pbp : 1;\n+\t\tu64 reserved_38_42 : 5;\n+\t\tu64 rparmode : 2;\n+\t\tu64 reserved_35_35 : 1;\n+\t\tu64 rskp_len : 7;\n+\t\tu64 reserved_27_26 : 2;\n+\t\tu64 rnqos : 1;\n+\t\tu64 rngrp : 1;\n+\t\tu64 rntt : 1;\n+\t\tu64 rntag : 1;\n+\t\tu64 use_ihdr : 1;\n+\t\tu64 reserved_20_16 : 5;\n+\t\tu64 par_mode : 2;\n+\t\tu64 reserved_13_13 : 1;\n+\t\tu64 skp_len : 7;\n+\t\tu64 reserved_5_4 : 2;\n+\t\tu64 nqos : 1;\n+\t\tu64 ngrp : 1;\n+\t\tu64 ntt : 1;\n+\t\tu64 ntag : 1;\n+\t} cn70xx;\n+\tstruct cvmx_sli_pktx_instr_header_cn70xx cn70xxp1;\n+\tstruct cvmx_sli_pktx_instr_header_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pktx_instr_header cvmx_sli_pktx_instr_header_t;\n+\n+/**\n+ * cvmx_sli_pkt#_int_levels\n+ *\n+ * This register contains output-packet interrupt levels.\n+ *\n+ */\n+union cvmx_sli_pktx_int_levels {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_int_levels_s {\n+\t\tu64 reserved_54_63 : 10;\n+\t\tu64 time : 22;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_sli_pktx_int_levels_s cn73xx;\n+\tstruct cvmx_sli_pktx_int_levels_s cn78xx;\n+\tstruct cvmx_sli_pktx_int_levels_s cn78xxp1;\n+\tstruct cvmx_sli_pktx_int_levels_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_int_levels cvmx_sli_pktx_int_levels_t;\n+\n+/**\n+ * cvmx_sli_pkt#_mbox_int\n+ *\n+ * This register contains information to service mbox interrupts to the VF\n+ * when the PF writes SLI_PKT()_PF_VF_MBOX_SIG(0).\n+ */\n+union cvmx_sli_pktx_mbox_int {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_mbox_int_s {\n+\t\tu64 po_int : 1;\n+\t\tu64 pi_int : 1;\n+\t\tu64 mbox_int : 1;\n+\t\tu64 resend : 1;\n+\t\tu64 reserved_1_59 : 59;\n+\t\tu64 mbox_en : 1;\n+\t} s;\n+\tstruct cvmx_sli_pktx_mbox_int_s cn73xx;\n+\tstruct cvmx_sli_pktx_mbox_int_s cn78xx;\n+\tstruct cvmx_sli_pktx_mbox_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_mbox_int cvmx_sli_pktx_mbox_int_t;\n+\n+/**\n+ * cvmx_sli_pkt#_out_size\n+ *\n+ * This register contains the BSIZE and ISIZE for output packet rings.\n+ *\n+ */\n+union cvmx_sli_pktx_out_size {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_out_size_s {\n+\t\tu64 reserved_23_63 : 41;\n+\t\tu64 isize : 7;\n+\t\tu64 bsize : 16;\n+\t} s;\n+\tstruct cvmx_sli_pktx_out_size_s cn61xx;\n+\tstruct cvmx_sli_pktx_out_size_s cn63xx;\n+\tstruct cvmx_sli_pktx_out_size_s cn63xxp1;\n+\tstruct cvmx_sli_pktx_out_size_s cn66xx;\n+\tstruct cvmx_sli_pktx_out_size_s cn68xx;\n+\tstruct cvmx_sli_pktx_out_size_s cn68xxp1;\n+\tstruct cvmx_sli_pktx_out_size_s cn70xx;\n+\tstruct cvmx_sli_pktx_out_size_s cn70xxp1;\n+\tstruct cvmx_sli_pktx_out_size_cn73xx {\n+\t\tu64 reserved_22_63 : 42;\n+\t\tu64 isize : 6;\n+\t\tu64 bsize : 16;\n+\t} cn73xx;\n+\tstruct cvmx_sli_pktx_out_size_cn73xx cn78xx;\n+\tstruct cvmx_sli_pktx_out_size_s cn78xxp1;\n+\tstruct cvmx_sli_pktx_out_size_s cnf71xx;\n+\tstruct cvmx_sli_pktx_out_size_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_out_size cvmx_sli_pktx_out_size_t;\n+\n+/**\n+ * cvmx_sli_pkt#_output_control\n+ *\n+ * This register is the control for read operations for gather list and instructions.\n+ *\n+ */\n+union cvmx_sli_pktx_output_control {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_output_control_s {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 tenb : 1;\n+\t\tu64 cenb : 1;\n+\t\tu64 iptr : 1;\n+\t\tu64 es : 2;\n+\t\tu64 nsr : 1;\n+\t\tu64 ror : 1;\n+\t\tu64 dptr : 1;\n+\t\tu64 bmode : 1;\n+\t\tu64 es_p : 2;\n+\t\tu64 nsr_p : 1;\n+\t\tu64 ror_p : 1;\n+\t\tu64 enb : 1;\n+\t} s;\n+\tstruct cvmx_sli_pktx_output_control_s cn73xx;\n+\tstruct cvmx_sli_pktx_output_control_s cn78xx;\n+\tstruct cvmx_sli_pktx_output_control_s cn78xxp1;\n+\tstruct cvmx_sli_pktx_output_control_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_output_control cvmx_sli_pktx_output_control_t;\n+\n+/**\n+ * cvmx_sli_pkt#_pf_vf_mbox_sig#\n+ *\n+ * These registers are used for communication of data from the PF to the VF and vice versa.\n+ *\n+ * There are two registers per ring, SIG(0) and SIG(1). The PF and VF, both, have read and\n+ * write access to these registers.\n+ *\n+ * For PF-to-VF ring interrupts, SLI_PKT(0..63)_MBOX_INT[MBOX_EN] must be set.\n+ * When [MBOX_EN] is set, writes from the PF to byte 0 of the SIG(0) register will cause\n+ * an interrupt by setting [MBOX_INT] in the corresponding ring address of\n+ * SLI_PKT()_MBOX_INT[MBOX_INT],\n+ * SLI_PKT_IN_DONE()_CNTS[MBOX_INT], and SLI_PKT()_CNTS[MBOX_INT].\n+ *\n+ * For VF-to-PF ring interrupt, SLI_MAC()_PF()_INT_ENB[VF_MBOX] must be set.\n+ * When [VF_MBOX] is set, write from the VF to byte 0 of the SIG(1) register will cause an\n+ * interrupt by setting ring address VF_INT field in corresponding SLI_MAC()_PF()_MBOX_INT\n+ * register,\n+ * which may cause an interrupt to occur through PF.\n+ *\n+ * Each PF and VF can only access the rings that it owns as programmed by\n+ * SLI_PKT_MAC()_PF()_RINFO.\n+ * The signaling is ring-based. If a VF owns more than one ring, it can ignore the other\n+ * rings' registers if not needed.\n+ */\n+union cvmx_sli_pktx_pf_vf_mbox_sigx {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_pf_vf_mbox_sigx_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_sli_pktx_pf_vf_mbox_sigx_s cn73xx;\n+\tstruct cvmx_sli_pktx_pf_vf_mbox_sigx_s cn78xx;\n+\tstruct cvmx_sli_pktx_pf_vf_mbox_sigx_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_pf_vf_mbox_sigx cvmx_sli_pktx_pf_vf_mbox_sigx_t;\n+\n+/**\n+ * cvmx_sli_pkt#_slist_baddr\n+ *\n+ * This register contains the start of scatter list for output-packet pointers. This address must\n+ * be 16-byte aligned.\n+ */\n+union cvmx_sli_pktx_slist_baddr {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_slist_baddr_s {\n+\t\tu64 addr : 60;\n+\t\tu64 reserved_0_3 : 4;\n+\t} s;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cn61xx;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cn63xx;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cn63xxp1;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cn66xx;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cn68xx;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cn68xxp1;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cn70xx;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cn70xxp1;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cn73xx;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cn78xx;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cn78xxp1;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cnf71xx;\n+\tstruct cvmx_sli_pktx_slist_baddr_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_slist_baddr cvmx_sli_pktx_slist_baddr_t;\n+\n+/**\n+ * cvmx_sli_pkt#_slist_baoff_dbell\n+ *\n+ * This register contains the doorbell and base-address offset for next read operation.\n+ *\n+ */\n+union cvmx_sli_pktx_slist_baoff_dbell {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s {\n+\t\tu64 aoff : 32;\n+\t\tu64 dbell : 32;\n+\t} s;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cn70xx;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cn70xxp1;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cn73xx;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cn78xx;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cn78xxp1;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx;\n+\tstruct cvmx_sli_pktx_slist_baoff_dbell_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_slist_baoff_dbell cvmx_sli_pktx_slist_baoff_dbell_t;\n+\n+/**\n+ * cvmx_sli_pkt#_slist_fifo_rsize\n+ *\n+ * This register contains the number of scatter pointer pairs in the scatter list.\n+ *\n+ */\n+union cvmx_sli_pktx_slist_fifo_rsize {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 rsize : 32;\n+\t} s;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_cn70xx {\n+\t\tu64 reserved_63_32 : 32;\n+\t\tu64 rsize : 32;\n+\t} cn70xx;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_cn70xx cn70xxp1;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_cn70xx cn73xx;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_cn70xx cn78xx;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_cn70xx cn78xxp1;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx;\n+\tstruct cvmx_sli_pktx_slist_fifo_rsize_cn70xx cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_slist_fifo_rsize cvmx_sli_pktx_slist_fifo_rsize_t;\n+\n+/**\n+ * cvmx_sli_pkt#_vf_int_sum\n+ *\n+ * This register contains summary interrupts bits for a VF. A VF read of this register\n+ * for any of its 8 rings will return the same 8-bit summary for packet input, packet\n+ * output and mailbox interrupts. If a PF reads this register it will return 0x0.\n+ */\n+union cvmx_sli_pktx_vf_int_sum {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_vf_int_sum_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 mbox : 8;\n+\t\tu64 reserved_24_31 : 8;\n+\t\tu64 pkt_out : 8;\n+\t\tu64 reserved_8_15 : 8;\n+\t\tu64 pkt_in : 8;\n+\t} s;\n+\tstruct cvmx_sli_pktx_vf_int_sum_s cn73xx;\n+\tstruct cvmx_sli_pktx_vf_int_sum_s cn78xx;\n+\tstruct cvmx_sli_pktx_vf_int_sum_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pktx_vf_int_sum cvmx_sli_pktx_vf_int_sum_t;\n+\n+/**\n+ * cvmx_sli_pkt#_vf_sig\n+ *\n+ * This register is used to signal between PF/VF. These 64 registers are index by VF number.\n+ *\n+ */\n+union cvmx_sli_pktx_vf_sig {\n+\tu64 u64;\n+\tstruct cvmx_sli_pktx_vf_sig_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_sli_pktx_vf_sig_s cn78xxp1;\n+};\n+\n+typedef union cvmx_sli_pktx_vf_sig cvmx_sli_pktx_vf_sig_t;\n+\n+/**\n+ * cvmx_sli_pkt_bist_status\n+ *\n+ * This is the built-in self-test (BIST) status register. Each bit is the BIST result of an\n+ * individual memory (per bit, 0 = pass and 1 = fail).\n+ */\n+union cvmx_sli_pkt_bist_status {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_bist_status_s {\n+\t\tu64 reserved_22_63 : 42;\n+\t\tu64 bist : 22;\n+\t} s;\n+\tstruct cvmx_sli_pkt_bist_status_s cn73xx;\n+\tstruct cvmx_sli_pkt_bist_status_s cn78xx;\n+\tstruct cvmx_sli_pkt_bist_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_bist_status cvmx_sli_pkt_bist_status_t;\n+\n+/**\n+ * cvmx_sli_pkt_cnt_int\n+ *\n+ * This register specifies which output packet rings are interrupting because of packet counters.\n+ * A bit set in this interrupt register will set a corresponding bit in SLI_PKT_INT and can\n+ * also cause SLI_MAC()_PF()_INT_SUM[PCNT] to be set if SLI_PKT()_OUTPUT_CONTROL[CENB] is set.\n+ * When read by a function, this register informs which rings owned by the function (0 to N,\n+ * N as large as 63) have this interrupt pending.\n+ */\n+union cvmx_sli_pkt_cnt_int {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_cnt_int_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_cnt_int_cn61xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 port : 32;\n+\t} cn61xx;\n+\tstruct cvmx_sli_pkt_cnt_int_cn61xx cn63xx;\n+\tstruct cvmx_sli_pkt_cnt_int_cn61xx cn63xxp1;\n+\tstruct cvmx_sli_pkt_cnt_int_cn61xx cn66xx;\n+\tstruct cvmx_sli_pkt_cnt_int_cn61xx cn68xx;\n+\tstruct cvmx_sli_pkt_cnt_int_cn61xx cn68xxp1;\n+\tstruct cvmx_sli_pkt_cnt_int_cn61xx cn70xx;\n+\tstruct cvmx_sli_pkt_cnt_int_cn61xx cn70xxp1;\n+\tstruct cvmx_sli_pkt_cnt_int_cn73xx {\n+\t\tu64 ring : 64;\n+\t} cn73xx;\n+\tstruct cvmx_sli_pkt_cnt_int_cn73xx cn78xx;\n+\tstruct cvmx_sli_pkt_cnt_int_cn73xx cn78xxp1;\n+\tstruct cvmx_sli_pkt_cnt_int_cn61xx cnf71xx;\n+\tstruct cvmx_sli_pkt_cnt_int_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_cnt_int cvmx_sli_pkt_cnt_int_t;\n+\n+/**\n+ * cvmx_sli_pkt_cnt_int_enb\n+ *\n+ * Enable for the packets rings that are interrupting because of Packet Counters.\n+ *\n+ */\n+union cvmx_sli_pkt_cnt_int_enb {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_cnt_int_enb_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 port : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_cnt_int_enb_s cn61xx;\n+\tstruct cvmx_sli_pkt_cnt_int_enb_s cn63xx;\n+\tstruct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_cnt_int_enb_s cn66xx;\n+\tstruct cvmx_sli_pkt_cnt_int_enb_s cn68xx;\n+\tstruct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_cnt_int_enb_s cn70xx;\n+\tstruct cvmx_sli_pkt_cnt_int_enb_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_cnt_int_enb_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_cnt_int_enb cvmx_sli_pkt_cnt_int_enb_t;\n+\n+/**\n+ * cvmx_sli_pkt_ctl\n+ *\n+ * Control for packets.\n+ *\n+ */\n+union cvmx_sli_pkt_ctl {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_ctl_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 ring_en : 1;\n+\t\tu64 pkt_bp : 4;\n+\t} s;\n+\tstruct cvmx_sli_pkt_ctl_s cn61xx;\n+\tstruct cvmx_sli_pkt_ctl_s cn63xx;\n+\tstruct cvmx_sli_pkt_ctl_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_ctl_s cn66xx;\n+\tstruct cvmx_sli_pkt_ctl_s cn68xx;\n+\tstruct cvmx_sli_pkt_ctl_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_ctl_s cn70xx;\n+\tstruct cvmx_sli_pkt_ctl_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_ctl cvmx_sli_pkt_ctl_t;\n+\n+/**\n+ * cvmx_sli_pkt_data_out_es\n+ *\n+ * The Endian Swap for writing Data Out.\n+ *\n+ */\n+union cvmx_sli_pkt_data_out_es {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_data_out_es_s {\n+\t\tu64 es : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_data_out_es_s cn61xx;\n+\tstruct cvmx_sli_pkt_data_out_es_s cn63xx;\n+\tstruct cvmx_sli_pkt_data_out_es_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_data_out_es_s cn66xx;\n+\tstruct cvmx_sli_pkt_data_out_es_s cn68xx;\n+\tstruct cvmx_sli_pkt_data_out_es_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_data_out_es_s cn70xx;\n+\tstruct cvmx_sli_pkt_data_out_es_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_data_out_es_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_data_out_es cvmx_sli_pkt_data_out_es_t;\n+\n+/**\n+ * cvmx_sli_pkt_data_out_ns\n+ *\n+ * The NS field for the TLP when writing packet data.\n+ *\n+ */\n+union cvmx_sli_pkt_data_out_ns {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_data_out_ns_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 nsr : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_data_out_ns_s cn61xx;\n+\tstruct cvmx_sli_pkt_data_out_ns_s cn63xx;\n+\tstruct cvmx_sli_pkt_data_out_ns_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_data_out_ns_s cn66xx;\n+\tstruct cvmx_sli_pkt_data_out_ns_s cn68xx;\n+\tstruct cvmx_sli_pkt_data_out_ns_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_data_out_ns_s cn70xx;\n+\tstruct cvmx_sli_pkt_data_out_ns_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_data_out_ns_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_data_out_ns cvmx_sli_pkt_data_out_ns_t;\n+\n+/**\n+ * cvmx_sli_pkt_data_out_ror\n+ *\n+ * The ROR field for the TLP when writing Packet Data.\n+ *\n+ */\n+union cvmx_sli_pkt_data_out_ror {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_data_out_ror_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 ror : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_data_out_ror_s cn61xx;\n+\tstruct cvmx_sli_pkt_data_out_ror_s cn63xx;\n+\tstruct cvmx_sli_pkt_data_out_ror_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_data_out_ror_s cn66xx;\n+\tstruct cvmx_sli_pkt_data_out_ror_s cn68xx;\n+\tstruct cvmx_sli_pkt_data_out_ror_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_data_out_ror_s cn70xx;\n+\tstruct cvmx_sli_pkt_data_out_ror_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_data_out_ror_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_data_out_ror cvmx_sli_pkt_data_out_ror_t;\n+\n+/**\n+ * cvmx_sli_pkt_dpaddr\n+ *\n+ * Used to detemine address and attributes for packet data writes.\n+ *\n+ */\n+union cvmx_sli_pkt_dpaddr {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_dpaddr_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 dptr : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_dpaddr_s cn61xx;\n+\tstruct cvmx_sli_pkt_dpaddr_s cn63xx;\n+\tstruct cvmx_sli_pkt_dpaddr_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_dpaddr_s cn66xx;\n+\tstruct cvmx_sli_pkt_dpaddr_s cn68xx;\n+\tstruct cvmx_sli_pkt_dpaddr_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_dpaddr_s cn70xx;\n+\tstruct cvmx_sli_pkt_dpaddr_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_dpaddr_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_dpaddr cvmx_sli_pkt_dpaddr_t;\n+\n+/**\n+ * cvmx_sli_pkt_gbl_control\n+ *\n+ * This register contains control bits that affect all packet rings.\n+ *\n+ */\n+union cvmx_sli_pkt_gbl_control {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_gbl_control_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 qtime : 16;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 bpkind : 6;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 pkpfval : 1;\n+\t\tu64 bpflr_d : 1;\n+\t\tu64 noptr_d : 1;\n+\t\tu64 picnt_d : 1;\n+\t} s;\n+\tstruct cvmx_sli_pkt_gbl_control_s cn73xx;\n+\tstruct cvmx_sli_pkt_gbl_control_s cn78xx;\n+\tstruct cvmx_sli_pkt_gbl_control_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_gbl_control cvmx_sli_pkt_gbl_control_t;\n+\n+/**\n+ * cvmx_sli_pkt_in_bp\n+ *\n+ * Which input rings have backpressure applied.\n+ *\n+ */\n+union cvmx_sli_pkt_in_bp {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_in_bp_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 bp : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_in_bp_s cn61xx;\n+\tstruct cvmx_sli_pkt_in_bp_s cn63xx;\n+\tstruct cvmx_sli_pkt_in_bp_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_in_bp_s cn66xx;\n+\tstruct cvmx_sli_pkt_in_bp_s cn70xx;\n+\tstruct cvmx_sli_pkt_in_bp_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_in_bp_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_in_bp cvmx_sli_pkt_in_bp_t;\n+\n+/**\n+ * cvmx_sli_pkt_in_done#_cnts\n+ *\n+ * This register contains counters for instructions completed on input rings.\n+ *\n+ */\n+union cvmx_sli_pkt_in_donex_cnts {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_s {\n+\t\tu64 po_int : 1;\n+\t\tu64 pi_int : 1;\n+\t\tu64 mbox_int : 1;\n+\t\tu64 resend : 1;\n+\t\tu64 reserved_49_59 : 11;\n+\t\tu64 cint_enb : 1;\n+\t\tu64 wmark : 16;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_cn61xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} cn61xx;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_cn61xx cn63xx;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_cn61xx cn63xxp1;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_cn61xx cn66xx;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_cn61xx cn68xx;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_cn61xx cn68xxp1;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_cn70xx {\n+\t\tu64 reserved_63_32 : 32;\n+\t\tu64 cnt : 32;\n+\t} cn70xx;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_cn70xx cn70xxp1;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_s cn73xx;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_s cn78xx;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_cn78xxp1 {\n+\t\tu64 po_int : 1;\n+\t\tu64 pi_int : 1;\n+\t\tu64 reserved_61_49 : 13;\n+\t\tu64 cint_enb : 1;\n+\t\tu64 wmark : 16;\n+\t\tu64 cnt : 32;\n+\t} cn78xxp1;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_cn61xx cnf71xx;\n+\tstruct cvmx_sli_pkt_in_donex_cnts_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_in_donex_cnts cvmx_sli_pkt_in_donex_cnts_t;\n+\n+/**\n+ * cvmx_sli_pkt_in_instr_counts\n+ *\n+ * This register contains keeps track of the number of instructions read into the FIFO and\n+ * packets sent to PKI. This register is PF-only.\n+ */\n+union cvmx_sli_pkt_in_instr_counts {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s {\n+\t\tu64 wr_cnt : 32;\n+\t\tu64 rd_cnt : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cn61xx;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cn63xx;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cn66xx;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cn68xx;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cn70xx;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cn73xx;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cn78xx;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cn78xxp1;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cnf71xx;\n+\tstruct cvmx_sli_pkt_in_instr_counts_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_in_instr_counts cvmx_sli_pkt_in_instr_counts_t;\n+\n+/**\n+ * cvmx_sli_pkt_in_int\n+ *\n+ * This register specifies which input packets rings are interrupting because of done counts.\n+ * A bit set in this interrupt register will set a corresponding bit in SLI_PKT_INT which\n+ * can cause a MSI-X interrupt.  When read by a function, this register informs which rings\n+ * owned by the function (0 to N, N as large as 63) have this interrupt pending.\n+ * SLI_PKT_IN_INT conditions can cause MSI-X interrupts, but do not cause any\n+ * SLI_MAC()_PF()_INT_SUM\n+ * bit to set, and cannot cause INTA/B/C/D nor MSI interrupts.\n+ */\n+union cvmx_sli_pkt_in_int {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_in_int_s {\n+\t\tu64 ring : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_in_int_s cn73xx;\n+\tstruct cvmx_sli_pkt_in_int_s cn78xx;\n+\tstruct cvmx_sli_pkt_in_int_s cn78xxp1;\n+\tstruct cvmx_sli_pkt_in_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_in_int cvmx_sli_pkt_in_int_t;\n+\n+/**\n+ * cvmx_sli_pkt_in_jabber\n+ *\n+ * Register to set limit on SLI packet input packet sizes.\n+ *\n+ */\n+union cvmx_sli_pkt_in_jabber {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_in_jabber_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 size : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_in_jabber_s cn73xx;\n+\tstruct cvmx_sli_pkt_in_jabber_s cn78xx;\n+\tstruct cvmx_sli_pkt_in_jabber_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_in_jabber cvmx_sli_pkt_in_jabber_t;\n+\n+/**\n+ * cvmx_sli_pkt_in_pcie_port\n+ *\n+ * Assigns Packet Input rings to MAC ports.\n+ *\n+ */\n+union cvmx_sli_pkt_in_pcie_port {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_in_pcie_port_s {\n+\t\tu64 pp : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_in_pcie_port_s cn61xx;\n+\tstruct cvmx_sli_pkt_in_pcie_port_s cn63xx;\n+\tstruct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_in_pcie_port_s cn66xx;\n+\tstruct cvmx_sli_pkt_in_pcie_port_s cn68xx;\n+\tstruct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_in_pcie_port_s cn70xx;\n+\tstruct cvmx_sli_pkt_in_pcie_port_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_in_pcie_port_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_in_pcie_port cvmx_sli_pkt_in_pcie_port_t;\n+\n+/**\n+ * cvmx_sli_pkt_input_control\n+ *\n+ * Control for reads for gather list and instructions.\n+ *\n+ */\n+union cvmx_sli_pkt_input_control {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_input_control_s {\n+\t\tu64 prd_erst : 1;\n+\t\tu64 prd_rds : 7;\n+\t\tu64 gii_erst : 1;\n+\t\tu64 gii_rds : 7;\n+\t\tu64 reserved_41_47 : 7;\n+\t\tu64 prc_idle : 1;\n+\t\tu64 reserved_24_39 : 16;\n+\t\tu64 pin_rst : 1;\n+\t\tu64 pkt_rr : 1;\n+\t\tu64 pbp_dhi : 13;\n+\t\tu64 d_nsr : 1;\n+\t\tu64 d_esr : 2;\n+\t\tu64 d_ror : 1;\n+\t\tu64 use_csr : 1;\n+\t\tu64 nsr : 1;\n+\t\tu64 esr : 2;\n+\t\tu64 ror : 1;\n+\t} s;\n+\tstruct cvmx_sli_pkt_input_control_s cn61xx;\n+\tstruct cvmx_sli_pkt_input_control_cn63xx {\n+\t\tu64 reserved_23_63 : 41;\n+\t\tu64 pkt_rr : 1;\n+\t\tu64 pbp_dhi : 13;\n+\t\tu64 d_nsr : 1;\n+\t\tu64 d_esr : 2;\n+\t\tu64 d_ror : 1;\n+\t\tu64 use_csr : 1;\n+\t\tu64 nsr : 1;\n+\t\tu64 esr : 2;\n+\t\tu64 ror : 1;\n+\t} cn63xx;\n+\tstruct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;\n+\tstruct cvmx_sli_pkt_input_control_s cn66xx;\n+\tstruct cvmx_sli_pkt_input_control_s cn68xx;\n+\tstruct cvmx_sli_pkt_input_control_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_input_control_s cn70xx;\n+\tstruct cvmx_sli_pkt_input_control_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_input_control_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_input_control cvmx_sli_pkt_input_control_t;\n+\n+/**\n+ * cvmx_sli_pkt_instr_enb\n+ *\n+ * Multi-ring instruction input enable register. This register is PF-only.\n+ *\n+ */\n+union cvmx_sli_pkt_instr_enb {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_instr_enb_s {\n+\t\tu64 enb : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_instr_enb_cn61xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 enb : 32;\n+\t} cn61xx;\n+\tstruct cvmx_sli_pkt_instr_enb_cn61xx cn63xx;\n+\tstruct cvmx_sli_pkt_instr_enb_cn61xx cn63xxp1;\n+\tstruct cvmx_sli_pkt_instr_enb_cn61xx cn66xx;\n+\tstruct cvmx_sli_pkt_instr_enb_cn61xx cn68xx;\n+\tstruct cvmx_sli_pkt_instr_enb_cn61xx cn68xxp1;\n+\tstruct cvmx_sli_pkt_instr_enb_cn61xx cn70xx;\n+\tstruct cvmx_sli_pkt_instr_enb_cn61xx cn70xxp1;\n+\tstruct cvmx_sli_pkt_instr_enb_s cn78xxp1;\n+\tstruct cvmx_sli_pkt_instr_enb_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_instr_enb cvmx_sli_pkt_instr_enb_t;\n+\n+/**\n+ * cvmx_sli_pkt_instr_rd_size\n+ *\n+ * The number of instruction allowed to be read at one time.\n+ *\n+ */\n+union cvmx_sli_pkt_instr_rd_size {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_instr_rd_size_s {\n+\t\tu64 rdsize : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_instr_rd_size_s cn61xx;\n+\tstruct cvmx_sli_pkt_instr_rd_size_s cn63xx;\n+\tstruct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_instr_rd_size_s cn66xx;\n+\tstruct cvmx_sli_pkt_instr_rd_size_s cn68xx;\n+\tstruct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_instr_rd_size_s cn70xx;\n+\tstruct cvmx_sli_pkt_instr_rd_size_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_instr_rd_size_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_instr_rd_size cvmx_sli_pkt_instr_rd_size_t;\n+\n+/**\n+ * cvmx_sli_pkt_instr_size\n+ *\n+ * Determines if instructions are 64 or 32 byte in size for a Packet-ring.\n+ *\n+ */\n+union cvmx_sli_pkt_instr_size {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_instr_size_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 is_64b : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_instr_size_s cn61xx;\n+\tstruct cvmx_sli_pkt_instr_size_s cn63xx;\n+\tstruct cvmx_sli_pkt_instr_size_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_instr_size_s cn66xx;\n+\tstruct cvmx_sli_pkt_instr_size_s cn68xx;\n+\tstruct cvmx_sli_pkt_instr_size_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_instr_size_s cn70xx;\n+\tstruct cvmx_sli_pkt_instr_size_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_instr_size_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_instr_size cvmx_sli_pkt_instr_size_t;\n+\n+/**\n+ * cvmx_sli_pkt_int\n+ *\n+ * This register combines the SLI_PKT_CNT_INT, SLI_PKT_TIME_INT or SLI_PKT_IN_INT interrupt\n+ * registers. When read by a function, this register informs which rings owned by the function\n+ * (0 to N, N as large as 63) have an interrupt pending.\n+ */\n+union cvmx_sli_pkt_int {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_int_s {\n+\t\tu64 ring : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_int_s cn73xx;\n+\tstruct cvmx_sli_pkt_int_s cn78xx;\n+\tstruct cvmx_sli_pkt_int_s cn78xxp1;\n+\tstruct cvmx_sli_pkt_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_int cvmx_sli_pkt_int_t;\n+\n+/**\n+ * cvmx_sli_pkt_int_levels\n+ *\n+ * SLI_PKT_INT_LEVELS = SLI's Packet Interrupt Levels\n+ * Output packet interrupt levels.\n+ */\n+union cvmx_sli_pkt_int_levels {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_int_levels_s {\n+\t\tu64 reserved_54_63 : 10;\n+\t\tu64 time : 22;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_int_levels_s cn61xx;\n+\tstruct cvmx_sli_pkt_int_levels_s cn63xx;\n+\tstruct cvmx_sli_pkt_int_levels_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_int_levels_s cn66xx;\n+\tstruct cvmx_sli_pkt_int_levels_s cn68xx;\n+\tstruct cvmx_sli_pkt_int_levels_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_int_levels_s cn70xx;\n+\tstruct cvmx_sli_pkt_int_levels_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_int_levels_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_int_levels cvmx_sli_pkt_int_levels_t;\n+\n+/**\n+ * cvmx_sli_pkt_iptr\n+ *\n+ * Controls using the Info-Pointer to store length and data.\n+ *\n+ */\n+union cvmx_sli_pkt_iptr {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_iptr_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 iptr : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_iptr_s cn61xx;\n+\tstruct cvmx_sli_pkt_iptr_s cn63xx;\n+\tstruct cvmx_sli_pkt_iptr_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_iptr_s cn66xx;\n+\tstruct cvmx_sli_pkt_iptr_s cn68xx;\n+\tstruct cvmx_sli_pkt_iptr_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_iptr_s cn70xx;\n+\tstruct cvmx_sli_pkt_iptr_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_iptr_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_iptr cvmx_sli_pkt_iptr_t;\n+\n+/**\n+ * cvmx_sli_pkt_mac#_pf#_rinfo\n+ *\n+ * This register sets the total number and starting number of rings for a given MAC and PF\n+ * combination. Indexed by (MAC index) SLI_PORT_E. In SR-IOV mode, SLI_PKT_MAC()_PF()_RINFO[RPVF]\n+ * and SLI_PKT_MAC()_PF()_RINFO[NVFS] must be non zero and determine which rings the PFs and\n+ * VFs own.\n+ *\n+ * An individual VF will own SLI_PKT_MAC()_PF()_RINFO[RPVF] number of rings.\n+ *\n+ * A PF will own the rings starting from ((SLI_PKT_MAC()_PF()_RINFO[SRN] +\n+ * (SLI_PKT_MAC()_PF()_RINFO[RPVF] * SLI_PKT_MAC()_PF()_RINFO[NVFS]))\n+ * to (SLI_PKT_MAC()_PF()_RINFO[SRN] + (SLI_PKT_MAC()_PF()_RINFO[TRS] -\n+ * 1)). SLI_PKT()_INPUT_CONTROL[PVF_NUM] must be written to values that\n+ * correlate with the fields in this register.\n+ *\n+ * e.g. Given:\n+ * _ SLI_PKT_MAC0_PF0_RINFO[SRN] = 32,\n+ * _ SLI_PKT_MAC0_PF0_RINFO[TRS] = 32,\n+ * _ SLI_PKT_MAC0_PF0_RINFO[RPVF] = 4,\n+ * _ SLI_PKT_MAC0_PF0_RINFO[NVFS] = 7:\n+ * _ rings owned by VF1: 32,33,34,35\n+ * _ rings owned by VF2: 36,37,38,39\n+ * _ rings owned by VF3: 40,41,42,43\n+ * _ rings owned by VF4: 44,45,46,47\n+ * _ rings owned by VF5: 48,49,50,51\n+ * _ rings owned by VF6: 52,53,54,55\n+ * _ rings owned by VF7: 56,57,58,59\n+ * _ rings owned by PF:  60,61,62,63\n+ */\n+union cvmx_sli_pkt_macx_pfx_rinfo {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_macx_pfx_rinfo_s {\n+\t\tu64 reserved_55_63 : 9;\n+\t\tu64 nvfs : 7;\n+\t\tu64 reserved_40_47 : 8;\n+\t\tu64 rpvf : 8;\n+\t\tu64 reserved_24_31 : 8;\n+\t\tu64 trs : 8;\n+\t\tu64 reserved_7_15 : 9;\n+\t\tu64 srn : 7;\n+\t} s;\n+\tstruct cvmx_sli_pkt_macx_pfx_rinfo_s cn73xx;\n+\tstruct cvmx_sli_pkt_macx_pfx_rinfo_s cn78xx;\n+\tstruct cvmx_sli_pkt_macx_pfx_rinfo_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_macx_pfx_rinfo cvmx_sli_pkt_macx_pfx_rinfo_t;\n+\n+/**\n+ * cvmx_sli_pkt_mac#_rinfo\n+ *\n+ * This register sets the total number and starting number of rings used by the MAC.\n+ * This register is PF-only.\n+ */\n+union cvmx_sli_pkt_macx_rinfo {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_macx_rinfo_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 rpvf : 8;\n+\t\tu64 reserved_24_31 : 8;\n+\t\tu64 trs : 8;\n+\t\tu64 reserved_7_15 : 9;\n+\t\tu64 srn : 7;\n+\t} s;\n+\tstruct cvmx_sli_pkt_macx_rinfo_s cn78xxp1;\n+};\n+\n+typedef union cvmx_sli_pkt_macx_rinfo cvmx_sli_pkt_macx_rinfo_t;\n+\n+/**\n+ * cvmx_sli_pkt_mac0_sig0\n+ *\n+ * This register is used to signal between PF/VF. This register can be R/W by the PF from MAC0\n+ * and any VF.\n+ */\n+union cvmx_sli_pkt_mac0_sig0 {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_mac0_sig0_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_mac0_sig0_s cn78xxp1;\n+};\n+\n+typedef union cvmx_sli_pkt_mac0_sig0 cvmx_sli_pkt_mac0_sig0_t;\n+\n+/**\n+ * cvmx_sli_pkt_mac0_sig1\n+ *\n+ * This register is used to signal between PF/VF. This register can be R/W by the PF from MAC0\n+ * and any VF.\n+ */\n+union cvmx_sli_pkt_mac0_sig1 {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_mac0_sig1_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_mac0_sig1_s cn78xxp1;\n+};\n+\n+typedef union cvmx_sli_pkt_mac0_sig1 cvmx_sli_pkt_mac0_sig1_t;\n+\n+/**\n+ * cvmx_sli_pkt_mac1_sig0\n+ *\n+ * This register is used to signal between PF/VF. This register can be R/W by the PF from MAC1\n+ * and any VF.\n+ */\n+union cvmx_sli_pkt_mac1_sig0 {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_mac1_sig0_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_mac1_sig0_s cn78xxp1;\n+};\n+\n+typedef union cvmx_sli_pkt_mac1_sig0 cvmx_sli_pkt_mac1_sig0_t;\n+\n+/**\n+ * cvmx_sli_pkt_mac1_sig1\n+ *\n+ * This register is used to signal between PF/VF. This register can be R/W by the PF from MAC1\n+ * and any VF.\n+ */\n+union cvmx_sli_pkt_mac1_sig1 {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_mac1_sig1_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_mac1_sig1_s cn78xxp1;\n+};\n+\n+typedef union cvmx_sli_pkt_mac1_sig1 cvmx_sli_pkt_mac1_sig1_t;\n+\n+/**\n+ * cvmx_sli_pkt_mem_ctl\n+ *\n+ * This register controls the ECC of the SLI packet memories.\n+ *\n+ */\n+union cvmx_sli_pkt_mem_ctl {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_mem_ctl_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 msix_mbox_fs : 2;\n+\t\tu64 msix_mbox_ecc : 1;\n+\t\tu64 reserved_36_44 : 9;\n+\t\tu64 pos_fs : 2;\n+\t\tu64 pos_ecc : 1;\n+\t\tu64 pinm_fs : 2;\n+\t\tu64 pinm_ecc : 1;\n+\t\tu64 pind_fs : 2;\n+\t\tu64 pind_ecc : 1;\n+\t\tu64 point_fs : 2;\n+\t\tu64 point_ecc : 1;\n+\t\tu64 slist_fs : 2;\n+\t\tu64 slist_ecc : 1;\n+\t\tu64 pop1_fs : 2;\n+\t\tu64 pop1_ecc : 1;\n+\t\tu64 pop0_fs : 2;\n+\t\tu64 pop0_ecc : 1;\n+\t\tu64 pfp_fs : 2;\n+\t\tu64 pfp_ecc : 1;\n+\t\tu64 pbn_fs : 2;\n+\t\tu64 pbn_ecc : 1;\n+\t\tu64 pdf_fs : 2;\n+\t\tu64 pdf_ecc : 1;\n+\t\tu64 psf_fs : 2;\n+\t\tu64 psf_ecc : 1;\n+\t\tu64 poi_fs : 2;\n+\t\tu64 poi_ecc : 1;\n+\t} s;\n+\tstruct cvmx_sli_pkt_mem_ctl_cn73xx {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 msix_mbox_fs : 2;\n+\t\tu64 msix_mbox_ecc : 1;\n+\t\tu64 msix_data_fs : 2;\n+\t\tu64 msix_data_ecc : 1;\n+\t\tu64 msix_addr_fs : 2;\n+\t\tu64 msix_addr_ecc : 1;\n+\t\tu64 pof_fs : 2;\n+\t\tu64 pof_ecc : 1;\n+\t\tu64 pos_fs : 2;\n+\t\tu64 pos_ecc : 1;\n+\t\tu64 pinm_fs : 2;\n+\t\tu64 pinm_ecc : 1;\n+\t\tu64 pind_fs : 2;\n+\t\tu64 pind_ecc : 1;\n+\t\tu64 point_fs : 2;\n+\t\tu64 point_ecc : 1;\n+\t\tu64 slist_fs : 2;\n+\t\tu64 slist_ecc : 1;\n+\t\tu64 pop1_fs : 2;\n+\t\tu64 pop1_ecc : 1;\n+\t\tu64 pop0_fs : 2;\n+\t\tu64 pop0_ecc : 1;\n+\t\tu64 pfp_fs : 2;\n+\t\tu64 pfp_ecc : 1;\n+\t\tu64 pbn_fs : 2;\n+\t\tu64 pbn_ecc : 1;\n+\t\tu64 pdf_fs : 2;\n+\t\tu64 pdf_ecc : 1;\n+\t\tu64 psf_fs : 2;\n+\t\tu64 psf_ecc : 1;\n+\t\tu64 poi_fs : 2;\n+\t\tu64 poi_ecc : 1;\n+\t} cn73xx;\n+\tstruct cvmx_sli_pkt_mem_ctl_cn73xx cn78xx;\n+\tstruct cvmx_sli_pkt_mem_ctl_cn78xxp1 {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 msid_fs : 2;\n+\t\tu64 msia_fs : 2;\n+\t\tu64 msi_ecc : 1;\n+\t\tu64 posi_fs : 2;\n+\t\tu64 posi_ecc : 1;\n+\t\tu64 pos_fs : 2;\n+\t\tu64 pos_ecc : 1;\n+\t\tu64 pinm_fs : 2;\n+\t\tu64 pinm_ecc : 1;\n+\t\tu64 pind_fs : 2;\n+\t\tu64 pind_ecc : 1;\n+\t\tu64 point_fs : 2;\n+\t\tu64 point_ecc : 1;\n+\t\tu64 slist_fs : 2;\n+\t\tu64 slist_ecc : 1;\n+\t\tu64 pop1_fs : 2;\n+\t\tu64 pop1_ecc : 1;\n+\t\tu64 pop0_fs : 2;\n+\t\tu64 pop0_ecc : 1;\n+\t\tu64 pfp_fs : 2;\n+\t\tu64 pfp_ecc : 1;\n+\t\tu64 pbn_fs : 2;\n+\t\tu64 pbn_ecc : 1;\n+\t\tu64 pdf_fs : 2;\n+\t\tu64 pdf_ecc : 1;\n+\t\tu64 psf_fs : 2;\n+\t\tu64 psf_ecc : 1;\n+\t\tu64 poi_fs : 2;\n+\t\tu64 poi_ecc : 1;\n+\t} cn78xxp1;\n+\tstruct cvmx_sli_pkt_mem_ctl_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_mem_ctl cvmx_sli_pkt_mem_ctl_t;\n+\n+/**\n+ * cvmx_sli_pkt_out_bmode\n+ *\n+ * Control the updating of the SLI_PKT#_CNT register.\n+ *\n+ */\n+union cvmx_sli_pkt_out_bmode {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_out_bmode_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 bmode : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_out_bmode_s cn61xx;\n+\tstruct cvmx_sli_pkt_out_bmode_s cn63xx;\n+\tstruct cvmx_sli_pkt_out_bmode_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_out_bmode_s cn66xx;\n+\tstruct cvmx_sli_pkt_out_bmode_s cn68xx;\n+\tstruct cvmx_sli_pkt_out_bmode_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_out_bmode_s cn70xx;\n+\tstruct cvmx_sli_pkt_out_bmode_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_out_bmode_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_out_bmode cvmx_sli_pkt_out_bmode_t;\n+\n+/**\n+ * cvmx_sli_pkt_out_bp_en\n+ *\n+ * This register enables sending backpressure to PKO.\n+ *\n+ */\n+union cvmx_sli_pkt_out_bp_en {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_out_bp_en_s {\n+\t\tu64 bp_en : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_out_bp_en_cn68xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 bp_en : 32;\n+\t} cn68xx;\n+\tstruct cvmx_sli_pkt_out_bp_en_cn68xx cn68xxp1;\n+\tstruct cvmx_sli_pkt_out_bp_en_s cn78xxp1;\n+};\n+\n+typedef union cvmx_sli_pkt_out_bp_en cvmx_sli_pkt_out_bp_en_t;\n+\n+/**\n+ * cvmx_sli_pkt_out_bp_en2_w1c\n+ *\n+ * This register disables sending backpressure to PKO.\n+ *\n+ */\n+union cvmx_sli_pkt_out_bp_en2_w1c {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_out_bp_en2_w1c_s {\n+\t\tu64 w1c : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_out_bp_en2_w1c_s cn73xx;\n+};\n+\n+typedef union cvmx_sli_pkt_out_bp_en2_w1c cvmx_sli_pkt_out_bp_en2_w1c_t;\n+\n+/**\n+ * cvmx_sli_pkt_out_bp_en2_w1s\n+ *\n+ * This register enables sending backpressure to PKO.\n+ *\n+ */\n+union cvmx_sli_pkt_out_bp_en2_w1s {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_out_bp_en2_w1s_s {\n+\t\tu64 w1s : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_out_bp_en2_w1s_s cn73xx;\n+};\n+\n+typedef union cvmx_sli_pkt_out_bp_en2_w1s cvmx_sli_pkt_out_bp_en2_w1s_t;\n+\n+/**\n+ * cvmx_sli_pkt_out_bp_en_w1c\n+ *\n+ * This register disables sending backpressure to PKO.\n+ *\n+ */\n+union cvmx_sli_pkt_out_bp_en_w1c {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_out_bp_en_w1c_s {\n+\t\tu64 w1c : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_out_bp_en_w1c_s cn73xx;\n+\tstruct cvmx_sli_pkt_out_bp_en_w1c_s cn78xx;\n+\tstruct cvmx_sli_pkt_out_bp_en_w1c_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_out_bp_en_w1c cvmx_sli_pkt_out_bp_en_w1c_t;\n+\n+/**\n+ * cvmx_sli_pkt_out_bp_en_w1s\n+ *\n+ * This register enables sending backpressure to PKO.\n+ *\n+ */\n+union cvmx_sli_pkt_out_bp_en_w1s {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_out_bp_en_w1s_s {\n+\t\tu64 w1s : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_out_bp_en_w1s_s cn73xx;\n+\tstruct cvmx_sli_pkt_out_bp_en_w1s_s cn78xx;\n+\tstruct cvmx_sli_pkt_out_bp_en_w1s_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_out_bp_en_w1s cvmx_sli_pkt_out_bp_en_w1s_t;\n+\n+/**\n+ * cvmx_sli_pkt_out_enb\n+ *\n+ * Multi-ring packet output enable register. This register is PF-only.\n+ *\n+ */\n+union cvmx_sli_pkt_out_enb {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_out_enb_s {\n+\t\tu64 enb : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_out_enb_cn61xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 enb : 32;\n+\t} cn61xx;\n+\tstruct cvmx_sli_pkt_out_enb_cn61xx cn63xx;\n+\tstruct cvmx_sli_pkt_out_enb_cn61xx cn63xxp1;\n+\tstruct cvmx_sli_pkt_out_enb_cn61xx cn66xx;\n+\tstruct cvmx_sli_pkt_out_enb_cn61xx cn68xx;\n+\tstruct cvmx_sli_pkt_out_enb_cn61xx cn68xxp1;\n+\tstruct cvmx_sli_pkt_out_enb_cn61xx cn70xx;\n+\tstruct cvmx_sli_pkt_out_enb_cn61xx cn70xxp1;\n+\tstruct cvmx_sli_pkt_out_enb_s cn78xxp1;\n+\tstruct cvmx_sli_pkt_out_enb_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_out_enb cvmx_sli_pkt_out_enb_t;\n+\n+/**\n+ * cvmx_sli_pkt_output_wmark\n+ *\n+ * This register sets the value that determines when backpressure is applied to the PKO. When\n+ * SLI_PKT()_SLIST_BAOFF_DBELL[DBELL] is less than [WMARK], backpressure is sent to PKO for\n+ * the associated channel. This register is PF-only.\n+ */\n+union cvmx_sli_pkt_output_wmark {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_output_wmark_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 wmark : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_output_wmark_s cn61xx;\n+\tstruct cvmx_sli_pkt_output_wmark_s cn63xx;\n+\tstruct cvmx_sli_pkt_output_wmark_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_output_wmark_s cn66xx;\n+\tstruct cvmx_sli_pkt_output_wmark_s cn68xx;\n+\tstruct cvmx_sli_pkt_output_wmark_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_output_wmark_s cn70xx;\n+\tstruct cvmx_sli_pkt_output_wmark_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_output_wmark_s cn73xx;\n+\tstruct cvmx_sli_pkt_output_wmark_s cn78xx;\n+\tstruct cvmx_sli_pkt_output_wmark_s cn78xxp1;\n+\tstruct cvmx_sli_pkt_output_wmark_s cnf71xx;\n+\tstruct cvmx_sli_pkt_output_wmark_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_output_wmark cvmx_sli_pkt_output_wmark_t;\n+\n+/**\n+ * cvmx_sli_pkt_pcie_port\n+ *\n+ * Assigns Packet Ports to MAC ports.\n+ *\n+ */\n+union cvmx_sli_pkt_pcie_port {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_pcie_port_s {\n+\t\tu64 pp : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_pcie_port_s cn61xx;\n+\tstruct cvmx_sli_pkt_pcie_port_s cn63xx;\n+\tstruct cvmx_sli_pkt_pcie_port_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_pcie_port_s cn66xx;\n+\tstruct cvmx_sli_pkt_pcie_port_s cn68xx;\n+\tstruct cvmx_sli_pkt_pcie_port_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_pcie_port_s cn70xx;\n+\tstruct cvmx_sli_pkt_pcie_port_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_pcie_port_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_pcie_port cvmx_sli_pkt_pcie_port_t;\n+\n+/**\n+ * cvmx_sli_pkt_pkind_valid\n+ *\n+ * Enables bits per PKIND that are allowed to be sent to PKI specified in the\n+ * DPI_PKT_INST_HDR_S[PKIND] DPI packet instruction field.\n+ */\n+union cvmx_sli_pkt_pkind_valid {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_pkind_valid_s {\n+\t\tu64 enb : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_pkind_valid_s cn73xx;\n+\tstruct cvmx_sli_pkt_pkind_valid_s cn78xx;\n+\tstruct cvmx_sli_pkt_pkind_valid_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_pkind_valid cvmx_sli_pkt_pkind_valid_t;\n+\n+/**\n+ * cvmx_sli_pkt_port_in_rst\n+ *\n+ * SLI_PKT_PORT_IN_RST = SLI Packet Port In Reset\n+ * Vector bits related to ring-port for ones that are reset.\n+ */\n+union cvmx_sli_pkt_port_in_rst {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_port_in_rst_s {\n+\t\tu64 in_rst : 32;\n+\t\tu64 out_rst : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_port_in_rst_s cn61xx;\n+\tstruct cvmx_sli_pkt_port_in_rst_s cn63xx;\n+\tstruct cvmx_sli_pkt_port_in_rst_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_port_in_rst_s cn66xx;\n+\tstruct cvmx_sli_pkt_port_in_rst_s cn68xx;\n+\tstruct cvmx_sli_pkt_port_in_rst_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_port_in_rst_s cn70xx;\n+\tstruct cvmx_sli_pkt_port_in_rst_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_port_in_rst_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_port_in_rst cvmx_sli_pkt_port_in_rst_t;\n+\n+/**\n+ * cvmx_sli_pkt_ring_rst\n+ *\n+ * When read by a PF, this register informs which rings owned by the function (0 to N, N as large\n+ * as 63) are in reset. See also SLI_PKT()_INPUT_CONTROL[RST].\n+ */\n+union cvmx_sli_pkt_ring_rst {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_ring_rst_s {\n+\t\tu64 rst : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_ring_rst_s cn73xx;\n+\tstruct cvmx_sli_pkt_ring_rst_s cn78xx;\n+\tstruct cvmx_sli_pkt_ring_rst_s cn78xxp1;\n+\tstruct cvmx_sli_pkt_ring_rst_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_ring_rst cvmx_sli_pkt_ring_rst_t;\n+\n+/**\n+ * cvmx_sli_pkt_slist_es\n+ *\n+ * The Endian Swap for Scatter List Read.\n+ *\n+ */\n+union cvmx_sli_pkt_slist_es {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_slist_es_s {\n+\t\tu64 es : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_slist_es_s cn61xx;\n+\tstruct cvmx_sli_pkt_slist_es_s cn63xx;\n+\tstruct cvmx_sli_pkt_slist_es_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_slist_es_s cn66xx;\n+\tstruct cvmx_sli_pkt_slist_es_s cn68xx;\n+\tstruct cvmx_sli_pkt_slist_es_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_slist_es_s cn70xx;\n+\tstruct cvmx_sli_pkt_slist_es_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_slist_es_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_slist_es cvmx_sli_pkt_slist_es_t;\n+\n+/**\n+ * cvmx_sli_pkt_slist_ns\n+ *\n+ * The NS field for the TLP when fetching Scatter List.\n+ *\n+ */\n+union cvmx_sli_pkt_slist_ns {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_slist_ns_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 nsr : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_slist_ns_s cn61xx;\n+\tstruct cvmx_sli_pkt_slist_ns_s cn63xx;\n+\tstruct cvmx_sli_pkt_slist_ns_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_slist_ns_s cn66xx;\n+\tstruct cvmx_sli_pkt_slist_ns_s cn68xx;\n+\tstruct cvmx_sli_pkt_slist_ns_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_slist_ns_s cn70xx;\n+\tstruct cvmx_sli_pkt_slist_ns_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_slist_ns_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_slist_ns cvmx_sli_pkt_slist_ns_t;\n+\n+/**\n+ * cvmx_sli_pkt_slist_ror\n+ *\n+ * The ROR field for the TLP when fetching Scatter List.\n+ *\n+ */\n+union cvmx_sli_pkt_slist_ror {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_slist_ror_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 ror : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_slist_ror_s cn61xx;\n+\tstruct cvmx_sli_pkt_slist_ror_s cn63xx;\n+\tstruct cvmx_sli_pkt_slist_ror_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_slist_ror_s cn66xx;\n+\tstruct cvmx_sli_pkt_slist_ror_s cn68xx;\n+\tstruct cvmx_sli_pkt_slist_ror_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_slist_ror_s cn70xx;\n+\tstruct cvmx_sli_pkt_slist_ror_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_slist_ror_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_slist_ror cvmx_sli_pkt_slist_ror_t;\n+\n+/**\n+ * cvmx_sli_pkt_time_int\n+ *\n+ * This register specifies which output packets rings are interrupting because of packet timers.\n+ * A bit set in this interrupt register will set a corresponding bit in SLI_PKT_INT and can\n+ * also cause SLI_MAC()_PF()_INT_SUM[PTIME] to be set if\n+ * SLI_PKT()_OUTPUT_CONTROL[TENB]\n+ * is set. When read by a function, this register informs which rings owned by the function (0 to\n+ * N,\n+ * N as large as 63) have this interrupt pending.\n+ */\n+union cvmx_sli_pkt_time_int {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_time_int_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_sli_pkt_time_int_cn61xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 port : 32;\n+\t} cn61xx;\n+\tstruct cvmx_sli_pkt_time_int_cn61xx cn63xx;\n+\tstruct cvmx_sli_pkt_time_int_cn61xx cn63xxp1;\n+\tstruct cvmx_sli_pkt_time_int_cn61xx cn66xx;\n+\tstruct cvmx_sli_pkt_time_int_cn61xx cn68xx;\n+\tstruct cvmx_sli_pkt_time_int_cn61xx cn68xxp1;\n+\tstruct cvmx_sli_pkt_time_int_cn61xx cn70xx;\n+\tstruct cvmx_sli_pkt_time_int_cn61xx cn70xxp1;\n+\tstruct cvmx_sli_pkt_time_int_cn73xx {\n+\t\tu64 ring : 64;\n+\t} cn73xx;\n+\tstruct cvmx_sli_pkt_time_int_cn73xx cn78xx;\n+\tstruct cvmx_sli_pkt_time_int_cn73xx cn78xxp1;\n+\tstruct cvmx_sli_pkt_time_int_cn61xx cnf71xx;\n+\tstruct cvmx_sli_pkt_time_int_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pkt_time_int cvmx_sli_pkt_time_int_t;\n+\n+/**\n+ * cvmx_sli_pkt_time_int_enb\n+ *\n+ * The packets rings that are interrupting because of Packet Timers.\n+ *\n+ */\n+union cvmx_sli_pkt_time_int_enb {\n+\tu64 u64;\n+\tstruct cvmx_sli_pkt_time_int_enb_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 port : 32;\n+\t} s;\n+\tstruct cvmx_sli_pkt_time_int_enb_s cn61xx;\n+\tstruct cvmx_sli_pkt_time_int_enb_s cn63xx;\n+\tstruct cvmx_sli_pkt_time_int_enb_s cn63xxp1;\n+\tstruct cvmx_sli_pkt_time_int_enb_s cn66xx;\n+\tstruct cvmx_sli_pkt_time_int_enb_s cn68xx;\n+\tstruct cvmx_sli_pkt_time_int_enb_s cn68xxp1;\n+\tstruct cvmx_sli_pkt_time_int_enb_s cn70xx;\n+\tstruct cvmx_sli_pkt_time_int_enb_s cn70xxp1;\n+\tstruct cvmx_sli_pkt_time_int_enb_s cnf71xx;\n+};\n+\n+typedef union cvmx_sli_pkt_time_int_enb cvmx_sli_pkt_time_int_enb_t;\n+\n+/**\n+ * cvmx_sli_port#_pkind\n+ *\n+ * SLI_PORT[0..31]_PKIND = SLI Port Pkind\n+ *\n+ * The SLI/DPI supports 32 input rings for fetching input packets. This register maps the input-rings (0-31) to a PKIND.\n+ */\n+union cvmx_sli_portx_pkind {\n+\tu64 u64;\n+\tstruct cvmx_sli_portx_pkind_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 rpk_enb : 1;\n+\t\tu64 reserved_22_23 : 2;\n+\t\tu64 pkindr : 6;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 bpkind : 6;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 pkind : 6;\n+\t} s;\n+\tstruct cvmx_sli_portx_pkind_s cn68xx;\n+\tstruct cvmx_sli_portx_pkind_cn68xxp1 {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 bpkind : 6;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 pkind : 6;\n+\t} cn68xxp1;\n+};\n+\n+typedef union cvmx_sli_portx_pkind cvmx_sli_portx_pkind_t;\n+\n+/**\n+ * cvmx_sli_pp_pkt_csr_control\n+ *\n+ * This register provides access to SLI packet register space from the cores.\n+ * These SLI packet registers include the following:\n+ *  SLI_MSIXX_TABLE_ADDR,\n+ *  SLI_MSIXX_TABLE_DATA,\n+ *  SLI_MSIX_PBA0,\n+ *  SLI_MSIX_PBA1,\n+ *  SLI_PKTX_INPUT_CONTROL,\n+ *  SLI_PKTX_INSTR_BADDR,\n+ *  SLI_PKTX_INSTR_BAOFF_DBELL,\n+ *  SLI_PKTX_INSTR_FIFO_RSIZE,\n+ *  SLI_PKT_IN_DONEX_CNTS,\n+ *  SLI_PKTX_OUTPUT_CONTROL,\n+ *  SLI_PKTX_OUT_SIZE,\n+ *  SLI_PKTX_SLIST_BADDR,\n+ *  SLI_PKTX_SLIST_BAOFF_DBELL,\n+ *  SLI_PKTX_SLIST_FIFO_RSIZE,\n+ *  SLI_PKTX_INT_LEVELS,\n+ *  SLI_PKTX_CNTS,\n+ *  SLI_PKTX_ERROR_INFO,\n+ *  SLI_PKTX_VF_INT_SUM,\n+ *  SLI_PKTX_PF_VF_MBOX_SIG,\n+ *  SLI_PKTX_MBOX_INT.\n+ */\n+union cvmx_sli_pp_pkt_csr_control {\n+\tu64 u64;\n+\tstruct cvmx_sli_pp_pkt_csr_control_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 mac : 2;\n+\t\tu64 pvf : 16;\n+\t} s;\n+\tstruct cvmx_sli_pp_pkt_csr_control_s cn73xx;\n+\tstruct cvmx_sli_pp_pkt_csr_control_s cn78xx;\n+\tstruct cvmx_sli_pp_pkt_csr_control_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_pp_pkt_csr_control cvmx_sli_pp_pkt_csr_control_t;\n+\n+/**\n+ * cvmx_sli_s2c_end_merge\n+ *\n+ * Writing this register will cause a merge to end.\n+ *\n+ */\n+union cvmx_sli_s2c_end_merge {\n+\tu64 u64;\n+\tstruct cvmx_sli_s2c_end_merge_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_sli_s2c_end_merge_s cn73xx;\n+\tstruct cvmx_sli_s2c_end_merge_s cn78xx;\n+\tstruct cvmx_sli_s2c_end_merge_s cn78xxp1;\n+\tstruct cvmx_sli_s2c_end_merge_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_s2c_end_merge cvmx_sli_s2c_end_merge_t;\n+\n+/**\n+ * cvmx_sli_s2m_port#_ctl\n+ *\n+ * These registers contain control for access from SLI to a MAC port. Indexed by SLI_PORT_E.\n+ * Write operations to these registers are not ordered with write/read operations to the MAC\n+ * memory space. To ensure that a write operation has completed, read the register before\n+ * making an access (i.e. MAC memory space) that requires the value of this register to be\n+ * updated.\n+ */\n+union cvmx_sli_s2m_portx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_sli_s2m_portx_ctl_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 dvferr : 1;\n+\t\tu64 lcl_node : 1;\n+\t\tu64 wind_d : 1;\n+\t\tu64 bar0_d : 1;\n+\t\tu64 reserved_0_2 : 3;\n+\t} s;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn61xx {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 wind_d : 1;\n+\t\tu64 bar0_d : 1;\n+\t\tu64 mrrs : 3;\n+\t} cn61xx;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn61xx cn63xx;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn61xx cn63xxp1;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn61xx cn66xx;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn61xx cn68xx;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn61xx cn68xxp1;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn61xx cn70xx;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn61xx cn70xxp1;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn73xx {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 dvferr : 1;\n+\t\tu64 lcl_node : 1;\n+\t\tu64 wind_d : 1;\n+\t\tu64 bar0_d : 1;\n+\t\tu64 ld_cmd : 2;\n+\t\tu64 reserved_0_0 : 1;\n+\t} cn73xx;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn73xx cn78xx;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn78xxp1 {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 lcl_node : 1;\n+\t\tu64 wind_d : 1;\n+\t\tu64 bar0_d : 1;\n+\t\tu64 ld_cmd : 2;\n+\t\tu64 reserved_0_0 : 1;\n+\t} cn78xxp1;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn61xx cnf71xx;\n+\tstruct cvmx_sli_s2m_portx_ctl_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sli_s2m_portx_ctl cvmx_sli_s2m_portx_ctl_t;\n+\n+/**\n+ * cvmx_sli_scratch_1\n+ *\n+ * This registers is a general purpose 64-bit scratch register for software use.\n+ *\n+ */\n+union cvmx_sli_scratch_1 {\n+\tu64 u64;\n+\tstruct cvmx_sli_scratch_1_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_sli_scratch_1_s cn61xx;\n+\tstruct cvmx_sli_scratch_1_s cn63xx;\n+\tstruct cvmx_sli_scratch_1_s cn63xxp1;\n+\tstruct cvmx_sli_scratch_1_s cn66xx;\n+\tstruct cvmx_sli_scratch_1_s cn68xx;\n+\tstruct cvmx_sli_scratch_1_s cn68xxp1;\n+\tstruct cvmx_sli_scratch_1_s cn70xx;\n+\tstruct cvmx_sli_scratch_1_s cn70xxp1;\n+\tstruct cvmx_sli_scratch_1_s cn73xx;\n+\tstruct cvmx_sli_scratch_1_s cn78xx;\n+\tstruct cvmx_sli_scratch_1_s cn78xxp1;\n+\tstruct cvmx_sli_scratch_1_s cnf71xx;\n+\tstruct cvmx_sli_scratch_1_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_scratch_1 cvmx_sli_scratch_1_t;\n+\n+/**\n+ * cvmx_sli_scratch_2\n+ *\n+ * This registers is a general purpose 64-bit scratch register for software use.\n+ *\n+ */\n+union cvmx_sli_scratch_2 {\n+\tu64 u64;\n+\tstruct cvmx_sli_scratch_2_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_sli_scratch_2_s cn61xx;\n+\tstruct cvmx_sli_scratch_2_s cn63xx;\n+\tstruct cvmx_sli_scratch_2_s cn63xxp1;\n+\tstruct cvmx_sli_scratch_2_s cn66xx;\n+\tstruct cvmx_sli_scratch_2_s cn68xx;\n+\tstruct cvmx_sli_scratch_2_s cn68xxp1;\n+\tstruct cvmx_sli_scratch_2_s cn70xx;\n+\tstruct cvmx_sli_scratch_2_s cn70xxp1;\n+\tstruct cvmx_sli_scratch_2_s cn73xx;\n+\tstruct cvmx_sli_scratch_2_s cn78xx;\n+\tstruct cvmx_sli_scratch_2_s cn78xxp1;\n+\tstruct cvmx_sli_scratch_2_s cnf71xx;\n+\tstruct cvmx_sli_scratch_2_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_scratch_2 cvmx_sli_scratch_2_t;\n+\n+/**\n+ * cvmx_sli_state1\n+ *\n+ * This register contains state machines in SLI and is for debug.\n+ *\n+ */\n+union cvmx_sli_state1 {\n+\tu64 u64;\n+\tstruct cvmx_sli_state1_s {\n+\t\tu64 cpl1 : 12;\n+\t\tu64 cpl0 : 12;\n+\t\tu64 arb : 1;\n+\t\tu64 csr : 39;\n+\t} s;\n+\tstruct cvmx_sli_state1_s cn61xx;\n+\tstruct cvmx_sli_state1_s cn63xx;\n+\tstruct cvmx_sli_state1_s cn63xxp1;\n+\tstruct cvmx_sli_state1_s cn66xx;\n+\tstruct cvmx_sli_state1_s cn68xx;\n+\tstruct cvmx_sli_state1_s cn68xxp1;\n+\tstruct cvmx_sli_state1_s cn70xx;\n+\tstruct cvmx_sli_state1_s cn70xxp1;\n+\tstruct cvmx_sli_state1_s cn73xx;\n+\tstruct cvmx_sli_state1_s cn78xx;\n+\tstruct cvmx_sli_state1_s cn78xxp1;\n+\tstruct cvmx_sli_state1_s cnf71xx;\n+\tstruct cvmx_sli_state1_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_state1 cvmx_sli_state1_t;\n+\n+/**\n+ * cvmx_sli_state2\n+ *\n+ * This register contains state machines in SLI and is for debug.\n+ *\n+ */\n+union cvmx_sli_state2 {\n+\tu64 u64;\n+\tstruct cvmx_sli_state2_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_sli_state2_cn61xx {\n+\t\tu64 reserved_56_63 : 8;\n+\t\tu64 nnp1 : 8;\n+\t\tu64 reserved_47_47 : 1;\n+\t\tu64 rac : 1;\n+\t\tu64 csm1 : 15;\n+\t\tu64 csm0 : 15;\n+\t\tu64 nnp0 : 8;\n+\t\tu64 nnd : 8;\n+\t} cn61xx;\n+\tstruct cvmx_sli_state2_cn61xx cn63xx;\n+\tstruct cvmx_sli_state2_cn61xx cn63xxp1;\n+\tstruct cvmx_sli_state2_cn61xx cn66xx;\n+\tstruct cvmx_sli_state2_cn61xx cn68xx;\n+\tstruct cvmx_sli_state2_cn61xx cn68xxp1;\n+\tstruct cvmx_sli_state2_cn61xx cn70xx;\n+\tstruct cvmx_sli_state2_cn61xx cn70xxp1;\n+\tstruct cvmx_sli_state2_cn73xx {\n+\t\tu64 reserved_57_63 : 7;\n+\t\tu64 nnp1 : 8;\n+\t\tu64 reserved_48_48 : 1;\n+\t\tu64 rac : 1;\n+\t\tu64 csm1 : 15;\n+\t\tu64 csm0 : 15;\n+\t\tu64 nnp0 : 8;\n+\t\tu64 nnd : 9;\n+\t} cn73xx;\n+\tstruct cvmx_sli_state2_cn73xx cn78xx;\n+\tstruct cvmx_sli_state2_cn73xx cn78xxp1;\n+\tstruct cvmx_sli_state2_cn61xx cnf71xx;\n+\tstruct cvmx_sli_state2_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sli_state2 cvmx_sli_state2_t;\n+\n+/**\n+ * cvmx_sli_state3\n+ *\n+ * This register contains state machines in SLI and is for debug.\n+ *\n+ */\n+union cvmx_sli_state3 {\n+\tu64 u64;\n+\tstruct cvmx_sli_state3_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_sli_state3_cn61xx {\n+\t\tu64 reserved_56_63 : 8;\n+\t\tu64 psm1 : 15;\n+\t\tu64 psm0 : 15;\n+\t\tu64 nsm1 : 13;\n+\t\tu64 nsm0 : 13;\n+\t} cn61xx;\n+\tstruct cvmx_sli_state3_cn61xx cn63xx;\n+\tstruct cvmx_sli_state3_cn61xx cn63xxp1;\n+\tstruct cvmx_sli_state3_cn61xx cn66xx;\n+\tstruct cvmx_sli_state3_cn61xx cn68xx;\n+\tstruct cvmx_sli_state3_cn61xx cn68xxp1;\n+\tstruct cvmx_sli_state3_cn61xx cn70xx;\n+\tstruct cvmx_sli_state3_cn61xx cn70xxp1;\n+\tstruct cvmx_sli_state3_cn73xx {\n+\t\tu64 reserved_60_63 : 4;\n+\t\tu64 psm1 : 15;\n+\t\tu64 psm0 : 15;\n+\t\tu64 nsm1 : 15;\n+\t\tu64 nsm0 : 15;\n+\t} cn73xx;\n+\tstruct cvmx_sli_state3_cn73xx cn78xx;\n+\tstruct cvmx_sli_state3_cn73xx cn78xxp1;\n+\tstruct cvmx_sli_state3_cn61xx cnf71xx;\n+\tstruct cvmx_sli_state3_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sli_state3 cvmx_sli_state3_t;\n+\n+/**\n+ * cvmx_sli_tx_pipe\n+ *\n+ * SLI_TX_PIPE = SLI Packet TX Pipe\n+ *\n+ * Contains the starting pipe number and number of pipes used by the SLI packet Output.\n+ * If a packet is recevied from PKO with an out of range PIPE number, the following occurs:\n+ * - SLI_INT_SUM[PIPE_ERR] is set.\n+ * - the out of range pipe value is used for returning credits to the PKO.\n+ * - the PCIe packet engine will treat the PIPE value to be equal to [BASE].\n+ */\n+union cvmx_sli_tx_pipe {\n+\tu64 u64;\n+\tstruct cvmx_sli_tx_pipe_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 nump : 8;\n+\t\tu64 reserved_7_15 : 9;\n+\t\tu64 base : 7;\n+\t} s;\n+\tstruct cvmx_sli_tx_pipe_s cn68xx;\n+\tstruct cvmx_sli_tx_pipe_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sli_tx_pipe cvmx_sli_tx_pipe_t;\n+\n+/**\n+ * cvmx_sli_win_rd_addr\n+ *\n+ * When the LSB of this register is written, the address in this register will be read. The data\n+ * returned from this read operation is placed in the WIN_RD_DATA register. This register should\n+ * NOT\n+ * be used to read SLI_* registers.\n+ */\n+union cvmx_sli_win_rd_addr {\n+\tu64 u64;\n+\tstruct cvmx_sli_win_rd_addr_s {\n+\t\tu64 reserved_51_63 : 13;\n+\t\tu64 ld_cmd : 2;\n+\t\tu64 iobit : 1;\n+\t\tu64 rd_addr : 48;\n+\t} s;\n+\tstruct cvmx_sli_win_rd_addr_s cn61xx;\n+\tstruct cvmx_sli_win_rd_addr_s cn63xx;\n+\tstruct cvmx_sli_win_rd_addr_s cn63xxp1;\n+\tstruct cvmx_sli_win_rd_addr_s cn66xx;\n+\tstruct cvmx_sli_win_rd_addr_s cn68xx;\n+\tstruct cvmx_sli_win_rd_addr_s cn68xxp1;\n+\tstruct cvmx_sli_win_rd_addr_s cn70xx;\n+\tstruct cvmx_sli_win_rd_addr_s cn70xxp1;\n+\tstruct cvmx_sli_win_rd_addr_s cn73xx;\n+\tstruct cvmx_sli_win_rd_addr_s cn78xx;\n+\tstruct cvmx_sli_win_rd_addr_s cn78xxp1;\n+\tstruct cvmx_sli_win_rd_addr_s cnf71xx;\n+\tstruct cvmx_sli_win_rd_addr_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_win_rd_addr cvmx_sli_win_rd_addr_t;\n+\n+/**\n+ * cvmx_sli_win_rd_data\n+ *\n+ * This register holds the data returned when a read operation is started by the writing of the\n+ * SLI_WIN_RD_ADDR register.\n+ */\n+union cvmx_sli_win_rd_data {\n+\tu64 u64;\n+\tstruct cvmx_sli_win_rd_data_s {\n+\t\tu64 rd_data : 64;\n+\t} s;\n+\tstruct cvmx_sli_win_rd_data_s cn61xx;\n+\tstruct cvmx_sli_win_rd_data_s cn63xx;\n+\tstruct cvmx_sli_win_rd_data_s cn63xxp1;\n+\tstruct cvmx_sli_win_rd_data_s cn66xx;\n+\tstruct cvmx_sli_win_rd_data_s cn68xx;\n+\tstruct cvmx_sli_win_rd_data_s cn68xxp1;\n+\tstruct cvmx_sli_win_rd_data_s cn70xx;\n+\tstruct cvmx_sli_win_rd_data_s cn70xxp1;\n+\tstruct cvmx_sli_win_rd_data_s cn73xx;\n+\tstruct cvmx_sli_win_rd_data_s cn78xx;\n+\tstruct cvmx_sli_win_rd_data_s cn78xxp1;\n+\tstruct cvmx_sli_win_rd_data_s cnf71xx;\n+\tstruct cvmx_sli_win_rd_data_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_win_rd_data cvmx_sli_win_rd_data_t;\n+\n+/**\n+ * cvmx_sli_win_wr_addr\n+ *\n+ * This register contains the address to be written to when a write operation is started by\n+ * writing the SLI_WIN_WR_DATA register.\n+ *\n+ * This register should NOT be used to write SLI_* registers.\n+ */\n+union cvmx_sli_win_wr_addr {\n+\tu64 u64;\n+\tstruct cvmx_sli_win_wr_addr_s {\n+\t\tu64 reserved_49_63 : 15;\n+\t\tu64 iobit : 1;\n+\t\tu64 wr_addr : 45;\n+\t\tu64 reserved_0_2 : 3;\n+\t} s;\n+\tstruct cvmx_sli_win_wr_addr_s cn61xx;\n+\tstruct cvmx_sli_win_wr_addr_s cn63xx;\n+\tstruct cvmx_sli_win_wr_addr_s cn63xxp1;\n+\tstruct cvmx_sli_win_wr_addr_s cn66xx;\n+\tstruct cvmx_sli_win_wr_addr_s cn68xx;\n+\tstruct cvmx_sli_win_wr_addr_s cn68xxp1;\n+\tstruct cvmx_sli_win_wr_addr_s cn70xx;\n+\tstruct cvmx_sli_win_wr_addr_s cn70xxp1;\n+\tstruct cvmx_sli_win_wr_addr_s cn73xx;\n+\tstruct cvmx_sli_win_wr_addr_s cn78xx;\n+\tstruct cvmx_sli_win_wr_addr_s cn78xxp1;\n+\tstruct cvmx_sli_win_wr_addr_s cnf71xx;\n+\tstruct cvmx_sli_win_wr_addr_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_win_wr_addr cvmx_sli_win_wr_addr_t;\n+\n+/**\n+ * cvmx_sli_win_wr_data\n+ *\n+ * This register contains the data to write to the address located in the SLI_WIN_WR_ADDR\n+ * register. Writing the least-significant byte of this register causes a write operation to take\n+ * place.\n+ */\n+union cvmx_sli_win_wr_data {\n+\tu64 u64;\n+\tstruct cvmx_sli_win_wr_data_s {\n+\t\tu64 wr_data : 64;\n+\t} s;\n+\tstruct cvmx_sli_win_wr_data_s cn61xx;\n+\tstruct cvmx_sli_win_wr_data_s cn63xx;\n+\tstruct cvmx_sli_win_wr_data_s cn63xxp1;\n+\tstruct cvmx_sli_win_wr_data_s cn66xx;\n+\tstruct cvmx_sli_win_wr_data_s cn68xx;\n+\tstruct cvmx_sli_win_wr_data_s cn68xxp1;\n+\tstruct cvmx_sli_win_wr_data_s cn70xx;\n+\tstruct cvmx_sli_win_wr_data_s cn70xxp1;\n+\tstruct cvmx_sli_win_wr_data_s cn73xx;\n+\tstruct cvmx_sli_win_wr_data_s cn78xx;\n+\tstruct cvmx_sli_win_wr_data_s cn78xxp1;\n+\tstruct cvmx_sli_win_wr_data_s cnf71xx;\n+\tstruct cvmx_sli_win_wr_data_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_win_wr_data cvmx_sli_win_wr_data_t;\n+\n+/**\n+ * cvmx_sli_win_wr_mask\n+ *\n+ * This register contains the mask for the data in the SLI_WIN_WR_DATA register.\n+ *\n+ */\n+union cvmx_sli_win_wr_mask {\n+\tu64 u64;\n+\tstruct cvmx_sli_win_wr_mask_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 wr_mask : 8;\n+\t} s;\n+\tstruct cvmx_sli_win_wr_mask_s cn61xx;\n+\tstruct cvmx_sli_win_wr_mask_s cn63xx;\n+\tstruct cvmx_sli_win_wr_mask_s cn63xxp1;\n+\tstruct cvmx_sli_win_wr_mask_s cn66xx;\n+\tstruct cvmx_sli_win_wr_mask_s cn68xx;\n+\tstruct cvmx_sli_win_wr_mask_s cn68xxp1;\n+\tstruct cvmx_sli_win_wr_mask_s cn70xx;\n+\tstruct cvmx_sli_win_wr_mask_s cn70xxp1;\n+\tstruct cvmx_sli_win_wr_mask_s cn73xx;\n+\tstruct cvmx_sli_win_wr_mask_s cn78xx;\n+\tstruct cvmx_sli_win_wr_mask_s cn78xxp1;\n+\tstruct cvmx_sli_win_wr_mask_s cnf71xx;\n+\tstruct cvmx_sli_win_wr_mask_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_win_wr_mask cvmx_sli_win_wr_mask_t;\n+\n+/**\n+ * cvmx_sli_window_ctl\n+ *\n+ * Access to register space on the IOI (caused by window read/write operations) waits for a\n+ * period of time specified by this register before timing out.\n+ */\n+union cvmx_sli_window_ctl {\n+\tu64 u64;\n+\tstruct cvmx_sli_window_ctl_s {\n+\t\tu64 ocx_time : 32;\n+\t\tu64 time : 32;\n+\t} s;\n+\tstruct cvmx_sli_window_ctl_cn61xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 time : 32;\n+\t} cn61xx;\n+\tstruct cvmx_sli_window_ctl_cn61xx cn63xx;\n+\tstruct cvmx_sli_window_ctl_cn61xx cn63xxp1;\n+\tstruct cvmx_sli_window_ctl_cn61xx cn66xx;\n+\tstruct cvmx_sli_window_ctl_cn61xx cn68xx;\n+\tstruct cvmx_sli_window_ctl_cn61xx cn68xxp1;\n+\tstruct cvmx_sli_window_ctl_cn61xx cn70xx;\n+\tstruct cvmx_sli_window_ctl_cn61xx cn70xxp1;\n+\tstruct cvmx_sli_window_ctl_s cn73xx;\n+\tstruct cvmx_sli_window_ctl_s cn78xx;\n+\tstruct cvmx_sli_window_ctl_s cn78xxp1;\n+\tstruct cvmx_sli_window_ctl_cn61xx cnf71xx;\n+\tstruct cvmx_sli_window_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_sli_window_ctl cvmx_sli_window_ctl_t;\n+\n+#endif\n",
    "prefixes": [
        "v1",
        "28/50"
    ]
}