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{
    "id": 1415043,
    "url": "http://patchwork.ozlabs.org/api/patches/1415043/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-18-sr@denx.de/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20201211160612.1498780-18-sr@denx.de>",
    "list_archive_url": null,
    "date": "2020-12-11T16:05:39",
    "name": "[v1,17/50] mips: octeon: Add cvmx-pcieepx-defs.h header file",
    "commit_ref": "c7ccfde7390a521f126034deda0610e4d7a54e39",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "8f3217f3ec431c8a4ad299da579265b7d16a1a20",
    "submitter": {
        "id": 13,
        "url": "http://patchwork.ozlabs.org/api/people/13/?format=api",
        "name": "Stefan Roese",
        "email": "sr@denx.de"
    },
    "delegate": {
        "id": 4307,
        "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api",
        "username": "danielschwierzeck",
        "first_name": "Daniel",
        "last_name": "Schwierzeck",
        "email": "daniel.schwierzeck@googlemail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-18-sr@denx.de/mbox/",
    "series": [
        {
            "id": 220054,
            "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054",
            "date": "2020-12-11T16:05:23",
            "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1415043/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1415043/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Stefan Roese <sr@denx.de>",
        "To": "u-boot@lists.denx.de",
        "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com",
        "Subject": "[PATCH v1 17/50] mips: octeon: Add cvmx-pcieepx-defs.h header file",
        "Date": "Fri, 11 Dec 2020 17:05:39 +0100",
        "Message-Id": "<20201211160612.1498780-18-sr@denx.de>",
        "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>",
        "References": "<20201211160612.1498780-1-sr@denx.de>",
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    "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-pcieepx-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../include/mach/cvmx-pcieepx-defs.h          | 6848 +++++++++++++++++\n 1 file changed, 6848 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pcieepx-defs.h",
    "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pcieepx-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-pcieepx-defs.h\nnew file mode 100644\nindex 0000000000..13ef599a92\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-pcieepx-defs.h\n@@ -0,0 +1,6848 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon pcieepx.\n+ */\n+\n+#ifndef __CVMX_PCIEEPX_DEFS_H__\n+#define __CVMX_PCIEEPX_DEFS_H__\n+\n+static inline u64 CVMX_PCIEEPX_CFG000(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000000ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000000ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000000ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000000ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000000ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000000ull;\n+\t}\n+\treturn 0x0000030000000000ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG001(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000004ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000004ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000004ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000004ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000004ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000004ull;\n+\t}\n+\treturn 0x0000030000000004ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG002(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000008ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000008ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000008ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000008ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000008ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000008ull;\n+\t}\n+\treturn 0x0000030000000008ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG003(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000000Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000000Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000000Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000000Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000000Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000000Cull;\n+\t}\n+\treturn 0x000003000000000Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG004(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000010ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000010ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000010ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000010ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000010ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000010ull;\n+\t}\n+\treturn 0x0000030000000010ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG004_MASK(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000010ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000010ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030080000010ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030080000010ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000010ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000080000010ull;\n+\t}\n+\treturn 0x0000030080000010ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG005(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000014ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000014ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000014ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000014ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000014ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000014ull;\n+\t}\n+\treturn 0x0000030000000014ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG005_MASK(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000014ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000014ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030080000014ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030080000014ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000014ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000080000014ull;\n+\t}\n+\treturn 0x0000030080000014ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG006(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000018ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000018ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000018ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000018ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000018ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000018ull;\n+\t}\n+\treturn 0x0000030000000018ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG006_MASK(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000018ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000018ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030080000018ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030080000018ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000018ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000080000018ull;\n+\t}\n+\treturn 0x0000030080000018ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG007(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000001Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000001Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000001Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000001Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000001Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000001Cull;\n+\t}\n+\treturn 0x000003000000001Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG007_MASK(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003008000001Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003008000001Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003008000001Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003008000001Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003008000001Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000008000001Cull;\n+\t}\n+\treturn 0x000003008000001Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG008(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000020ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000020ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000020ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000020ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000020ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000020ull;\n+\t}\n+\treturn 0x0000030000000020ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG008_MASK(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000020ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000020ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030080000020ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030080000020ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000020ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000080000020ull;\n+\t}\n+\treturn 0x0000030080000020ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG009(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000024ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000024ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000024ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000024ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000024ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000024ull;\n+\t}\n+\treturn 0x0000030000000024ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG009_MASK(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000024ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000024ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030080000024ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030080000024ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000024ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000080000024ull;\n+\t}\n+\treturn 0x0000030080000024ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG010(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000028ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000028ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000028ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000028ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000028ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000028ull;\n+\t}\n+\treturn 0x0000030000000028ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG011(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000002Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000002Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000002Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000002Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000002Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000002Cull;\n+\t}\n+\treturn 0x000003000000002Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG012(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000030ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000030ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000030ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000030ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000030ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000030ull;\n+\t}\n+\treturn 0x0000030000000030ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG012_MASK(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000030ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000030ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030080000030ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030080000030ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030080000030ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000080000030ull;\n+\t}\n+\treturn 0x0000030080000030ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG013(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000034ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000034ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000034ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000034ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000034ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000034ull;\n+\t}\n+\treturn 0x0000030000000034ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG015(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000003Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000003Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000003Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000003Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000003Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000003Cull;\n+\t}\n+\treturn 0x000003000000003Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG016(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000040ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000040ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000040ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000040ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000040ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000040ull;\n+\t}\n+\treturn 0x0000030000000040ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG017(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000044ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000044ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000044ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000044ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000044ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000044ull;\n+\t}\n+\treturn 0x0000030000000044ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG020(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000050ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000050ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000050ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000050ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000050ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000050ull;\n+\t}\n+\treturn 0x0000030000000050ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG021(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000054ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000054ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000054ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000054ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000054ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000054ull;\n+\t}\n+\treturn 0x0000030000000054ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG022(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000058ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000058ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000058ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000058ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000058ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000058ull;\n+\t}\n+\treturn 0x0000030000000058ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG023(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000005Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000005Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000005Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000005Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000005Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000005Cull;\n+\t}\n+\treturn 0x000003000000005Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG024(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000060ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000060ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000060ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000060ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000060ull + (offset) * 0x100000000ull;\n+\t}\n+\treturn 0x0000030000000060ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG025(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000064ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000064ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000064ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000064ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000064ull + (offset) * 0x100000000ull;\n+\t}\n+\treturn 0x0000030000000064ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG028(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000070ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000070ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000070ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000070ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000070ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000070ull;\n+\t}\n+\treturn 0x0000030000000070ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG029(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000074ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000074ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000074ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000074ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000074ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000074ull;\n+\t}\n+\treturn 0x0000030000000074ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG030(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000078ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000078ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000078ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000078ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000078ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000078ull;\n+\t}\n+\treturn 0x0000030000000078ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG031(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000007Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000007Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000007Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000007Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000007Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000007Cull;\n+\t}\n+\treturn 0x000003000000007Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG032(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000080ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000080ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000080ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000080ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000080ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000080ull;\n+\t}\n+\treturn 0x0000030000000080ull;\n+}\n+\n+#define CVMX_PCIEEPX_CFG033(offset) (0x0000000000000084ull)\n+#define CVMX_PCIEEPX_CFG034(offset) (0x0000000000000088ull)\n+static inline u64 CVMX_PCIEEPX_CFG037(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000094ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000094ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000094ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000094ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000094ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000094ull;\n+\t}\n+\treturn 0x0000030000000094ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG038(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000098ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000098ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000098ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000098ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000098ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000098ull;\n+\t}\n+\treturn 0x0000030000000098ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG039(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000009Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000009Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000009Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000009Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000009Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000009Cull;\n+\t}\n+\treturn 0x000003000000009Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG040(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000000A0ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000000A0ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000000A0ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000000A0ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000000A0ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000000A0ull;\n+\t}\n+\treturn 0x00000300000000A0ull;\n+}\n+\n+#define CVMX_PCIEEPX_CFG041(offset) (0x00000000000000A4ull)\n+#define CVMX_PCIEEPX_CFG042(offset) (0x00000000000000A8ull)\n+static inline u64 CVMX_PCIEEPX_CFG044(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000000B0ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000000B0ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000000B0ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000000B0ull;\n+\t}\n+\treturn 0x00000300000000B0ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG045(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000000B4ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000000B4ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000000B4ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000000B4ull;\n+\t}\n+\treturn 0x00000300000000B4ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG046(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000000B8ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000000B8ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000000B8ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000000B8ull;\n+\t}\n+\treturn 0x00000300000000B8ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG064(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000100ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000100ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000100ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000100ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000100ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000100ull;\n+\t}\n+\treturn 0x0000030000000100ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG065(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000104ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000104ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000104ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000104ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000104ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000104ull;\n+\t}\n+\treturn 0x0000030000000104ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG066(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000108ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000108ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000108ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000108ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000108ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000108ull;\n+\t}\n+\treturn 0x0000030000000108ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG067(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000010Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000010Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000010Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000010Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000010Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000010Cull;\n+\t}\n+\treturn 0x000003000000010Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG068(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000110ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000110ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000110ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000110ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000110ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000110ull;\n+\t}\n+\treturn 0x0000030000000110ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG069(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000114ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000114ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000114ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000114ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000114ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000114ull;\n+\t}\n+\treturn 0x0000030000000114ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG070(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000118ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000118ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000118ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000118ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000118ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000118ull;\n+\t}\n+\treturn 0x0000030000000118ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG071(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000011Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000011Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000011Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000011Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000011Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000011Cull;\n+\t}\n+\treturn 0x000003000000011Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG072(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000120ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000120ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000120ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000120ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000120ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000120ull;\n+\t}\n+\treturn 0x0000030000000120ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG073(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000124ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000124ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000124ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000124ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000124ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000124ull;\n+\t}\n+\treturn 0x0000030000000124ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG074(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000128ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000128ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000128ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000128ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000128ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000128ull;\n+\t}\n+\treturn 0x0000030000000128ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG078(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000138ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000138ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000138ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000138ull;\n+\t}\n+\treturn 0x0000030000000138ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG082(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000148ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000148ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000148ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000148ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000148ull + (offset) * 0x100000000ull;\n+\t}\n+\treturn 0x0000030000000148ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG083(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000014Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000014Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000014Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000014Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000014Cull + (offset) * 0x100000000ull;\n+\t}\n+\treturn 0x000003000000014Cull;\n+}\n+\n+#define CVMX_PCIEEPX_CFG084(offset) (0x0000030000000150ull + ((offset) & 3) * 0x100000000ull)\n+static inline u64 CVMX_PCIEEPX_CFG086(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000158ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000158ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000158ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000158ull;\n+\t}\n+\treturn 0x0000030000000158ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG087(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000015Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000015Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000015Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000015Cull;\n+\t}\n+\treturn 0x000003000000015Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG088(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000160ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000160ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000160ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000160ull;\n+\t}\n+\treturn 0x0000030000000160ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG089(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000164ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000164ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000164ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000164ull;\n+\t}\n+\treturn 0x0000030000000164ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG090(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000168ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000168ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000168ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000168ull;\n+\t}\n+\treturn 0x0000030000000168ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG091(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000016Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000016Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000016Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000016Cull;\n+\t}\n+\treturn 0x000003000000016Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG092(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000170ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000170ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000170ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000170ull;\n+\t}\n+\treturn 0x0000030000000170ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG094(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000178ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000178ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000178ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000178ull;\n+\t}\n+\treturn 0x0000030000000178ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG095(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000017Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000017Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000017Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000017Cull;\n+\t}\n+\treturn 0x000003000000017Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG096(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000180ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000180ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000180ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000180ull;\n+\t}\n+\treturn 0x0000030000000180ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG097(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000184ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000184ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000184ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000184ull;\n+\t}\n+\treturn 0x0000030000000184ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG098(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000188ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000188ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000188ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000188ull;\n+\t}\n+\treturn 0x0000030000000188ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG099(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000018Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000018Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000018Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000018Cull;\n+\t}\n+\treturn 0x000003000000018Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG100(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000190ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000190ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000190ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000190ull;\n+\t}\n+\treturn 0x0000030000000190ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG101(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000194ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000194ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000194ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000194ull;\n+\t}\n+\treturn 0x0000030000000194ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG102(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000198ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000198ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000198ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000198ull;\n+\t}\n+\treturn 0x0000030000000198ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG103(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000019Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000019Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000019Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000019Cull;\n+\t}\n+\treturn 0x000003000000019Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG104(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000001A0ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000001A0ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001A0ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001A0ull;\n+\t}\n+\treturn 0x00000300000001A0ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG105(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000001A4ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000001A4ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001A4ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001A4ull;\n+\t}\n+\treturn 0x00000300000001A4ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG106(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000001A8ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000001A8ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001A8ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001A8ull;\n+\t}\n+\treturn 0x00000300000001A8ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG107(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000001ACull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000001ACull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001ACull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001ACull;\n+\t}\n+\treturn 0x00000300000001ACull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG108(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000001B0ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000001B0ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001B0ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001B0ull;\n+\t}\n+\treturn 0x00000300000001B0ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG109(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000001B4ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000001B4ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001B4ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001B4ull;\n+\t}\n+\treturn 0x00000300000001B4ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG110(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000001B8ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000001B8ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001B8ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001B8ull;\n+\t}\n+\treturn 0x00000300000001B8ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG111(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000001BCull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000001BCull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001BCull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001BCull;\n+\t}\n+\treturn 0x00000300000001BCull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG112(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000001C0ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000001C0ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001C0ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000001C0ull;\n+\t}\n+\treturn 0x00000300000001C0ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG448(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000700ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000700ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000700ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000700ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000700ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000700ull;\n+\t}\n+\treturn 0x0000030000000700ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG449(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000704ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000704ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000704ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000704ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000704ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000704ull;\n+\t}\n+\treturn 0x0000030000000704ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG450(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000708ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000708ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000708ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000708ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000708ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000708ull;\n+\t}\n+\treturn 0x0000030000000708ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG451(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000070Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000070Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000070Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000070Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000070Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000070Cull;\n+\t}\n+\treturn 0x000003000000070Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG452(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000710ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000710ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000710ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000710ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000710ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000710ull;\n+\t}\n+\treturn 0x0000030000000710ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG453(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000714ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000714ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000714ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000714ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000714ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000714ull;\n+\t}\n+\treturn 0x0000030000000714ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG454(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000718ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000718ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000718ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000718ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000718ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000718ull;\n+\t}\n+\treturn 0x0000030000000718ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG455(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000071Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000071Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000071Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000071Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000071Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000071Cull;\n+\t}\n+\treturn 0x000003000000071Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG456(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000720ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000720ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000720ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000720ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000720ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000720ull;\n+\t}\n+\treturn 0x0000030000000720ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG458(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000728ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000728ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000728ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000728ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000728ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000728ull;\n+\t}\n+\treturn 0x0000030000000728ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG459(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000072Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000072Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000072Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000072Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000072Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000072Cull;\n+\t}\n+\treturn 0x000003000000072Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG460(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000730ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000730ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000730ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000730ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000730ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000730ull;\n+\t}\n+\treturn 0x0000030000000730ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG461(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000734ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000734ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000734ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000734ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000734ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000734ull;\n+\t}\n+\treturn 0x0000030000000734ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG462(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000738ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000738ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000738ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000738ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000738ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000738ull;\n+\t}\n+\treturn 0x0000030000000738ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG463(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000073Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000073Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000073Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000073Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000073Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000073Cull;\n+\t}\n+\treturn 0x000003000000073Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG464(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000740ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000740ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000740ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000740ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000740ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000740ull;\n+\t}\n+\treturn 0x0000030000000740ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG465(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000744ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000744ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000744ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000744ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000744ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000744ull;\n+\t}\n+\treturn 0x0000030000000744ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG466(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000748ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000748ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000748ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000748ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000748ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000748ull;\n+\t}\n+\treturn 0x0000030000000748ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG467(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000074Cull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000074Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000074Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000074Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000074Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000074Cull;\n+\t}\n+\treturn 0x000003000000074Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG468(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000750ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000750ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000750ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000750ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000750ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000750ull;\n+\t}\n+\treturn 0x0000030000000750ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG490(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000007A8ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000007A8ull + (offset) * 0x100000000ull;\n+\t}\n+\treturn 0x00000000000007A8ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG491(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000007ACull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000007ACull + (offset) * 0x100000000ull;\n+\t}\n+\treturn 0x00000000000007ACull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG492(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000000000007B0ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000007B0ull + (offset) * 0x100000000ull;\n+\t}\n+\treturn 0x00000000000007B0ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG515(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000080Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x000003000000080Cull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x000003000000080Cull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000080Cull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000003000000080Cull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x000000000000080Cull;\n+\t}\n+\treturn 0x000003000000080Cull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG516(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000810ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000810ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000810ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000810ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000810ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000810ull;\n+\t}\n+\treturn 0x0000030000000810ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG517(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000814ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000814ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000814ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000814ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000814ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000814ull;\n+\t}\n+\treturn 0x0000030000000814ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG548(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0000030000000890ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0000030000000890ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000890ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000030000000890ull;\n+\t}\n+\treturn 0x0000030000000890ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG554(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000008A8ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000008A8ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000008A8ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000008A8ull;\n+\t}\n+\treturn 0x00000300000008A8ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG558(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000008B8ull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000008B8ull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000008B8ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000008B8ull;\n+\t}\n+\treturn 0x00000300000008B8ull;\n+}\n+\n+static inline u64 CVMX_PCIEEPX_CFG559(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00000300000008BCull + (offset) * 0x100000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00000300000008BCull + (offset) * 0x100000000ull;\n+\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000008BCull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00000300000008BCull;\n+\t}\n+\treturn 0x00000300000008BCull;\n+}\n+\n+/**\n+ * cvmx_pcieep#_cfg000\n+ *\n+ * This register contains the first 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg000 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg000_s {\n+\t\tu32 devid : 16;\n+\t\tu32 vendid : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg000_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg000_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg000_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg000_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg000_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg000_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg000_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg000_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg000_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg000_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg000_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg000_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg000_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg000_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg000_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg000_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg000_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg000 cvmx_pcieepx_cfg000_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg001\n+ *\n+ * This register contains the second 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg001 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg001_s {\n+\t\tu32 dpe : 1;\n+\t\tu32 sse : 1;\n+\t\tu32 rma : 1;\n+\t\tu32 rta : 1;\n+\t\tu32 sta : 1;\n+\t\tu32 devt : 2;\n+\t\tu32 mdpe : 1;\n+\t\tu32 fbb : 1;\n+\t\tu32 reserved_22_22 : 1;\n+\t\tu32 m66 : 1;\n+\t\tu32 cl : 1;\n+\t\tu32 i_stat : 1;\n+\t\tu32 reserved_11_18 : 8;\n+\t\tu32 i_dis : 1;\n+\t\tu32 fbbe : 1;\n+\t\tu32 see : 1;\n+\t\tu32 ids_wcc : 1;\n+\t\tu32 per : 1;\n+\t\tu32 vps : 1;\n+\t\tu32 mwice : 1;\n+\t\tu32 scse : 1;\n+\t\tu32 me : 1;\n+\t\tu32 msae : 1;\n+\t\tu32 isae : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg001_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg001_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg001_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg001_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg001_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg001_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg001_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg001_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg001_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg001_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg001_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg001_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg001_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg001_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg001_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg001_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg001_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg001 cvmx_pcieepx_cfg001_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg002\n+ *\n+ * This register contains the third 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg002 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg002_s {\n+\t\tu32 bcc : 8;\n+\t\tu32 sc : 8;\n+\t\tu32 pi : 8;\n+\t\tu32 rid : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg002_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg002_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg002_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg002_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg002_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg002_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg002_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg002_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg002_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg002_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg002_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg002_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg002_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg002_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg002_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg002_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg002_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg002 cvmx_pcieepx_cfg002_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg003\n+ *\n+ * This register contains the fourth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg003 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg003_s {\n+\t\tu32 bist : 8;\n+\t\tu32 mfd : 1;\n+\t\tu32 chf : 7;\n+\t\tu32 lt : 8;\n+\t\tu32 cls : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg003_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg003_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg003_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg003_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg003_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg003_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg003_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg003_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg003_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg003_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg003_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg003_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg003_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg003_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg003_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg003_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg003_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg003 cvmx_pcieepx_cfg003_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg004\n+ *\n+ * This register contains the fifth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg004 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg004_s {\n+\t\tu32 reserved_4_31 : 28;\n+\t\tu32 pf : 1;\n+\t\tu32 typ : 2;\n+\t\tu32 mspc : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx {\n+\t\tu32 lbab : 18;\n+\t\tu32 reserved_4_13 : 10;\n+\t\tu32 pf : 1;\n+\t\tu32 typ : 2;\n+\t\tu32 mspc : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx cn61xx;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx cn70xx;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg004_cn73xx {\n+\t\tu32 lbab : 9;\n+\t\tu32 reserved_4_22 : 19;\n+\t\tu32 pf : 1;\n+\t\tu32 typ : 2;\n+\t\tu32 mspc : 1;\n+\t} cn73xx;\n+\tstruct cvmx_pcieepx_cfg004_cn73xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg004_cn78xxp1 {\n+\t\tu32 lbab : 17;\n+\t\tu32 reserved_4_14 : 11;\n+\t\tu32 pf : 1;\n+\t\tu32 typ : 2;\n+\t\tu32 mspc : 1;\n+\t} cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg004_cn52xx cnf71xx;\n+\tstruct cvmx_pcieepx_cfg004_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg004 cvmx_pcieepx_cfg004_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg004_mask\n+ *\n+ * The BAR 0 mask register is invisible to host software and not readable from the application.\n+ * The BAR 0 mask register is only writable through PEM()_CFG_WR.\n+ */\n+union cvmx_pcieepx_cfg004_mask {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg004_mask_s {\n+\t\tu32 lmask : 31;\n+\t\tu32 enb : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg004_mask_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg004_mask cvmx_pcieepx_cfg004_mask_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg005\n+ *\n+ * This register contains the sixth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg005 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg005_s {\n+\t\tu32 ubab : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg005_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg005_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg005_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg005_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg005_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg005_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg005_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg005_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg005_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg005_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg005_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg005_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg005_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg005_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg005_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg005_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg005_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg005 cvmx_pcieepx_cfg005_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg005_mask\n+ *\n+ * The BAR 0 mask register is invisible to host software and not readable from the application.\n+ * The BAR 0 mask register is only writable through PEM()_CFG_WR.\n+ */\n+union cvmx_pcieepx_cfg005_mask {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg005_mask_s {\n+\t\tu32 umask : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg005_mask_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg005_mask cvmx_pcieepx_cfg005_mask_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg006\n+ *\n+ * This register contains the seventh 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg006 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg006_s {\n+\t\tu32 lbab : 6;\n+\t\tu32 reserved_4_25 : 22;\n+\t\tu32 pf : 1;\n+\t\tu32 typ : 2;\n+\t\tu32 mspc : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg006_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg006_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg006_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg006_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg006_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg006_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg006_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg006_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg006_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg006_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg006_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg006_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg006_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg006_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg006_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg006_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg006_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg006 cvmx_pcieepx_cfg006_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg006_mask\n+ *\n+ * The BAR 1 mask register is invisible to host software and not readable from the application.\n+ * The BAR 1 mask register is only writable through PEM()_CFG_WR.\n+ */\n+union cvmx_pcieepx_cfg006_mask {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg006_mask_s {\n+\t\tu32 lmask : 31;\n+\t\tu32 enb : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg006_mask_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg006_mask cvmx_pcieepx_cfg006_mask_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg007\n+ *\n+ * This register contains the eighth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg007 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg007_s {\n+\t\tu32 ubab : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg007_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg007_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg007_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg007_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg007_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg007_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg007_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg007_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg007_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg007_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg007_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg007_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg007_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg007_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg007_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg007_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg007_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg007 cvmx_pcieepx_cfg007_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg007_mask\n+ *\n+ * The BAR 1 mask register is invisible to host software and not readable from the application.\n+ * The BAR 1 mask register is only writable through PEM()_CFG_WR.\n+ */\n+union cvmx_pcieepx_cfg007_mask {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg007_mask_s {\n+\t\tu32 umask : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg007_mask_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg007_mask cvmx_pcieepx_cfg007_mask_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg008\n+ *\n+ * This register contains the ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg008 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg008_s {\n+\t\tu32 lbab : 12;\n+\t\tu32 reserved_4_19 : 16;\n+\t\tu32 pf : 1;\n+\t\tu32 typ : 2;\n+\t\tu32 mspc : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg008_cn52xx {\n+\t\tu32 reserved_4_31 : 28;\n+\t\tu32 pf : 1;\n+\t\tu32 typ : 2;\n+\t\tu32 mspc : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg008_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg008_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg008_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg008_cn52xx cn61xx;\n+\tstruct cvmx_pcieepx_cfg008_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg008_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg008_cn52xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg008_cn52xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg008_cn52xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg008_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg008_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg008_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg008_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg008_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg008_cn52xx cnf71xx;\n+\tstruct cvmx_pcieepx_cfg008_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg008 cvmx_pcieepx_cfg008_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg008_mask\n+ *\n+ * The BAR 2 mask register is invisible to host software and not readable from the application.\n+ * The BAR 2 mask register is only writable through PEM()_CFG_WR.\n+ */\n+union cvmx_pcieepx_cfg008_mask {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg008_mask_s {\n+\t\tu32 lmask : 31;\n+\t\tu32 enb : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg008_mask_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg008_mask cvmx_pcieepx_cfg008_mask_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg009\n+ *\n+ * This register contains the tenth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg009 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg009_s {\n+\t\tu32 reserved_0_31 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg009_cn52xx {\n+\t\tu32 ubab : 25;\n+\t\tu32 reserved_0_6 : 7;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg009_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg009_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg009_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg009_cn61xx {\n+\t\tu32 ubab : 23;\n+\t\tu32 reserved_0_8 : 9;\n+\t} cn61xx;\n+\tstruct cvmx_pcieepx_cfg009_cn61xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg009_cn61xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg009_cn61xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg009_cn61xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg009_cn61xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg009_cn70xx {\n+\t\tu32 ubab : 32;\n+\t} cn70xx;\n+\tstruct cvmx_pcieepx_cfg009_cn70xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg009_cn70xx cn73xx;\n+\tstruct cvmx_pcieepx_cfg009_cn70xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg009_cn70xx cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg009_cn61xx cnf71xx;\n+\tstruct cvmx_pcieepx_cfg009_cn70xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg009 cvmx_pcieepx_cfg009_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg009_mask\n+ *\n+ * The BAR 2 mask register is invisible to host software and not readable from the application.\n+ * The BAR 2 mask register is only writable through PEM()_CFG_WR.\n+ */\n+union cvmx_pcieepx_cfg009_mask {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg009_mask_s {\n+\t\tu32 umask : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg009_mask_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg009_mask cvmx_pcieepx_cfg009_mask_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg010\n+ *\n+ * This register contains the eleventh 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg010 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg010_s {\n+\t\tu32 cisp : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg010_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg010_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg010_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg010_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg010_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg010_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg010_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg010_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg010_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg010_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg010_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg010_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg010_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg010_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg010_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg010_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg010_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg010 cvmx_pcieepx_cfg010_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg011\n+ *\n+ * This register contains the twelfth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg011 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg011_s {\n+\t\tu32 ssid : 16;\n+\t\tu32 ssvid : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg011_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg011_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg011_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg011_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg011_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg011_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg011_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg011_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg011_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg011_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg011_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg011_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg011_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg011_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg011_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg011_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg011_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg011 cvmx_pcieepx_cfg011_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg012\n+ *\n+ * This register contains the thirteenth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg012 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg012_s {\n+\t\tu32 eraddr : 16;\n+\t\tu32 reserved_1_15 : 15;\n+\t\tu32 er_en : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg012_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg012_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg012_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg012_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg012_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg012_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg012_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg012_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg012_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg012_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg012_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg012_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg012_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg012_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg012_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg012_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg012_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg012 cvmx_pcieepx_cfg012_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg012_mask\n+ *\n+ * The ROM mask register is invisible to host software and not readable from the application. The\n+ * ROM mask register is only writable through PEM()_CFG_WR.\n+ */\n+union cvmx_pcieepx_cfg012_mask {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg012_mask_s {\n+\t\tu32 mask : 31;\n+\t\tu32 enb : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg012_mask_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg012_mask cvmx_pcieepx_cfg012_mask_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg013\n+ *\n+ * This register contains the fourteenth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg013 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg013_s {\n+\t\tu32 reserved_8_31 : 24;\n+\t\tu32 cp : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg013_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg013_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg013_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg013_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg013_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg013_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg013_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg013_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg013_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg013_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg013_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg013_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg013_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg013_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg013_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg013_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg013_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg013 cvmx_pcieepx_cfg013_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg015\n+ *\n+ * This register contains the sixteenth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg015 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg015_s {\n+\t\tu32 ml : 8;\n+\t\tu32 mg : 8;\n+\t\tu32 inta : 8;\n+\t\tu32 il : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg015_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg015_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg015_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg015_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg015_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg015_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg015_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg015_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg015_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg015_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg015_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg015_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg015_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg015_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg015_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg015_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg015_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg015 cvmx_pcieepx_cfg015_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg016\n+ *\n+ * This register contains the seventeenth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg016 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg016_s {\n+\t\tu32 pmes : 5;\n+\t\tu32 d2s : 1;\n+\t\tu32 d1s : 1;\n+\t\tu32 auxc : 3;\n+\t\tu32 dsi : 1;\n+\t\tu32 reserved_20_20 : 1;\n+\t\tu32 pme_clock : 1;\n+\t\tu32 pmsv : 3;\n+\t\tu32 ncp : 8;\n+\t\tu32 pmcid : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg016_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg016_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg016_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg016_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg016_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg016_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg016_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg016_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg016_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg016_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg016_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg016_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg016_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg016_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg016_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg016_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg016_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg016 cvmx_pcieepx_cfg016_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg017\n+ *\n+ * This register contains the eighteenth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg017 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg017_s {\n+\t\tu32 pmdia : 8;\n+\t\tu32 bpccee : 1;\n+\t\tu32 bd3h : 1;\n+\t\tu32 reserved_16_21 : 6;\n+\t\tu32 pmess : 1;\n+\t\tu32 pmedsia : 2;\n+\t\tu32 pmds : 4;\n+\t\tu32 pmeens : 1;\n+\t\tu32 reserved_4_7 : 4;\n+\t\tu32 nsr : 1;\n+\t\tu32 reserved_2_2 : 1;\n+\t\tu32 ps : 2;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg017_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg017_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg017_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg017_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg017_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg017_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg017_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg017_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg017_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg017_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg017_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg017_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg017_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg017_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg017_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg017_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg017_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg017 cvmx_pcieepx_cfg017_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg020\n+ *\n+ * This register contains the twenty-first 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg020 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg020_s {\n+\t\tu32 reserved_25_31 : 7;\n+\t\tu32 pvm : 1;\n+\t\tu32 m64 : 1;\n+\t\tu32 mme : 3;\n+\t\tu32 mmc : 3;\n+\t\tu32 msien : 1;\n+\t\tu32 ncp : 8;\n+\t\tu32 msicid : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg020_cn52xx {\n+\t\tu32 reserved_24_31 : 8;\n+\t\tu32 m64 : 1;\n+\t\tu32 mme : 3;\n+\t\tu32 mmc : 3;\n+\t\tu32 msien : 1;\n+\t\tu32 ncp : 8;\n+\t\tu32 msicid : 8;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg020_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg020_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg020_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg020_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg020_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg020_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg020_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg020_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg020_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg020_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg020_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg020_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg020_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg020_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg020_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg020_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg020 cvmx_pcieepx_cfg020_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg021\n+ *\n+ * This register contains the twenty-second 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg021 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg021_s {\n+\t\tu32 lmsi : 30;\n+\t\tu32 reserved_0_1 : 2;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg021_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg021_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg021_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg021_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg021_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg021_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg021_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg021_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg021_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg021_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg021_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg021_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg021_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg021_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg021_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg021_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg021_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg021 cvmx_pcieepx_cfg021_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg022\n+ *\n+ * This register contains the twenty-third 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg022 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg022_s {\n+\t\tu32 umsi : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg022_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg022_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg022_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg022_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg022_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg022_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg022_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg022_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg022_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg022_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg022_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg022_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg022_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg022_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg022_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg022_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg022_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg022 cvmx_pcieepx_cfg022_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg023\n+ *\n+ * This register contains the twenty-fourth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg023 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg023_s {\n+\t\tu32 reserved_16_31 : 16;\n+\t\tu32 msimd : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg023_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg023_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg023_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg023_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg023_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg023_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg023_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg023_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg023_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg023_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg023_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg023_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg023_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg023_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg023_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg023_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg023_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg023 cvmx_pcieepx_cfg023_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg024\n+ *\n+ * This register contains the twenty-fifth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg024 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg024_s {\n+\t\tu32 msimm : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg024_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg024_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg024_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg024_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg024_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg024_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg024 cvmx_pcieepx_cfg024_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg025\n+ *\n+ * This register contains the twenty-sixth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg025 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg025_s {\n+\t\tu32 msimp : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg025_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg025_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg025_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg025_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg025_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg025_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg025 cvmx_pcieepx_cfg025_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg028\n+ *\n+ * This register contains the twenty-ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg028 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg028_s {\n+\t\tu32 reserved_30_31 : 2;\n+\t\tu32 imn : 5;\n+\t\tu32 si : 1;\n+\t\tu32 dpt : 4;\n+\t\tu32 pciecv : 4;\n+\t\tu32 ncp : 8;\n+\t\tu32 pcieid : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg028_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg028_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg028_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg028_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg028_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg028_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg028_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg028_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg028_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg028_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg028_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg028_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg028_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg028_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg028_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg028_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg028_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg028 cvmx_pcieepx_cfg028_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg029\n+ *\n+ * This register contains the thirtieth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg029 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg029_s {\n+\t\tu32 reserved_28_31 : 4;\n+\t\tu32 cspls : 2;\n+\t\tu32 csplv : 8;\n+\t\tu32 reserved_16_17 : 2;\n+\t\tu32 rber : 1;\n+\t\tu32 reserved_12_14 : 3;\n+\t\tu32 el1al : 3;\n+\t\tu32 el0al : 3;\n+\t\tu32 etfs : 1;\n+\t\tu32 pfs : 2;\n+\t\tu32 mpss : 3;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg029_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg029_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg029_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg029_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg029_cn61xx {\n+\t\tu32 reserved_29_31 : 3;\n+\t\tu32 flr_cap : 1;\n+\t\tu32 cspls : 2;\n+\t\tu32 csplv : 8;\n+\t\tu32 reserved_16_17 : 2;\n+\t\tu32 rber : 1;\n+\t\tu32 reserved_12_14 : 3;\n+\t\tu32 el1al : 3;\n+\t\tu32 el0al : 3;\n+\t\tu32 etfs : 1;\n+\t\tu32 pfs : 2;\n+\t\tu32 mpss : 3;\n+\t} cn61xx;\n+\tstruct cvmx_pcieepx_cfg029_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg029_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg029_cn66xx {\n+\t\tu32 reserved_29_31 : 3;\n+\t\tu32 flr : 1;\n+\t\tu32 cspls : 2;\n+\t\tu32 csplv : 8;\n+\t\tu32 reserved_16_17 : 2;\n+\t\tu32 rber : 1;\n+\t\tu32 reserved_12_14 : 3;\n+\t\tu32 el1al : 3;\n+\t\tu32 el0al : 3;\n+\t\tu32 etfs : 1;\n+\t\tu32 pfs : 2;\n+\t\tu32 mpss : 3;\n+\t} cn66xx;\n+\tstruct cvmx_pcieepx_cfg029_cn66xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg029_cn66xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg029_cn61xx cn70xx;\n+\tstruct cvmx_pcieepx_cfg029_cn61xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg029_cn61xx cn73xx;\n+\tstruct cvmx_pcieepx_cfg029_cn61xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg029_cn61xx cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg029_cn61xx cnf71xx;\n+\tstruct cvmx_pcieepx_cfg029_cn61xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg029 cvmx_pcieepx_cfg029_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg030\n+ *\n+ * This register contains the thirty-first 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg030 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg030_s {\n+\t\tu32 reserved_22_31 : 10;\n+\t\tu32 tp : 1;\n+\t\tu32 ap_d : 1;\n+\t\tu32 ur_d : 1;\n+\t\tu32 fe_d : 1;\n+\t\tu32 nfe_d : 1;\n+\t\tu32 ce_d : 1;\n+\t\tu32 i_flr : 1;\n+\t\tu32 mrrs : 3;\n+\t\tu32 ns_en : 1;\n+\t\tu32 ap_en : 1;\n+\t\tu32 pf_en : 1;\n+\t\tu32 etf_en : 1;\n+\t\tu32 mps : 3;\n+\t\tu32 ro_en : 1;\n+\t\tu32 ur_en : 1;\n+\t\tu32 fe_en : 1;\n+\t\tu32 nfe_en : 1;\n+\t\tu32 ce_en : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg030_cn52xx {\n+\t\tu32 reserved_22_31 : 10;\n+\t\tu32 tp : 1;\n+\t\tu32 ap_d : 1;\n+\t\tu32 ur_d : 1;\n+\t\tu32 fe_d : 1;\n+\t\tu32 nfe_d : 1;\n+\t\tu32 ce_d : 1;\n+\t\tu32 reserved_15_15 : 1;\n+\t\tu32 mrrs : 3;\n+\t\tu32 ns_en : 1;\n+\t\tu32 ap_en : 1;\n+\t\tu32 pf_en : 1;\n+\t\tu32 etf_en : 1;\n+\t\tu32 mps : 3;\n+\t\tu32 ro_en : 1;\n+\t\tu32 ur_en : 1;\n+\t\tu32 fe_en : 1;\n+\t\tu32 nfe_en : 1;\n+\t\tu32 ce_en : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg030_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg030_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg030_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg030_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg030_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg030_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg030_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg030_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg030_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg030_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg030_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg030_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg030_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg030_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg030_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg030_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg030 cvmx_pcieepx_cfg030_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg031\n+ *\n+ * This register contains the thirty-second 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg031 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg031_s {\n+\t\tu32 pnum : 8;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 aspm : 1;\n+\t\tu32 lbnc : 1;\n+\t\tu32 dllarc : 1;\n+\t\tu32 sderc : 1;\n+\t\tu32 cpm : 1;\n+\t\tu32 l1el : 3;\n+\t\tu32 l0el : 3;\n+\t\tu32 aslpms : 2;\n+\t\tu32 mlw : 6;\n+\t\tu32 mls : 4;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg031_cn52xx {\n+\t\tu32 pnum : 8;\n+\t\tu32 reserved_22_23 : 2;\n+\t\tu32 lbnc : 1;\n+\t\tu32 dllarc : 1;\n+\t\tu32 sderc : 1;\n+\t\tu32 cpm : 1;\n+\t\tu32 l1el : 3;\n+\t\tu32 l0el : 3;\n+\t\tu32 aslpms : 2;\n+\t\tu32 mlw : 6;\n+\t\tu32 mls : 4;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg031_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg031_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg031_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg031_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg031_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg031_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg031_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg031_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg031_cn52xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg031_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg031_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg031_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg031_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg031_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg031_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg031_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg031 cvmx_pcieepx_cfg031_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg032\n+ *\n+ * This register contains the thirty-third 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg032 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg032_s {\n+\t\tu32 lab : 1;\n+\t\tu32 lbm : 1;\n+\t\tu32 dlla : 1;\n+\t\tu32 scc : 1;\n+\t\tu32 lt : 1;\n+\t\tu32 reserved_26_26 : 1;\n+\t\tu32 nlw : 6;\n+\t\tu32 ls : 4;\n+\t\tu32 reserved_12_15 : 4;\n+\t\tu32 lab_int_enb : 1;\n+\t\tu32 lbm_int_enb : 1;\n+\t\tu32 hawd : 1;\n+\t\tu32 ecpm : 1;\n+\t\tu32 es : 1;\n+\t\tu32 ccc : 1;\n+\t\tu32 rl : 1;\n+\t\tu32 ld : 1;\n+\t\tu32 rcb : 1;\n+\t\tu32 reserved_2_2 : 1;\n+\t\tu32 aslpc : 2;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg032_cn52xx {\n+\t\tu32 reserved_30_31 : 2;\n+\t\tu32 dlla : 1;\n+\t\tu32 scc : 1;\n+\t\tu32 lt : 1;\n+\t\tu32 reserved_26_26 : 1;\n+\t\tu32 nlw : 6;\n+\t\tu32 ls : 4;\n+\t\tu32 reserved_10_15 : 6;\n+\t\tu32 hawd : 1;\n+\t\tu32 ecpm : 1;\n+\t\tu32 es : 1;\n+\t\tu32 ccc : 1;\n+\t\tu32 rl : 1;\n+\t\tu32 ld : 1;\n+\t\tu32 rcb : 1;\n+\t\tu32 reserved_2_2 : 1;\n+\t\tu32 aslpc : 2;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg032_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg032_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg032_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg032_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg032_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg032_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg032_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg032_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg032_cn68xxp1 {\n+\t\tu32 reserved_30_31 : 2;\n+\t\tu32 dlla : 1;\n+\t\tu32 scc : 1;\n+\t\tu32 lt : 1;\n+\t\tu32 reserved_26_26 : 1;\n+\t\tu32 nlw : 6;\n+\t\tu32 ls : 4;\n+\t\tu32 reserved_12_15 : 4;\n+\t\tu32 lab_int_enb : 1;\n+\t\tu32 lbm_int_enb : 1;\n+\t\tu32 hawd : 1;\n+\t\tu32 ecpm : 1;\n+\t\tu32 es : 1;\n+\t\tu32 ccc : 1;\n+\t\tu32 rl : 1;\n+\t\tu32 ld : 1;\n+\t\tu32 rcb : 1;\n+\t\tu32 reserved_2_2 : 1;\n+\t\tu32 aslpc : 2;\n+\t} cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg032_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg032_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg032_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg032_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg032_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg032_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg032_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg032 cvmx_pcieepx_cfg032_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg033\n+ *\n+ * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 0 config space\n+ * (Slot Capabilities Register)\n+ */\n+union cvmx_pcieepx_cfg033 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg033_s {\n+\t\tu32 ps_num : 13;\n+\t\tu32 nccs : 1;\n+\t\tu32 emip : 1;\n+\t\tu32 sp_ls : 2;\n+\t\tu32 sp_lv : 8;\n+\t\tu32 hp_c : 1;\n+\t\tu32 hp_s : 1;\n+\t\tu32 pip : 1;\n+\t\tu32 aip : 1;\n+\t\tu32 mrlsp : 1;\n+\t\tu32 pcp : 1;\n+\t\tu32 abp : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg033_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg033_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg033_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg033_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg033_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg033_s cn63xxp1;\n+};\n+\n+typedef union cvmx_pcieepx_cfg033 cvmx_pcieepx_cfg033_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg034\n+ *\n+ * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 0 config space\n+ * (Slot Control Register/Slot Status Register)\n+ */\n+union cvmx_pcieepx_cfg034 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg034_s {\n+\t\tu32 reserved_25_31 : 7;\n+\t\tu32 dlls_c : 1;\n+\t\tu32 emis : 1;\n+\t\tu32 pds : 1;\n+\t\tu32 mrlss : 1;\n+\t\tu32 ccint_d : 1;\n+\t\tu32 pd_c : 1;\n+\t\tu32 mrls_c : 1;\n+\t\tu32 pf_d : 1;\n+\t\tu32 abp_d : 1;\n+\t\tu32 reserved_13_15 : 3;\n+\t\tu32 dlls_en : 1;\n+\t\tu32 emic : 1;\n+\t\tu32 pcc : 1;\n+\t\tu32 pic : 2;\n+\t\tu32 aic : 2;\n+\t\tu32 hpint_en : 1;\n+\t\tu32 ccint_en : 1;\n+\t\tu32 pd_en : 1;\n+\t\tu32 mrls_en : 1;\n+\t\tu32 pf_en : 1;\n+\t\tu32 abp_en : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg034_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg034_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg034_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg034_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg034_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg034_s cn63xxp1;\n+};\n+\n+typedef union cvmx_pcieepx_cfg034 cvmx_pcieepx_cfg034_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg037\n+ *\n+ * This register contains the thirty-eighth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg037 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg037_s {\n+\t\tu32 reserved_24_31 : 8;\n+\t\tu32 meetp : 2;\n+\t\tu32 eetps : 1;\n+\t\tu32 effs : 1;\n+\t\tu32 obffs : 2;\n+\t\tu32 reserved_12_17 : 6;\n+\t\tu32 ltrs : 1;\n+\t\tu32 noroprpr : 1;\n+\t\tu32 atom128s : 1;\n+\t\tu32 atom64s : 1;\n+\t\tu32 atom32s : 1;\n+\t\tu32 atom_ops : 1;\n+\t\tu32 ari : 1;\n+\t\tu32 ctds : 1;\n+\t\tu32 ctrs : 4;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg037_cn52xx {\n+\t\tu32 reserved_5_31 : 27;\n+\t\tu32 ctds : 1;\n+\t\tu32 ctrs : 4;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg037_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg037_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg037_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg037_cn61xx {\n+\t\tu32 reserved_14_31 : 18;\n+\t\tu32 tph : 2;\n+\t\tu32 reserved_11_11 : 1;\n+\t\tu32 noroprpr : 1;\n+\t\tu32 atom128s : 1;\n+\t\tu32 atom64s : 1;\n+\t\tu32 atom32s : 1;\n+\t\tu32 atom_ops : 1;\n+\t\tu32 ari : 1;\n+\t\tu32 ctds : 1;\n+\t\tu32 ctrs : 4;\n+\t} cn61xx;\n+\tstruct cvmx_pcieepx_cfg037_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg037_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg037_cn61xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg037_cn61xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg037_cn61xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg037_cn61xx cn70xx;\n+\tstruct cvmx_pcieepx_cfg037_cn61xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg037_cn73xx {\n+\t\tu32 reserved_24_31 : 8;\n+\t\tu32 meetp : 2;\n+\t\tu32 eetps : 1;\n+\t\tu32 effs : 1;\n+\t\tu32 obffs : 2;\n+\t\tu32 reserved_14_17 : 4;\n+\t\tu32 tphs : 2;\n+\t\tu32 ltrs : 1;\n+\t\tu32 noroprpr : 1;\n+\t\tu32 atom128s : 1;\n+\t\tu32 atom64s : 1;\n+\t\tu32 atom32s : 1;\n+\t\tu32 atom_ops : 1;\n+\t\tu32 ari : 1;\n+\t\tu32 ctds : 1;\n+\t\tu32 ctrs : 4;\n+\t} cn73xx;\n+\tstruct cvmx_pcieepx_cfg037_cn73xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg037_cn73xx cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg037_cnf71xx {\n+\t\tu32 reserved_20_31 : 12;\n+\t\tu32 obffs : 2;\n+\t\tu32 reserved_14_17 : 4;\n+\t\tu32 tphs : 2;\n+\t\tu32 ltrs : 1;\n+\t\tu32 noroprpr : 1;\n+\t\tu32 atom128s : 1;\n+\t\tu32 atom64s : 1;\n+\t\tu32 atom32s : 1;\n+\t\tu32 atom_ops : 1;\n+\t\tu32 ari : 1;\n+\t\tu32 ctds : 1;\n+\t\tu32 ctrs : 4;\n+\t} cnf71xx;\n+\tstruct cvmx_pcieepx_cfg037_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg037 cvmx_pcieepx_cfg037_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg038\n+ *\n+ * This register contains the thirty-ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg038 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg038_s {\n+\t\tu32 reserved_16_31 : 16;\n+\t\tu32 eetpb : 1;\n+\t\tu32 obffe : 2;\n+\t\tu32 reserved_11_12 : 2;\n+\t\tu32 ltre : 1;\n+\t\tu32 id0_cp : 1;\n+\t\tu32 id0_rq : 1;\n+\t\tu32 atom_op_eb : 1;\n+\t\tu32 atom_op : 1;\n+\t\tu32 ari : 1;\n+\t\tu32 ctd : 1;\n+\t\tu32 ctv : 4;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg038_cn52xx {\n+\t\tu32 reserved_5_31 : 27;\n+\t\tu32 ctd : 1;\n+\t\tu32 ctv : 4;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg038_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg038_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg038_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg038_cn61xx {\n+\t\tu32 reserved_10_31 : 22;\n+\t\tu32 id0_cp : 1;\n+\t\tu32 id0_rq : 1;\n+\t\tu32 atom_op_eb : 1;\n+\t\tu32 atom_op : 1;\n+\t\tu32 ari : 1;\n+\t\tu32 ctd : 1;\n+\t\tu32 ctv : 4;\n+\t} cn61xx;\n+\tstruct cvmx_pcieepx_cfg038_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg038_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg038_cn61xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg038_cn61xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg038_cn61xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg038_cn61xx cn70xx;\n+\tstruct cvmx_pcieepx_cfg038_cn61xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg038_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg038_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg038_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg038_cnf71xx {\n+\t\tu32 reserved_15_31 : 17;\n+\t\tu32 obffe : 2;\n+\t\tu32 reserved_11_12 : 2;\n+\t\tu32 ltre : 1;\n+\t\tu32 id0_cp : 1;\n+\t\tu32 id0_rq : 1;\n+\t\tu32 atom_op_eb : 1;\n+\t\tu32 atom_op : 1;\n+\t\tu32 ari : 1;\n+\t\tu32 ctd : 1;\n+\t\tu32 ctv : 4;\n+\t} cnf71xx;\n+\tstruct cvmx_pcieepx_cfg038_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg038 cvmx_pcieepx_cfg038_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg039\n+ *\n+ * This register contains the fortieth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg039 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg039_s {\n+\t\tu32 reserved_9_31 : 23;\n+\t\tu32 cls : 1;\n+\t\tu32 slsv : 7;\n+\t\tu32 reserved_0_0 : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg039_cn52xx {\n+\t\tu32 reserved_0_31 : 32;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg039_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg039_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg039_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg039_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg039_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg039_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg039_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg039_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg039_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg039_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg039_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg039_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg039_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg039_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg039_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg039_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg039 cvmx_pcieepx_cfg039_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg040\n+ *\n+ * This register contains the forty-first 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg040 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg040_s {\n+\t\tu32 reserved_22_31 : 10;\n+\t\tu32 ler : 1;\n+\t\tu32 ep3s : 1;\n+\t\tu32 ep2s : 1;\n+\t\tu32 ep1s : 1;\n+\t\tu32 eqc : 1;\n+\t\tu32 cdl : 1;\n+\t\tu32 cde : 4;\n+\t\tu32 csos : 1;\n+\t\tu32 emc : 1;\n+\t\tu32 tm : 3;\n+\t\tu32 sde : 1;\n+\t\tu32 hasd : 1;\n+\t\tu32 ec : 1;\n+\t\tu32 tls : 4;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg040_cn52xx {\n+\t\tu32 reserved_0_31 : 32;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg040_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg040_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg040_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg040_cn61xx {\n+\t\tu32 reserved_17_31 : 15;\n+\t\tu32 cdl : 1;\n+\t\tu32 reserved_13_15 : 3;\n+\t\tu32 cde : 1;\n+\t\tu32 csos : 1;\n+\t\tu32 emc : 1;\n+\t\tu32 tm : 3;\n+\t\tu32 sde : 1;\n+\t\tu32 hasd : 1;\n+\t\tu32 ec : 1;\n+\t\tu32 tls : 4;\n+\t} cn61xx;\n+\tstruct cvmx_pcieepx_cfg040_cn61xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg040_cn61xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg040_cn61xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg040_cn61xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg040_cn61xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg040_cn61xx cn70xx;\n+\tstruct cvmx_pcieepx_cfg040_cn61xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg040_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg040_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg040_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg040_cn61xx cnf71xx;\n+\tstruct cvmx_pcieepx_cfg040_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg040 cvmx_pcieepx_cfg040_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg041\n+ *\n+ * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 0 config space\n+ * (Slot Capabilities 2 Register)\n+ */\n+union cvmx_pcieepx_cfg041 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg041_s {\n+\t\tu32 reserved_0_31 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg041_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg041_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg041_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg041_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg041_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg041_s cn63xxp1;\n+};\n+\n+typedef union cvmx_pcieepx_cfg041 cvmx_pcieepx_cfg041_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg042\n+ *\n+ * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 0 config space\n+ * (Slot Control 2 Register/Slot Status 2 Register)\n+ */\n+union cvmx_pcieepx_cfg042 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg042_s {\n+\t\tu32 reserved_0_31 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg042_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg042_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg042_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg042_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg042_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg042_s cn63xxp1;\n+};\n+\n+typedef union cvmx_pcieepx_cfg042 cvmx_pcieepx_cfg042_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg044\n+ *\n+ * This register contains the forty-fifth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg044 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg044_s {\n+\t\tu32 msixen : 1;\n+\t\tu32 funm : 1;\n+\t\tu32 reserved_27_29 : 3;\n+\t\tu32 msixts : 11;\n+\t\tu32 ncp : 8;\n+\t\tu32 msixcid : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg044_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg044_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg044_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg044_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg044 cvmx_pcieepx_cfg044_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg045\n+ *\n+ * This register contains the forty-sixth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg045 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg045_s {\n+\t\tu32 msixtoffs : 29;\n+\t\tu32 msixtbir : 3;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg045_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg045_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg045_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg045_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg045 cvmx_pcieepx_cfg045_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg046\n+ *\n+ * This register contains the forty-seventh 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg046 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg046_s {\n+\t\tu32 msixpoffs : 29;\n+\t\tu32 msixpbir : 3;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg046_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg046_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg046_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg046_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg046 cvmx_pcieepx_cfg046_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg064\n+ *\n+ * This register contains the sixty-fifth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg064 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg064_s {\n+\t\tu32 nco : 12;\n+\t\tu32 cv : 4;\n+\t\tu32 pcieec : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg064_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg064_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg064_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg064_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg064_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg064_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg064_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg064_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg064_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg064_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg064_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg064_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg064_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg064_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg064_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg064_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg064_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg064 cvmx_pcieepx_cfg064_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg065\n+ *\n+ * This register contains the sixty-sixth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg065 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg065_s {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 tpbes : 1;\n+\t\tu32 uatombs : 1;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 ucies : 1;\n+\t\tu32 reserved_21_21 : 1;\n+\t\tu32 ures : 1;\n+\t\tu32 ecrces : 1;\n+\t\tu32 mtlps : 1;\n+\t\tu32 ros : 1;\n+\t\tu32 ucs : 1;\n+\t\tu32 cas : 1;\n+\t\tu32 cts : 1;\n+\t\tu32 fcpes : 1;\n+\t\tu32 ptlps : 1;\n+\t\tu32 reserved_6_11 : 6;\n+\t\tu32 sdes : 1;\n+\t\tu32 dlpes : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg065_cn52xx {\n+\t\tu32 reserved_21_31 : 11;\n+\t\tu32 ures : 1;\n+\t\tu32 ecrces : 1;\n+\t\tu32 mtlps : 1;\n+\t\tu32 ros : 1;\n+\t\tu32 ucs : 1;\n+\t\tu32 cas : 1;\n+\t\tu32 cts : 1;\n+\t\tu32 fcpes : 1;\n+\t\tu32 ptlps : 1;\n+\t\tu32 reserved_6_11 : 6;\n+\t\tu32 sdes : 1;\n+\t\tu32 dlpes : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg065_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg065_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg065_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg065_cn61xx {\n+\t\tu32 reserved_25_31 : 7;\n+\t\tu32 uatombs : 1;\n+\t\tu32 reserved_21_23 : 3;\n+\t\tu32 ures : 1;\n+\t\tu32 ecrces : 1;\n+\t\tu32 mtlps : 1;\n+\t\tu32 ros : 1;\n+\t\tu32 ucs : 1;\n+\t\tu32 cas : 1;\n+\t\tu32 cts : 1;\n+\t\tu32 fcpes : 1;\n+\t\tu32 ptlps : 1;\n+\t\tu32 reserved_6_11 : 6;\n+\t\tu32 sdes : 1;\n+\t\tu32 dlpes : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn61xx;\n+\tstruct cvmx_pcieepx_cfg065_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg065_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg065_cn61xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg065_cn61xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg065_cn52xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg065_cn70xx {\n+\t\tu32 reserved_25_31 : 7;\n+\t\tu32 uatombs : 1;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 ucies : 1;\n+\t\tu32 reserved_21_21 : 1;\n+\t\tu32 ures : 1;\n+\t\tu32 ecrces : 1;\n+\t\tu32 mtlps : 1;\n+\t\tu32 ros : 1;\n+\t\tu32 ucs : 1;\n+\t\tu32 cas : 1;\n+\t\tu32 cts : 1;\n+\t\tu32 fcpes : 1;\n+\t\tu32 ptlps : 1;\n+\t\tu32 reserved_6_11 : 6;\n+\t\tu32 sdes : 1;\n+\t\tu32 dlpes : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn70xx;\n+\tstruct cvmx_pcieepx_cfg065_cn70xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg065_cn73xx {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 tpbes : 1;\n+\t\tu32 uatombs : 1;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 ucies : 1;\n+\t\tu32 reserved_21_21 : 1;\n+\t\tu32 ures : 1;\n+\t\tu32 ecrces : 1;\n+\t\tu32 mtlps : 1;\n+\t\tu32 ros : 1;\n+\t\tu32 ucs : 1;\n+\t\tu32 cas : 1;\n+\t\tu32 cts : 1;\n+\t\tu32 fcpes : 1;\n+\t\tu32 ptlps : 1;\n+\t\tu32 reserved_5_11 : 7;\n+\t\tu32 dlpes : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn73xx;\n+\tstruct cvmx_pcieepx_cfg065_cn73xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg065_cn73xx cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg065_cnf71xx {\n+\t\tu32 reserved_25_31 : 7;\n+\t\tu32 uatombs : 1;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 ucies : 1;\n+\t\tu32 reserved_21_21 : 1;\n+\t\tu32 ures : 1;\n+\t\tu32 ecrces : 1;\n+\t\tu32 mtlps : 1;\n+\t\tu32 ros : 1;\n+\t\tu32 ucs : 1;\n+\t\tu32 cas : 1;\n+\t\tu32 cts : 1;\n+\t\tu32 fcpes : 1;\n+\t\tu32 ptlps : 1;\n+\t\tu32 reserved_5_11 : 7;\n+\t\tu32 dlpes : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cnf71xx;\n+\tstruct cvmx_pcieepx_cfg065_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg065 cvmx_pcieepx_cfg065_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg066\n+ *\n+ * This register contains the sixty-seventh 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg066 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg066_s {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 tpbem : 1;\n+\t\tu32 uatombm : 1;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 uciem : 1;\n+\t\tu32 reserved_21_21 : 1;\n+\t\tu32 urem : 1;\n+\t\tu32 ecrcem : 1;\n+\t\tu32 mtlpm : 1;\n+\t\tu32 rom : 1;\n+\t\tu32 ucm : 1;\n+\t\tu32 cam : 1;\n+\t\tu32 ctm : 1;\n+\t\tu32 fcpem : 1;\n+\t\tu32 ptlpm : 1;\n+\t\tu32 reserved_6_11 : 6;\n+\t\tu32 sdem : 1;\n+\t\tu32 dlpem : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg066_cn52xx {\n+\t\tu32 reserved_21_31 : 11;\n+\t\tu32 urem : 1;\n+\t\tu32 ecrcem : 1;\n+\t\tu32 mtlpm : 1;\n+\t\tu32 rom : 1;\n+\t\tu32 ucm : 1;\n+\t\tu32 cam : 1;\n+\t\tu32 ctm : 1;\n+\t\tu32 fcpem : 1;\n+\t\tu32 ptlpm : 1;\n+\t\tu32 reserved_6_11 : 6;\n+\t\tu32 sdem : 1;\n+\t\tu32 dlpem : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg066_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg066_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg066_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg066_cn61xx {\n+\t\tu32 reserved_25_31 : 7;\n+\t\tu32 uatombm : 1;\n+\t\tu32 reserved_21_23 : 3;\n+\t\tu32 urem : 1;\n+\t\tu32 ecrcem : 1;\n+\t\tu32 mtlpm : 1;\n+\t\tu32 rom : 1;\n+\t\tu32 ucm : 1;\n+\t\tu32 cam : 1;\n+\t\tu32 ctm : 1;\n+\t\tu32 fcpem : 1;\n+\t\tu32 ptlpm : 1;\n+\t\tu32 reserved_6_11 : 6;\n+\t\tu32 sdem : 1;\n+\t\tu32 dlpem : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn61xx;\n+\tstruct cvmx_pcieepx_cfg066_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg066_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg066_cn61xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg066_cn61xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg066_cn52xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg066_cn70xx {\n+\t\tu32 reserved_25_31 : 7;\n+\t\tu32 uatombm : 1;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 uciem : 1;\n+\t\tu32 reserved_21_21 : 1;\n+\t\tu32 urem : 1;\n+\t\tu32 ecrcem : 1;\n+\t\tu32 mtlpm : 1;\n+\t\tu32 rom : 1;\n+\t\tu32 ucm : 1;\n+\t\tu32 cam : 1;\n+\t\tu32 ctm : 1;\n+\t\tu32 fcpem : 1;\n+\t\tu32 ptlpm : 1;\n+\t\tu32 reserved_6_11 : 6;\n+\t\tu32 sdem : 1;\n+\t\tu32 dlpem : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn70xx;\n+\tstruct cvmx_pcieepx_cfg066_cn70xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg066_cn73xx {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 tpbem : 1;\n+\t\tu32 uatombm : 1;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 uciem : 1;\n+\t\tu32 reserved_21_21 : 1;\n+\t\tu32 urem : 1;\n+\t\tu32 ecrcem : 1;\n+\t\tu32 mtlpm : 1;\n+\t\tu32 rom : 1;\n+\t\tu32 ucm : 1;\n+\t\tu32 cam : 1;\n+\t\tu32 ctm : 1;\n+\t\tu32 fcpem : 1;\n+\t\tu32 ptlpm : 1;\n+\t\tu32 reserved_5_11 : 7;\n+\t\tu32 dlpem : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn73xx;\n+\tstruct cvmx_pcieepx_cfg066_cn73xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg066_cn73xx cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg066_cnf71xx {\n+\t\tu32 reserved_25_31 : 7;\n+\t\tu32 uatombm : 1;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 uciem : 1;\n+\t\tu32 reserved_21_21 : 1;\n+\t\tu32 urem : 1;\n+\t\tu32 ecrcem : 1;\n+\t\tu32 mtlpm : 1;\n+\t\tu32 rom : 1;\n+\t\tu32 ucm : 1;\n+\t\tu32 cam : 1;\n+\t\tu32 ctm : 1;\n+\t\tu32 fcpem : 1;\n+\t\tu32 ptlpm : 1;\n+\t\tu32 reserved_5_11 : 7;\n+\t\tu32 dlpem : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cnf71xx;\n+\tstruct cvmx_pcieepx_cfg066_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg066 cvmx_pcieepx_cfg066_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg067\n+ *\n+ * This register contains the sixty-eighth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg067 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg067_s {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 tpbes : 1;\n+\t\tu32 uatombs : 1;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 ucies : 1;\n+\t\tu32 reserved_21_21 : 1;\n+\t\tu32 ures : 1;\n+\t\tu32 ecrces : 1;\n+\t\tu32 mtlps : 1;\n+\t\tu32 ros : 1;\n+\t\tu32 ucs : 1;\n+\t\tu32 cas : 1;\n+\t\tu32 cts : 1;\n+\t\tu32 fcpes : 1;\n+\t\tu32 ptlps : 1;\n+\t\tu32 reserved_6_11 : 6;\n+\t\tu32 sdes : 1;\n+\t\tu32 dlpes : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg067_cn52xx {\n+\t\tu32 reserved_21_31 : 11;\n+\t\tu32 ures : 1;\n+\t\tu32 ecrces : 1;\n+\t\tu32 mtlps : 1;\n+\t\tu32 ros : 1;\n+\t\tu32 ucs : 1;\n+\t\tu32 cas : 1;\n+\t\tu32 cts : 1;\n+\t\tu32 fcpes : 1;\n+\t\tu32 ptlps : 1;\n+\t\tu32 reserved_6_11 : 6;\n+\t\tu32 sdes : 1;\n+\t\tu32 dlpes : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg067_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg067_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg067_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg067_cn61xx {\n+\t\tu32 reserved_25_31 : 7;\n+\t\tu32 uatombs : 1;\n+\t\tu32 reserved_21_23 : 3;\n+\t\tu32 ures : 1;\n+\t\tu32 ecrces : 1;\n+\t\tu32 mtlps : 1;\n+\t\tu32 ros : 1;\n+\t\tu32 ucs : 1;\n+\t\tu32 cas : 1;\n+\t\tu32 cts : 1;\n+\t\tu32 fcpes : 1;\n+\t\tu32 ptlps : 1;\n+\t\tu32 reserved_6_11 : 6;\n+\t\tu32 sdes : 1;\n+\t\tu32 dlpes : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn61xx;\n+\tstruct cvmx_pcieepx_cfg067_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg067_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg067_cn61xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg067_cn61xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg067_cn52xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg067_cn70xx {\n+\t\tu32 reserved_25_31 : 7;\n+\t\tu32 uatombs : 1;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 ucies : 1;\n+\t\tu32 reserved_21_21 : 1;\n+\t\tu32 ures : 1;\n+\t\tu32 ecrces : 1;\n+\t\tu32 mtlps : 1;\n+\t\tu32 ros : 1;\n+\t\tu32 ucs : 1;\n+\t\tu32 cas : 1;\n+\t\tu32 cts : 1;\n+\t\tu32 fcpes : 1;\n+\t\tu32 ptlps : 1;\n+\t\tu32 reserved_6_11 : 6;\n+\t\tu32 sdes : 1;\n+\t\tu32 dlpes : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn70xx;\n+\tstruct cvmx_pcieepx_cfg067_cn70xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg067_cn73xx {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 tpbes : 1;\n+\t\tu32 uatombs : 1;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 ucies : 1;\n+\t\tu32 reserved_21_21 : 1;\n+\t\tu32 ures : 1;\n+\t\tu32 ecrces : 1;\n+\t\tu32 mtlps : 1;\n+\t\tu32 ros : 1;\n+\t\tu32 ucs : 1;\n+\t\tu32 cas : 1;\n+\t\tu32 cts : 1;\n+\t\tu32 fcpes : 1;\n+\t\tu32 ptlps : 1;\n+\t\tu32 reserved_11_5 : 7;\n+\t\tu32 dlpes : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn73xx;\n+\tstruct cvmx_pcieepx_cfg067_cn73xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg067_cn73xx cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg067_cnf71xx {\n+\t\tu32 reserved_25_31 : 7;\n+\t\tu32 uatombs : 1;\n+\t\tu32 reserved_23_23 : 1;\n+\t\tu32 ucies : 1;\n+\t\tu32 reserved_21_21 : 1;\n+\t\tu32 ures : 1;\n+\t\tu32 ecrces : 1;\n+\t\tu32 mtlps : 1;\n+\t\tu32 ros : 1;\n+\t\tu32 ucs : 1;\n+\t\tu32 cas : 1;\n+\t\tu32 cts : 1;\n+\t\tu32 fcpes : 1;\n+\t\tu32 ptlps : 1;\n+\t\tu32 reserved_5_11 : 7;\n+\t\tu32 dlpes : 1;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cnf71xx;\n+\tstruct cvmx_pcieepx_cfg067_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg067 cvmx_pcieepx_cfg067_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg068\n+ *\n+ * This register contains the sixty-ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg068 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg068_s {\n+\t\tu32 reserved_15_31 : 17;\n+\t\tu32 cies : 1;\n+\t\tu32 anfes : 1;\n+\t\tu32 rtts : 1;\n+\t\tu32 reserved_9_11 : 3;\n+\t\tu32 rnrs : 1;\n+\t\tu32 bdllps : 1;\n+\t\tu32 btlps : 1;\n+\t\tu32 reserved_1_5 : 5;\n+\t\tu32 res : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg068_cn52xx {\n+\t\tu32 reserved_14_31 : 18;\n+\t\tu32 anfes : 1;\n+\t\tu32 rtts : 1;\n+\t\tu32 reserved_9_11 : 3;\n+\t\tu32 rnrs : 1;\n+\t\tu32 bdllps : 1;\n+\t\tu32 btlps : 1;\n+\t\tu32 reserved_1_5 : 5;\n+\t\tu32 res : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg068_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg068_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg068_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg068_cn52xx cn61xx;\n+\tstruct cvmx_pcieepx_cfg068_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg068_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg068_cn52xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg068_cn52xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg068_cn52xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg068_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg068_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg068_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg068_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg068_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg068_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg068_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg068 cvmx_pcieepx_cfg068_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg069\n+ *\n+ * This register contains the seventieth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg069 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg069_s {\n+\t\tu32 reserved_15_31 : 17;\n+\t\tu32 ciem : 1;\n+\t\tu32 anfem : 1;\n+\t\tu32 rttm : 1;\n+\t\tu32 reserved_9_11 : 3;\n+\t\tu32 rnrm : 1;\n+\t\tu32 bdllpm : 1;\n+\t\tu32 btlpm : 1;\n+\t\tu32 reserved_1_5 : 5;\n+\t\tu32 rem : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg069_cn52xx {\n+\t\tu32 reserved_14_31 : 18;\n+\t\tu32 anfem : 1;\n+\t\tu32 rttm : 1;\n+\t\tu32 reserved_9_11 : 3;\n+\t\tu32 rnrm : 1;\n+\t\tu32 bdllpm : 1;\n+\t\tu32 btlpm : 1;\n+\t\tu32 reserved_1_5 : 5;\n+\t\tu32 rem : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg069_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg069_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg069_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg069_cn52xx cn61xx;\n+\tstruct cvmx_pcieepx_cfg069_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg069_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg069_cn52xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg069_cn52xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg069_cn52xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg069_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg069_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg069_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg069_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg069_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg069_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg069_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg069 cvmx_pcieepx_cfg069_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg070\n+ *\n+ * This register contains the seventy-first 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg070 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg070_s {\n+\t\tu32 reserved_12_31 : 20;\n+\t\tu32 tlp_plp : 1;\n+\t\tu32 reserved_9_10 : 2;\n+\t\tu32 ce : 1;\n+\t\tu32 cc : 1;\n+\t\tu32 ge : 1;\n+\t\tu32 gc : 1;\n+\t\tu32 fep : 5;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx {\n+\t\tu32 reserved_9_31 : 23;\n+\t\tu32 ce : 1;\n+\t\tu32 cc : 1;\n+\t\tu32 ge : 1;\n+\t\tu32 gc : 1;\n+\t\tu32 fep : 5;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx cn61xx;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx cn70xx;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg070_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg070_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg070_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg070_cn52xx cnf71xx;\n+\tstruct cvmx_pcieepx_cfg070_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg070 cvmx_pcieepx_cfg070_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg071\n+ *\n+ * This register contains the seventy-second 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg071 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg071_s {\n+\t\tu32 dword1 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg071_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg071_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg071_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg071_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg071_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg071_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg071_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg071_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg071_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg071_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg071_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg071_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg071_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg071_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg071_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg071_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg071_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg071 cvmx_pcieepx_cfg071_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg072\n+ *\n+ * This register contains the seventy-third 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg072 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg072_s {\n+\t\tu32 dword2 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg072_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg072_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg072_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg072_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg072_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg072_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg072_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg072_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg072_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg072_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg072_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg072_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg072_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg072_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg072_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg072_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg072_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg072 cvmx_pcieepx_cfg072_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg073\n+ *\n+ * This register contains the seventy-fourth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg073 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg073_s {\n+\t\tu32 dword3 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg073_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg073_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg073_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg073_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg073_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg073_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg073_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg073_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg073_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg073_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg073_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg073_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg073_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg073_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg073_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg073_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg073_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg073 cvmx_pcieepx_cfg073_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg074\n+ *\n+ * This register contains the seventy-fifth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg074 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg074_s {\n+\t\tu32 dword4 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg074_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg074_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg074_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg074_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg074_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg074_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg074_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg074_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg074_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg074_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg074_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg074_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg074_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg074_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg074_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg074_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg074_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg074 cvmx_pcieepx_cfg074_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg078\n+ *\n+ * This register contains the seventy-ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg078 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg078_s {\n+\t\tu32 tlp_pfx_log : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg078_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg078_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg078_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg078_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg078 cvmx_pcieepx_cfg078_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg082\n+ *\n+ * This register contains the eighty-third 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg082 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg082_s {\n+\t\tu32 nco : 12;\n+\t\tu32 cv : 4;\n+\t\tu32 reserved_0_15 : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg082_cn70xx {\n+\t\tu32 nco : 12;\n+\t\tu32 cv : 4;\n+\t\tu32 pcieec : 16;\n+\t} cn70xx;\n+\tstruct cvmx_pcieepx_cfg082_cn70xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg082_cn73xx {\n+\t\tu32 nco : 12;\n+\t\tu32 cv : 4;\n+\t\tu32 ariid : 16;\n+\t} cn73xx;\n+\tstruct cvmx_pcieepx_cfg082_cn73xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg082_cn73xx cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg082_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg082 cvmx_pcieepx_cfg082_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg083\n+ *\n+ * This register contains the eighty-fourth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg083 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg083_s {\n+\t\tu32 reserved_2_31 : 30;\n+\t\tu32 acsfgc : 1;\n+\t\tu32 mfvcfgc : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg083_cn70xx {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 srs : 22;\n+\t\tu32 reserved_0_3 : 4;\n+\t} cn70xx;\n+\tstruct cvmx_pcieepx_cfg083_cn70xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg083_cn73xx {\n+\t\tu32 reserved_23_31 : 9;\n+\t\tu32 fg : 3;\n+\t\tu32 reserved_18_19 : 2;\n+\t\tu32 acsfge : 1;\n+\t\tu32 mfvcfge : 1;\n+\t\tu32 nfn : 8;\n+\t\tu32 reserved_2_7 : 6;\n+\t\tu32 acsfgc : 1;\n+\t\tu32 mfvcfgc : 1;\n+\t} cn73xx;\n+\tstruct cvmx_pcieepx_cfg083_cn73xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg083_cn73xx cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg083_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg083 cvmx_pcieepx_cfg083_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg084\n+ *\n+ * PCIE_CFG084 = Eighty-fifth 32-bits of PCIE type 0 config space\n+ * (PCI Express Resizable BAR (RBAR) Control Register)\n+ */\n+union cvmx_pcieepx_cfg084 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg084_s {\n+\t\tu32 reserved_13_31 : 19;\n+\t\tu32 rbars : 5;\n+\t\tu32 nrbar : 3;\n+\t\tu32 reserved_3_4 : 2;\n+\t\tu32 rbari : 3;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg084_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg084_s cn70xxp1;\n+};\n+\n+typedef union cvmx_pcieepx_cfg084 cvmx_pcieepx_cfg084_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg086\n+ *\n+ * This register contains the eighty-seventh 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg086 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg086_s {\n+\t\tu32 nco : 12;\n+\t\tu32 cv : 4;\n+\t\tu32 pcieec : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg086_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg086_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg086_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg086_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg086 cvmx_pcieepx_cfg086_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg087\n+ *\n+ * This register contains the eighty-eighth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg087 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg087_s {\n+\t\tu32 reserved_0_31 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg087_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg087_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg087_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg087_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg087 cvmx_pcieepx_cfg087_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg088\n+ *\n+ * This register contains the eighty-ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg088 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg088_s {\n+\t\tu32 reserved_8_31 : 24;\n+\t\tu32 les : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg088_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg088_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg088_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg088_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg088 cvmx_pcieepx_cfg088_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg089\n+ *\n+ * This register contains the ninetieth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg089 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg089_s {\n+\t\tu32 reserved_31_31 : 1;\n+\t\tu32 l1dph : 3;\n+\t\tu32 l1dtp : 4;\n+\t\tu32 reserved_15_23 : 9;\n+\t\tu32 l0dph : 3;\n+\t\tu32 l0dtp : 4;\n+\t\tu32 reserved_0_7 : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg089_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg089_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg089_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg089_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg089 cvmx_pcieepx_cfg089_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg090\n+ *\n+ * This register contains the ninety-first 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg090 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg090_s {\n+\t\tu32 reserved_31_31 : 1;\n+\t\tu32 l3dph : 3;\n+\t\tu32 l3dtp : 4;\n+\t\tu32 reserved_15_23 : 9;\n+\t\tu32 l2dph : 3;\n+\t\tu32 l2dtp : 4;\n+\t\tu32 reserved_0_7 : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg090_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg090_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg090_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg090_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg090 cvmx_pcieepx_cfg090_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg091\n+ *\n+ * This register contains the ninety-second 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg091 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg091_s {\n+\t\tu32 reserved_31_31 : 1;\n+\t\tu32 l5dph : 3;\n+\t\tu32 l5dtp : 4;\n+\t\tu32 reserved_15_23 : 9;\n+\t\tu32 l4dph : 3;\n+\t\tu32 l4dtp : 4;\n+\t\tu32 reserved_0_7 : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg091_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg091_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg091_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg091_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg091 cvmx_pcieepx_cfg091_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg092\n+ *\n+ * This register contains the ninety-fourth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg092 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg092_s {\n+\t\tu32 reserved_31_31 : 1;\n+\t\tu32 l7dph : 3;\n+\t\tu32 l7dtp : 4;\n+\t\tu32 reserved_15_23 : 9;\n+\t\tu32 l6dph : 3;\n+\t\tu32 l6dtp : 4;\n+\t\tu32 reserved_0_7 : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg092_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg092_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg092_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg092_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg092 cvmx_pcieepx_cfg092_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg094\n+ *\n+ * This register contains the ninety-fifth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg094 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg094_s {\n+\t\tu32 nco : 12;\n+\t\tu32 cv : 4;\n+\t\tu32 pcieec : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg094_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg094_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg094_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg094_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg094 cvmx_pcieepx_cfg094_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg095\n+ *\n+ * This register contains the ninety-sixth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg095 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg095_s {\n+\t\tu32 vfmimn : 11;\n+\t\tu32 reserved_2_20 : 19;\n+\t\tu32 arichp : 1;\n+\t\tu32 vfmc : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg095_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg095_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg095_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg095_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg095 cvmx_pcieepx_cfg095_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg096\n+ *\n+ * This register contains the ninety-seventh 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg096 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg096_s {\n+\t\tu32 reserved_17_31 : 15;\n+\t\tu32 ms : 1;\n+\t\tu32 reserved_5_15 : 11;\n+\t\tu32 ach : 1;\n+\t\tu32 mse : 1;\n+\t\tu32 mie : 1;\n+\t\tu32 me : 1;\n+\t\tu32 vfe : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg096_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg096_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg096_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg096_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg096 cvmx_pcieepx_cfg096_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg097\n+ *\n+ * This register contains the ninety-eighth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg097 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg097_s {\n+\t\tu32 tvf : 16;\n+\t\tu32 ivf : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg097_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg097_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg097_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg097_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg097 cvmx_pcieepx_cfg097_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg098\n+ *\n+ * This register contains the ninety-ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg098 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg098_s {\n+\t\tu32 reserved_24_31 : 8;\n+\t\tu32 fdl : 8;\n+\t\tu32 nvf : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg098_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg098_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg098_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg098_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg098 cvmx_pcieepx_cfg098_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg099\n+ *\n+ * This register contains the one hundredth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg099 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg099_s {\n+\t\tu32 vfs : 16;\n+\t\tu32 fo : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg099_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg099_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg099_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg099_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg099 cvmx_pcieepx_cfg099_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg100\n+ *\n+ * This register contains the one hundred first 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg100 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg100_s {\n+\t\tu32 vfdev : 16;\n+\t\tu32 reserved_0_15 : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg100_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg100_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg100_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg100_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg100 cvmx_pcieepx_cfg100_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg101\n+ *\n+ * This register contains the one hundred second 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg101 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg101_s {\n+\t\tu32 supps : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg101_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg101_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg101_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg101_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg101 cvmx_pcieepx_cfg101_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg102\n+ *\n+ * This register contains the one hundred third 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg102 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg102_s {\n+\t\tu32 ps : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg102_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg102_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg102_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg102_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg102 cvmx_pcieepx_cfg102_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg103\n+ *\n+ * This register contains the one hundred fourth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg103 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg103_s {\n+\t\tu32 reserved_4_31 : 28;\n+\t\tu32 pf : 1;\n+\t\tu32 typ : 2;\n+\t\tu32 mspc : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg103_cn73xx {\n+\t\tu32 lbab : 12;\n+\t\tu32 reserved_4_19 : 16;\n+\t\tu32 pf : 1;\n+\t\tu32 typ : 2;\n+\t\tu32 mspc : 1;\n+\t} cn73xx;\n+\tstruct cvmx_pcieepx_cfg103_cn73xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg103_cn78xxp1 {\n+\t\tu32 lbab : 17;\n+\t\tu32 reserved_4_14 : 11;\n+\t\tu32 pf : 1;\n+\t\tu32 typ : 2;\n+\t\tu32 mspc : 1;\n+\t} cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg103_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg103 cvmx_pcieepx_cfg103_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg104\n+ *\n+ * This register contains the one hundred seventh 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg104 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg104_s {\n+\t\tu32 ubab : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg104_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg104_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg104_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg104_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg104 cvmx_pcieepx_cfg104_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg105\n+ *\n+ * This register contains the one hundred sixth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg105 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg105_s {\n+\t\tu32 reserved_0_31 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg105_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg105_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg105_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg105_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg105 cvmx_pcieepx_cfg105_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg106\n+ *\n+ * This register contains the one hundred seventh 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg106 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg106_s {\n+\t\tu32 reserved_0_31 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg106_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg106_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg106_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg106_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg106 cvmx_pcieepx_cfg106_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg107\n+ *\n+ * This register contains the one hundred eighth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg107 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg107_s {\n+\t\tu32 reserved_0_31 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg107_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg107_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg107_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg107_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg107 cvmx_pcieepx_cfg107_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg108\n+ *\n+ * This register contains the one hundred ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg108 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg108_s {\n+\t\tu32 reserved_0_31 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg108_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg108_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg108_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg108_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg108 cvmx_pcieepx_cfg108_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg109\n+ *\n+ * This register contains the one hundred tenth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg109 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg109_s {\n+\t\tu32 mso : 29;\n+\t\tu32 msbir : 3;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg109_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg109_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg109_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg109_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg109 cvmx_pcieepx_cfg109_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg110\n+ *\n+ * This register contains the one hundred eleventh 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg110 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg110_s {\n+\t\tu32 nco : 12;\n+\t\tu32 cv : 4;\n+\t\tu32 pcieec : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg110_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg110_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg110_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg110_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg110 cvmx_pcieepx_cfg110_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg111\n+ *\n+ * This register contains the one hundred twelfth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg111 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg111_s {\n+\t\tu32 reserved_30_31 : 2;\n+\t\tu32 srs : 26;\n+\t\tu32 reserved_0_3 : 4;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg111_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg111_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg111_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg111_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg111 cvmx_pcieepx_cfg111_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg112\n+ *\n+ * This register contains the one hundred thirteenth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg112 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg112_s {\n+\t\tu32 reserved_13_31 : 19;\n+\t\tu32 rbars : 5;\n+\t\tu32 nrbar : 3;\n+\t\tu32 reserved_3_4 : 2;\n+\t\tu32 rbari : 3;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg112_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg112_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg112_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg112_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg112 cvmx_pcieepx_cfg112_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg448\n+ *\n+ * This register contains the four hundred forty-ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg448 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg448_s {\n+\t\tu32 rtl : 16;\n+\t\tu32 rtltl : 16;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg448_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg448_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg448_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg448_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg448_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg448_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg448_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg448_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg448_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg448_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg448_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg448_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg448_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg448_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg448_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg448_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg448_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg448 cvmx_pcieepx_cfg448_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg449\n+ *\n+ * This register contains the four hundred fiftieth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg449 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg449_s {\n+\t\tu32 omr : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg449_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg449_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg449_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg449_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg449_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg449_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg449_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg449_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg449_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg449_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg449_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg449_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg449_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg449_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg449_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg449_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg449_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg449 cvmx_pcieepx_cfg449_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg450\n+ *\n+ * This register contains the four hundred fifty-first 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg450 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg450_s {\n+\t\tu32 lpec : 8;\n+\t\tu32 reserved_22_23 : 2;\n+\t\tu32 link_state : 6;\n+\t\tu32 force_link : 1;\n+\t\tu32 reserved_8_14 : 7;\n+\t\tu32 link_num : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg450_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg450_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg450_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg450_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg450_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg450_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg450_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg450_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg450_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg450_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg450_cn70xx {\n+\t\tu32 lpec : 8;\n+\t\tu32 reserved_22_23 : 2;\n+\t\tu32 link_state : 6;\n+\t\tu32 force_link : 1;\n+\t\tu32 reserved_12_14 : 3;\n+\t\tu32 link_cmd : 4;\n+\t\tu32 link_num : 8;\n+\t} cn70xx;\n+\tstruct cvmx_pcieepx_cfg450_cn70xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg450_cn73xx {\n+\t\tu32 lpec : 8;\n+\t\tu32 reserved_22_23 : 2;\n+\t\tu32 link_state : 6;\n+\t\tu32 force_link : 1;\n+\t\tu32 reserved_12_14 : 3;\n+\t\tu32 forced_ltssm : 4;\n+\t\tu32 link_num : 8;\n+\t} cn73xx;\n+\tstruct cvmx_pcieepx_cfg450_cn73xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg450_cn73xx cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg450_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg450_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg450 cvmx_pcieepx_cfg450_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg451\n+ *\n+ * This register contains the four hundred fifty-second 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg451 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg451_s {\n+\t\tu32 reserved_31_31 : 1;\n+\t\tu32 easpml1 : 1;\n+\t\tu32 l1el : 3;\n+\t\tu32 l0el : 3;\n+\t\tu32 n_fts_cc : 8;\n+\t\tu32 n_fts : 8;\n+\t\tu32 ack_freq : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg451_cn52xx {\n+\t\tu32 reserved_30_31 : 2;\n+\t\tu32 l1el : 3;\n+\t\tu32 l0el : 3;\n+\t\tu32 n_fts_cc : 8;\n+\t\tu32 n_fts : 8;\n+\t\tu32 ack_freq : 8;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg451_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg451_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg451_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg451_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg451_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg451_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg451_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg451_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg451_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg451_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg451_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg451_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg451_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg451_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg451_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg451_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg451 cvmx_pcieepx_cfg451_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg452\n+ *\n+ * This register contains the four hundred fifty-third 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg452 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg452_s {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 eccrc : 1;\n+\t\tu32 reserved_22_24 : 3;\n+\t\tu32 lme : 6;\n+\t\tu32 reserved_12_15 : 4;\n+\t\tu32 link_rate : 4;\n+\t\tu32 flm : 1;\n+\t\tu32 reserved_6_6 : 1;\n+\t\tu32 dllle : 1;\n+\t\tu32 reserved_4_4 : 1;\n+\t\tu32 ra : 1;\n+\t\tu32 le : 1;\n+\t\tu32 sd : 1;\n+\t\tu32 omr : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg452_cn52xx {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 eccrc : 1;\n+\t\tu32 reserved_22_24 : 3;\n+\t\tu32 lme : 6;\n+\t\tu32 reserved_8_15 : 8;\n+\t\tu32 flm : 1;\n+\t\tu32 reserved_6_6 : 1;\n+\t\tu32 dllle : 1;\n+\t\tu32 reserved_4_4 : 1;\n+\t\tu32 ra : 1;\n+\t\tu32 le : 1;\n+\t\tu32 sd : 1;\n+\t\tu32 omr : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg452_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg452_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg452_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg452_cn61xx {\n+\t\tu32 reserved_22_31 : 10;\n+\t\tu32 lme : 6;\n+\t\tu32 reserved_8_15 : 8;\n+\t\tu32 flm : 1;\n+\t\tu32 reserved_6_6 : 1;\n+\t\tu32 dllle : 1;\n+\t\tu32 reserved_4_4 : 1;\n+\t\tu32 ra : 1;\n+\t\tu32 le : 1;\n+\t\tu32 sd : 1;\n+\t\tu32 omr : 1;\n+\t} cn61xx;\n+\tstruct cvmx_pcieepx_cfg452_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg452_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg452_cn61xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg452_cn61xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg452_cn61xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg452_cn70xx {\n+\t\tu32 reserved_22_31 : 10;\n+\t\tu32 lme : 6;\n+\t\tu32 reserved_12_15 : 4;\n+\t\tu32 link_rate : 4;\n+\t\tu32 flm : 1;\n+\t\tu32 reserved_6_6 : 1;\n+\t\tu32 dllle : 1;\n+\t\tu32 reserved_4_4 : 1;\n+\t\tu32 ra : 1;\n+\t\tu32 le : 1;\n+\t\tu32 sd : 1;\n+\t\tu32 omr : 1;\n+\t} cn70xx;\n+\tstruct cvmx_pcieepx_cfg452_cn70xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg452_cn70xx cn73xx;\n+\tstruct cvmx_pcieepx_cfg452_cn70xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg452_cn70xx cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg452_cn61xx cnf71xx;\n+\tstruct cvmx_pcieepx_cfg452_cn70xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg452 cvmx_pcieepx_cfg452_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg453\n+ *\n+ * This register contains the four hundred fifty-fourth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg453 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg453_s {\n+\t\tu32 dlld : 1;\n+\t\tu32 reserved_26_30 : 5;\n+\t\tu32 ack_nak : 1;\n+\t\tu32 fcd : 1;\n+\t\tu32 ilst : 24;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg453_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg453_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg453_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg453_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg453_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg453_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg453_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg453_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg453_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg453_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg453_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg453_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg453_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg453_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg453_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg453_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg453_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg453 cvmx_pcieepx_cfg453_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg454\n+ *\n+ * This register contains the four hundred fifty-fifth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg454 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg454_s {\n+\t\tu32 cx_nfunc : 3;\n+\t\tu32 tmfcwt : 5;\n+\t\tu32 tmanlt : 5;\n+\t\tu32 tmrt : 5;\n+\t\tu32 reserved_11_13 : 3;\n+\t\tu32 nskps : 3;\n+\t\tu32 reserved_0_7 : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg454_cn52xx {\n+\t\tu32 reserved_29_31 : 3;\n+\t\tu32 tmfcwt : 5;\n+\t\tu32 tmanlt : 5;\n+\t\tu32 tmrt : 5;\n+\t\tu32 reserved_11_13 : 3;\n+\t\tu32 nskps : 3;\n+\t\tu32 reserved_4_7 : 4;\n+\t\tu32 ntss : 4;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg454_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg454_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg454_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg454_cn61xx {\n+\t\tu32 cx_nfunc : 3;\n+\t\tu32 tmfcwt : 5;\n+\t\tu32 tmanlt : 5;\n+\t\tu32 tmrt : 5;\n+\t\tu32 reserved_8_13 : 6;\n+\t\tu32 mfuncn : 8;\n+\t} cn61xx;\n+\tstruct cvmx_pcieepx_cfg454_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg454_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg454_cn61xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg454_cn61xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg454_cn52xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg454_cn70xx {\n+\t\tu32 reserved_24_31 : 8;\n+\t\tu32 tmanlt : 5;\n+\t\tu32 tmrt : 5;\n+\t\tu32 reserved_8_13 : 6;\n+\t\tu32 mfuncn : 8;\n+\t} cn70xx;\n+\tstruct cvmx_pcieepx_cfg454_cn70xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg454_cn73xx {\n+\t\tu32 reserved_29_31 : 3;\n+\t\tu32 tmfcwt : 5;\n+\t\tu32 tmanlt : 5;\n+\t\tu32 tmrt : 5;\n+\t\tu32 reserved_8_13 : 6;\n+\t\tu32 mfuncn : 8;\n+\t} cn73xx;\n+\tstruct cvmx_pcieepx_cfg454_cn73xx cn78xx;\n+\tstruct cvmx_pcieepx_cfg454_cn73xx cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg454_cn61xx cnf71xx;\n+\tstruct cvmx_pcieepx_cfg454_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg454 cvmx_pcieepx_cfg454_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg455\n+ *\n+ * This register contains the four hundred fifty-sixth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg455 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg455_s {\n+\t\tu32 m_cfg0_filt : 1;\n+\t\tu32 m_io_filt : 1;\n+\t\tu32 msg_ctrl : 1;\n+\t\tu32 m_cpl_ecrc_filt : 1;\n+\t\tu32 m_ecrc_filt : 1;\n+\t\tu32 m_cpl_len_err : 1;\n+\t\tu32 m_cpl_attr_err : 1;\n+\t\tu32 m_cpl_tc_err : 1;\n+\t\tu32 m_cpl_fun_err : 1;\n+\t\tu32 m_cpl_rid_err : 1;\n+\t\tu32 m_cpl_tag_err : 1;\n+\t\tu32 m_lk_filt : 1;\n+\t\tu32 m_cfg1_filt : 1;\n+\t\tu32 m_bar_match : 1;\n+\t\tu32 m_pois_filt : 1;\n+\t\tu32 m_fun : 1;\n+\t\tu32 dfcwt : 1;\n+\t\tu32 reserved_11_14 : 4;\n+\t\tu32 skpiv : 11;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg455_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg455_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg455_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg455_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg455_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg455_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg455_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg455_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg455_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg455_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg455_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg455_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg455_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg455_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg455_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg455_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg455_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg455 cvmx_pcieepx_cfg455_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg456\n+ *\n+ * This register contains the four hundred fifty-seventh 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg456 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg456_s {\n+\t\tu32 reserved_4_31 : 28;\n+\t\tu32 m_handle_flush : 1;\n+\t\tu32 m_dabort_4ucpl : 1;\n+\t\tu32 m_vend1_drp : 1;\n+\t\tu32 m_vend0_drp : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg456_cn52xx {\n+\t\tu32 reserved_2_31 : 30;\n+\t\tu32 m_vend1_drp : 1;\n+\t\tu32 m_vend0_drp : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg456_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg456_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg456_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg456_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg456_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg456_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg456_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg456_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg456_cn52xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg456_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg456_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg456_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg456_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg456_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg456_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg456_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg456 cvmx_pcieepx_cfg456_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg458\n+ *\n+ * This register contains the four hundred fifty-ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg458 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg458_s {\n+\t\tu32 dbg_info_l32 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg458_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg458_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg458_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg458_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg458_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg458_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg458_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg458_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg458_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg458_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg458_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg458_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg458_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg458_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg458_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg458_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg458_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg458 cvmx_pcieepx_cfg458_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg459\n+ *\n+ * This register contains the four hundred sixtieth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg459 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg459_s {\n+\t\tu32 dbg_info_u32 : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg459_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg459_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg459_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg459_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg459_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg459_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg459_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg459_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg459_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg459_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg459_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg459_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg459_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg459_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg459_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg459_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg459_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg459 cvmx_pcieepx_cfg459_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg460\n+ *\n+ * This register contains the four hundred sixty-first 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg460 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg460_s {\n+\t\tu32 reserved_20_31 : 12;\n+\t\tu32 tphfcc : 8;\n+\t\tu32 tpdfcc : 12;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg460_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg460_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg460_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg460_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg460_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg460_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg460_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg460_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg460_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg460_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg460_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg460_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg460_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg460_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg460_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg460_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg460_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg460 cvmx_pcieepx_cfg460_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg461\n+ *\n+ * This register contains the four hundred sixty-second 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg461 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg461_s {\n+\t\tu32 reserved_20_31 : 12;\n+\t\tu32 tchfcc : 8;\n+\t\tu32 tcdfcc : 12;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg461_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg461_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg461_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg461_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg461_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg461_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg461_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg461_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg461_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg461_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg461_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg461_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg461_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg461_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg461_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg461_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg461_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg461 cvmx_pcieepx_cfg461_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg462\n+ *\n+ * This register contains the four hundred sixty-third 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg462 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg462_s {\n+\t\tu32 reserved_20_31 : 12;\n+\t\tu32 tchfcc : 8;\n+\t\tu32 tcdfcc : 12;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg462_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg462_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg462_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg462_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg462_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg462_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg462_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg462_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg462_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg462_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg462_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg462_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg462_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg462_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg462_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg462_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg462_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg462 cvmx_pcieepx_cfg462_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg463\n+ *\n+ * This register contains the four hundred sixty-fourth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg463 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg463_s {\n+\t\tu32 fcltoe : 1;\n+\t\tu32 reserved_29_30 : 2;\n+\t\tu32 fcltov : 13;\n+\t\tu32 reserved_3_15 : 13;\n+\t\tu32 rqne : 1;\n+\t\tu32 trbne : 1;\n+\t\tu32 rtlpfccnr : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx {\n+\t\tu32 reserved_3_31 : 29;\n+\t\tu32 rqne : 1;\n+\t\tu32 trbne : 1;\n+\t\tu32 rtlpfccnr : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx cn56xx;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx cn61xx;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx cn70xx;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg463_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg463_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg463_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg463_cn52xx cnf71xx;\n+\tstruct cvmx_pcieepx_cfg463_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg463 cvmx_pcieepx_cfg463_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg464\n+ *\n+ * This register contains the four hundred sixty-fifth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg464 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg464_s {\n+\t\tu32 wrr_vc3 : 8;\n+\t\tu32 wrr_vc2 : 8;\n+\t\tu32 wrr_vc1 : 8;\n+\t\tu32 wrr_vc0 : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg464_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg464_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg464_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg464_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg464_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg464_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg464_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg464_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg464_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg464_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg464_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg464_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg464_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg464_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg464_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg464_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg464_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg464 cvmx_pcieepx_cfg464_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg465\n+ *\n+ * This register contains the four hundred sixty-sixth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg465 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg465_s {\n+\t\tu32 wrr_vc7 : 8;\n+\t\tu32 wrr_vc6 : 8;\n+\t\tu32 wrr_vc5 : 8;\n+\t\tu32 wrr_vc4 : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg465_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg465_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg465_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg465_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg465_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg465_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg465_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg465_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg465_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg465_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg465_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg465_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg465_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg465_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg465_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg465_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg465_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg465 cvmx_pcieepx_cfg465_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg466\n+ *\n+ * This register contains the four hundred sixty-seventh 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg466 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg466_s {\n+\t\tu32 rx_queue_order : 1;\n+\t\tu32 type_ordering : 1;\n+\t\tu32 reserved_24_29 : 6;\n+\t\tu32 queue_mode : 3;\n+\t\tu32 reserved_20_20 : 1;\n+\t\tu32 header_credits : 8;\n+\t\tu32 data_credits : 12;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg466_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg466_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg466_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg466_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg466_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg466_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg466_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg466_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg466_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg466_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg466_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg466_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg466_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg466_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg466_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg466_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg466_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg466 cvmx_pcieepx_cfg466_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg467\n+ *\n+ * This register contains the four hundred sixty-eighth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg467 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg467_s {\n+\t\tu32 reserved_24_31 : 8;\n+\t\tu32 queue_mode : 3;\n+\t\tu32 reserved_20_20 : 1;\n+\t\tu32 header_credits : 8;\n+\t\tu32 data_credits : 12;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg467_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg467_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg467_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg467_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg467_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg467_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg467_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg467_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg467_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg467_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg467_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg467_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg467_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg467_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg467_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg467_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg467_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg467 cvmx_pcieepx_cfg467_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg468\n+ *\n+ * This register contains the four hundred sixty-ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg468 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg468_s {\n+\t\tu32 reserved_24_31 : 8;\n+\t\tu32 queue_mode : 3;\n+\t\tu32 reserved_20_20 : 1;\n+\t\tu32 header_credits : 8;\n+\t\tu32 data_credits : 12;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg468_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg468_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg468_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg468_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg468_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg468_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg468_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg468_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg468_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg468_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg468_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg468_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg468_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg468_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg468_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg468_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg468_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg468 cvmx_pcieepx_cfg468_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg490\n+ *\n+ * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 0 config space\n+ * (VC0 Posted Buffer Depth)\n+ */\n+union cvmx_pcieepx_cfg490 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg490_s {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 header_depth : 10;\n+\t\tu32 reserved_14_15 : 2;\n+\t\tu32 data_depth : 14;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg490_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg490_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg490_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg490_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg490_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg490_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg490_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg490_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg490_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg490_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg490_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg490_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg490_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg490 cvmx_pcieepx_cfg490_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg491\n+ *\n+ * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 0 config space\n+ * (VC0 Non-Posted Buffer Depth)\n+ */\n+union cvmx_pcieepx_cfg491 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg491_s {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 header_depth : 10;\n+\t\tu32 reserved_14_15 : 2;\n+\t\tu32 data_depth : 14;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg491_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg491_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg491_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg491_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg491_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg491_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg491_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg491_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg491_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg491_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg491_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg491_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg491_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg491 cvmx_pcieepx_cfg491_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg492\n+ *\n+ * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 0 config space\n+ * (VC0 Completion Buffer Depth)\n+ */\n+union cvmx_pcieepx_cfg492 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg492_s {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 header_depth : 10;\n+\t\tu32 reserved_14_15 : 2;\n+\t\tu32 data_depth : 14;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg492_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg492_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg492_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg492_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg492_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg492_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg492_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg492_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg492_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg492_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg492_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg492_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg492_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg492 cvmx_pcieepx_cfg492_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg515\n+ *\n+ * This register contains the five hundred sixteenth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg515 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg515_s {\n+\t\tu32 reserved_21_31 : 11;\n+\t\tu32 s_d_e : 1;\n+\t\tu32 ctcrb : 1;\n+\t\tu32 cpyts : 1;\n+\t\tu32 dsc : 1;\n+\t\tu32 reserved_8_16 : 9;\n+\t\tu32 n_fts : 8;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg515_cn61xx {\n+\t\tu32 reserved_21_31 : 11;\n+\t\tu32 s_d_e : 1;\n+\t\tu32 ctcrb : 1;\n+\t\tu32 cpyts : 1;\n+\t\tu32 dsc : 1;\n+\t\tu32 le : 9;\n+\t\tu32 n_fts : 8;\n+\t} cn61xx;\n+\tstruct cvmx_pcieepx_cfg515_cn61xx cn63xx;\n+\tstruct cvmx_pcieepx_cfg515_cn61xx cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg515_cn61xx cn66xx;\n+\tstruct cvmx_pcieepx_cfg515_cn61xx cn68xx;\n+\tstruct cvmx_pcieepx_cfg515_cn61xx cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg515_cn61xx cn70xx;\n+\tstruct cvmx_pcieepx_cfg515_cn61xx cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg515_cn61xx cn73xx;\n+\tstruct cvmx_pcieepx_cfg515_cn78xx {\n+\t\tu32 reserved_21_31 : 11;\n+\t\tu32 s_d_e : 1;\n+\t\tu32 ctcrb : 1;\n+\t\tu32 cpyts : 1;\n+\t\tu32 dsc : 1;\n+\t\tu32 alaneflip : 1;\n+\t\tu32 pdetlane : 3;\n+\t\tu32 nlanes : 5;\n+\t\tu32 n_fts : 8;\n+\t} cn78xx;\n+\tstruct cvmx_pcieepx_cfg515_cn61xx cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg515_cn61xx cnf71xx;\n+\tstruct cvmx_pcieepx_cfg515_cn78xx cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg515 cvmx_pcieepx_cfg515_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg516\n+ *\n+ * This register contains the five hundred seventeenth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg516 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg516_s {\n+\t\tu32 phy_stat : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg516_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg516_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg516_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg516_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg516_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg516_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg516_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg516_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg516_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg516_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg516_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg516_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg516_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg516_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg516_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg516_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg516_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg516 cvmx_pcieepx_cfg516_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg517\n+ *\n+ * This register contains the five hundred eighteenth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg517 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg517_s {\n+\t\tu32 phy_ctrl : 32;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg517_s cn52xx;\n+\tstruct cvmx_pcieepx_cfg517_s cn52xxp1;\n+\tstruct cvmx_pcieepx_cfg517_s cn56xx;\n+\tstruct cvmx_pcieepx_cfg517_s cn56xxp1;\n+\tstruct cvmx_pcieepx_cfg517_s cn61xx;\n+\tstruct cvmx_pcieepx_cfg517_s cn63xx;\n+\tstruct cvmx_pcieepx_cfg517_s cn63xxp1;\n+\tstruct cvmx_pcieepx_cfg517_s cn66xx;\n+\tstruct cvmx_pcieepx_cfg517_s cn68xx;\n+\tstruct cvmx_pcieepx_cfg517_s cn68xxp1;\n+\tstruct cvmx_pcieepx_cfg517_s cn70xx;\n+\tstruct cvmx_pcieepx_cfg517_s cn70xxp1;\n+\tstruct cvmx_pcieepx_cfg517_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg517_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg517_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg517_s cnf71xx;\n+\tstruct cvmx_pcieepx_cfg517_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg517 cvmx_pcieepx_cfg517_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg548\n+ *\n+ * This register contains the five hundred forty-ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg548 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg548_s {\n+\t\tu32 reserved_26_31 : 6;\n+\t\tu32 rss : 2;\n+\t\tu32 eiedd : 1;\n+\t\tu32 reserved_19_22 : 4;\n+\t\tu32 dcbd : 1;\n+\t\tu32 dtdd : 1;\n+\t\tu32 ed : 1;\n+\t\tu32 reserved_13_15 : 3;\n+\t\tu32 rxeq_ph01_en : 1;\n+\t\tu32 erd : 1;\n+\t\tu32 ecrd : 1;\n+\t\tu32 ep2p3d : 1;\n+\t\tu32 dsg3 : 1;\n+\t\tu32 reserved_1_7 : 7;\n+\t\tu32 grizdnc : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg548_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg548_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg548_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg548_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg548 cvmx_pcieepx_cfg548_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg554\n+ *\n+ * This register contains the five hundred fifty-fifth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg554 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg554_s {\n+\t\tu32 reserved_27_31 : 5;\n+\t\tu32 scefpm : 1;\n+\t\tu32 reserved_25_25 : 1;\n+\t\tu32 iif : 1;\n+\t\tu32 prv : 16;\n+\t\tu32 reserved_6_7 : 2;\n+\t\tu32 p23td : 1;\n+\t\tu32 bt : 1;\n+\t\tu32 fm : 4;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg554_cn73xx {\n+\t\tu32 reserved_25_31 : 7;\n+\t\tu32 iif : 1;\n+\t\tu32 prv : 16;\n+\t\tu32 reserved_6_7 : 2;\n+\t\tu32 p23td : 1;\n+\t\tu32 bt : 1;\n+\t\tu32 fm : 4;\n+\t} cn73xx;\n+\tstruct cvmx_pcieepx_cfg554_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg554_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg554_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg554 cvmx_pcieepx_cfg554_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg558\n+ *\n+ * This register contains the five hundred fifty-ninth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg558 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg558_s {\n+\t\tu32 ple : 1;\n+\t\tu32 rxstatus : 31;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg558_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg558_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg558_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg558_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg558 cvmx_pcieepx_cfg558_t;\n+\n+/**\n+ * cvmx_pcieep#_cfg559\n+ *\n+ * This register contains the five hundred sixtieth 32-bits of PCIe type 0 configuration space.\n+ *\n+ */\n+union cvmx_pcieepx_cfg559 {\n+\tu32 u32;\n+\tstruct cvmx_pcieepx_cfg559_s {\n+\t\tu32 reserved_1_31 : 31;\n+\t\tu32 dbi_ro_wr_en : 1;\n+\t} s;\n+\tstruct cvmx_pcieepx_cfg559_s cn73xx;\n+\tstruct cvmx_pcieepx_cfg559_s cn78xx;\n+\tstruct cvmx_pcieepx_cfg559_s cn78xxp1;\n+\tstruct cvmx_pcieepx_cfg559_s cnf75xx;\n+};\n+\n+typedef union cvmx_pcieepx_cfg559 cvmx_pcieepx_cfg559_t;\n+\n+#endif\n",
    "prefixes": [
        "v1",
        "17/50"
    ]
}