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{
    "id": 1415041,
    "url": "http://patchwork.ozlabs.org/api/patches/1415041/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-12-sr@denx.de/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20201211160612.1498780-12-sr@denx.de>",
    "list_archive_url": null,
    "date": "2020-12-11T16:05:33",
    "name": "[v1,11/50] mips: octeon: Add cvmx-gmxx-defs.h header file",
    "commit_ref": "297a3d5850747ddef3bdcb2aafbe64c376c7a09b",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "eea73170888ba57a9a2b37eafec134e2ca307bbf",
    "submitter": {
        "id": 13,
        "url": "http://patchwork.ozlabs.org/api/people/13/?format=api",
        "name": "Stefan Roese",
        "email": "sr@denx.de"
    },
    "delegate": {
        "id": 4307,
        "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api",
        "username": "danielschwierzeck",
        "first_name": "Daniel",
        "last_name": "Schwierzeck",
        "email": "daniel.schwierzeck@googlemail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-12-sr@denx.de/mbox/",
    "series": [
        {
            "id": 220054,
            "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054",
            "date": "2020-12-11T16:05:23",
            "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1415041/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1415041/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Stefan Roese <sr@denx.de>",
        "To": "u-boot@lists.denx.de",
        "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com",
        "Subject": "[PATCH v1 11/50] mips: octeon: Add cvmx-gmxx-defs.h header file",
        "Date": "Fri, 11 Dec 2020 17:05:33 +0100",
        "Message-Id": "<20201211160612.1498780-12-sr@denx.de>",
        "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>",
        "References": "<20201211160612.1498780-1-sr@denx.de>",
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    "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-gmxx-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-gmxx-defs.h | 6378 +++++++++++++++++\n 1 file changed, 6378 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-gmxx-defs.h",
    "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-gmxx-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-gmxx-defs.h\nnew file mode 100644\nindex 0000000000..8231fef220\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-gmxx-defs.h\n@@ -0,0 +1,6378 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon gmxx.\n+ */\n+\n+#ifndef __CVMX_GMXX_DEFS_H__\n+#define __CVMX_GMXX_DEFS_H__\n+\n+static inline u64 CVMX_GMXX_BAD_REG(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000518ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000518ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000518ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000518ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_BIST(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000400ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000400ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000400ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000400ull + (offset) * 0x8000000ull;\n+}\n+\n+#define CVMX_GMXX_BPID_MAPX(offset, block_id)                                                      \\\n+\t(0x0001180008000680ull + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8)\n+#define CVMX_GMXX_BPID_MSK(offset) (0x0001180008000700ull + ((offset) & 7) * 0x1000000ull)\n+static inline u64 CVMX_GMXX_CLK_EN(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080007F0ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080007F0ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080007F0ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080007F0ull + (offset) * 0x8000000ull;\n+}\n+\n+#define CVMX_GMXX_EBP_DIS(offset) (0x0001180008000608ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_GMXX_EBP_MSK(offset) (0x0001180008000600ull + ((offset) & 7) * 0x1000000ull)\n+static inline u64 CVMX_GMXX_HG2_CONTROL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000550ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000550ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000550ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000550ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_INF_MODE(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080007F8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080007F8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080007F8ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080007F8ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_NXA_ADR(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000510ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000510ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000510ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000510ull + (offset) * 0x8000000ull;\n+}\n+\n+#define CVMX_GMXX_PIPE_STATUS(offset) (0x0001180008000760ull + ((offset) & 7) * 0x1000000ull)\n+static inline u64 CVMX_GMXX_PRTX_CBFC_CTL(unsigned long __attribute__((unused)) offset,\n+\t\t\t\t\t  unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000580ull + (block_id) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000580ull + (block_id) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000580ull + (block_id) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000580ull + (block_id) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000010ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000010ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000010ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+#define CVMX_GMXX_QSGMII_CTL(offset) (0x0001180008000760ull + ((offset) & 1) * 0x8000000ull)\n+static inline u64 CVMX_GMXX_RXAUI_CTL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000740ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000740ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000740ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000180ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000180ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000180ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000188ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000188ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000188ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000190ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000190ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000190ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000198ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000198ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000198ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080001A0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080001A0ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080001A0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080001A8ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080001A8ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080001A8ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000110ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000110ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000110ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000110ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000108ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000108ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000108ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000100ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000100ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000100ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000040ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000040ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000040ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000020ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000020ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000020ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000018ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000018ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000018ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id)                                                    \\\n+\t(0x0001180008000030ull + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)\n+#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id)                                                    \\\n+\t(0x0001180008000028ull + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)\n+static inline u64 CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000058ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000058ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000058ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000008ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000008ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000008ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000000ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000000ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000000ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000038ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000038ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000038ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000068ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000068ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000068ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000068ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000068ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+#define CVMX_GMXX_RXX_RX_INBND(offset, block_id)                                                   \\\n+\t(0x0001180008000060ull + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)\n+static inline u64 CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000050ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000050ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000050ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000088ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000088ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000088ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000098ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000098ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000098ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080000A8ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080000A8ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080000A8ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080000B8ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080000B8ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080000B8ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000080ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000080ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000080ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080000C0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080000C0ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080000C0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000090ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000090ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000090ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080000A0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080000A0ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080000A0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080000B0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080000B0ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080000B0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000048ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000048ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000048ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000420ull + ((offset) + (block_id) * 0x1000000ull) * 8;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000420ull + ((offset) + (block_id) * 0x200000ull) * 8;\n+\t}\n+\treturn 0x0001180008000420ull + ((offset) + (block_id) * 0x1000000ull) * 8;\n+}\n+\n+static inline u64 CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000460ull + ((offset) + (block_id) * 0x1000000ull) * 8;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000460ull + ((offset) + (block_id) * 0x200000ull) * 8;\n+\t}\n+\treturn 0x0001180008000460ull + ((offset) + (block_id) * 0x1000000ull) * 8;\n+}\n+\n+static inline u64 CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000440ull + ((offset) + (block_id) * 0x1000000ull) * 8;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000440ull + ((offset) + (block_id) * 0x200000ull) * 8;\n+\t}\n+\treturn 0x0001180008000440ull + ((offset) + (block_id) * 0x1000000ull) * 8;\n+}\n+\n+static inline u64 CVMX_GMXX_RX_HG2_STATUS(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000548ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000548ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000548ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000548ull + (offset) * 0x8000000ull;\n+}\n+\n+#define CVMX_GMXX_RX_PASS_EN(offset) (0x00011800080005F8ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id)                                                   \\\n+\t(0x0001180008000600ull + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8)\n+static inline u64 CVMX_GMXX_RX_PRTS(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000410ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000410ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000410ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000410ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_RX_PRT_INFO(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004E8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004E8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004E8ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080004E8ull + (offset) * 0x8000000ull;\n+}\n+\n+#define CVMX_GMXX_RX_TX_STATUS(offset) (0x00011800080007E8ull)\n+static inline u64 CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000538ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000538ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000538ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000538ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_RX_XAUI_CTL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000530ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000530ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000530ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000530ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000230ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000230ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000230ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_SOFT_BIST(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080007E8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080007E8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080007E8ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080007E8ull + (offset) * 0x1000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_STAT_BP(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000520ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000520ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000520ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000520ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TB_REG(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080007E0ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080007E0ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080007E0ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080007E0ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000218ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000218ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000218ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+#define CVMX_GMXX_TXX_BCK_CRDT(offset, block_id)                                                   \\\n+\t(0x0001180008000388ull + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)\n+static inline u64 CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000228ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000228ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000228ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_CBFC_XOFF(unsigned long __attribute__((unused)) offset,\n+\t\t\t\t\t  unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080005A0ull + (block_id) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080005A0ull + (block_id) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080005A0ull + (block_id) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080005A0ull + (block_id) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_CBFC_XON(unsigned long __attribute__((unused)) offset,\n+\t\t\t\t\t unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080005C0ull + (block_id) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080005C0ull + (block_id) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080005C0ull + (block_id) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080005C0ull + (block_id) * 0x8000000ull;\n+}\n+\n+#define CVMX_GMXX_TXX_CLK(offset, block_id)                                                        \\\n+\t(0x0001180008000208ull + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)\n+static inline u64 CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000270ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000270ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000270ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+#define CVMX_GMXX_TXX_JAM_MODE(offset, block_id)                                                   \\\n+\t(0x0001180008000380ull + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)\n+static inline u64 CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000240ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000240ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000240ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000248ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000248ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000248ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000238ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000238ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000238ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000258ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000258ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000258ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000260ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000260ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000260ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+#define CVMX_GMXX_TXX_PIPE(offset, block_id)                                                       \\\n+\t(0x0001180008000310ull + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048)\n+static inline u64 CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000300ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000300ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000300ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000300ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000220ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000220ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000220ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000250ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000250ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000250ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000280ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000280ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000280ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000288ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000288ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000288ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000290ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000290ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000290ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000298ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000298ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000298ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080002A0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080002A0ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080002A0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080002A8ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080002A8ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080002A8ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080002B0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080002B0ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080002B0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080002B8ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080002B8ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080002B8ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080002C0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080002C0ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080002C0ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080002C8ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080002C8ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x00011800080002C8ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000268ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000268ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000268ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000210ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000210ull + ((offset) + (block_id) * 0x2000ull) * 2048;\n+\t}\n+\treturn 0x0001180008000210ull + ((offset) + (block_id) * 0x10000ull) * 2048;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_BP(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004D0ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004D0ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004D0ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080004D0ull + (offset) * 0x8000000ull;\n+}\n+\n+#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id)                                                    \\\n+\t(0x0001180008000780ull + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)\n+static inline u64 CVMX_GMXX_TX_COL_ATTEMPT(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000498ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000498ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000498ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000498ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_CORRUPT(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004D8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004D8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004D8ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080004D8ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_HG2_REG1(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000558ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000558ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000558ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000558ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_HG2_REG2(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000560ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000560ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000560ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000560ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_IFG(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000488ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000488ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000488ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000488ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_INT_EN(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000508ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000508ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000508ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000508ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_INT_REG(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000500ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000500ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000500ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000500ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_JAM(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000490ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000490ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000490ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000490ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_LFSR(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004F8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004F8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004F8ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080004F8ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_OVR_BP(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004C8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004C8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004C8ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080004C8ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004A0ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004A0ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004A0ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080004A0ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004A8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004A8ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800080004A8ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800080004A8ull + (offset) * 0x8000000ull;\n+}\n+\n+static inline u64 CVMX_GMXX_TX_PRTS(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000480ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000480ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000480ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000480ull + (offset) * 0x8000000ull;\n+}\n+\n+#define CVMX_GMXX_TX_SPI_CTL(offset)   (0x00011800080004C0ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_GMXX_TX_SPI_DRAIN(offset) (0x00011800080004E0ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_GMXX_TX_SPI_MAX(offset)   (0x00011800080004B0ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id)                                                  \\\n+\t(0x0001180008000680ull + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)\n+#define CVMX_GMXX_TX_SPI_THRESH(offset) (0x00011800080004B8ull + ((offset) & 1) * 0x8000000ull)\n+static inline u64 CVMX_GMXX_TX_XAUI_CTL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000528ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000528ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000528ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000528ull + (offset) * 0x8000000ull;\n+}\n+\n+#define CVMX_GMXX_WOL_CTL(offset) (0x0001180008000780ull + ((offset) & 1) * 0x8000000ull)\n+static inline u64 CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000540ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000540ull + (offset) * 0x8000000ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180008000540ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x0001180008000540ull + (offset) * 0x8000000ull;\n+}\n+\n+/**\n+ * cvmx_gmx#_bad_reg\n+ *\n+ * GMX_BAD_REG = A collection of things that have gone very, very wrong\n+ *\n+ *\n+ * Notes:\n+ * In XAUI mode, only the lsb (corresponding to port0) of INB_NXA, LOSTSTAT, OUT_OVR, are used.\n+ *\n+ */\n+union cvmx_gmxx_bad_reg {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_bad_reg_s {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 inb_nxa : 4;\n+\t\tu64 statovr : 1;\n+\t\tu64 loststat : 4;\n+\t\tu64 reserved_18_21 : 4;\n+\t\tu64 out_ovr : 16;\n+\t\tu64 ncb_ovr : 1;\n+\t\tu64 out_col : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_bad_reg_cn30xx {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 inb_nxa : 4;\n+\t\tu64 statovr : 1;\n+\t\tu64 reserved_25_25 : 1;\n+\t\tu64 loststat : 3;\n+\t\tu64 reserved_5_21 : 17;\n+\t\tu64 out_ovr : 3;\n+\t\tu64 reserved_0_1 : 2;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_bad_reg_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_bad_reg_s cn38xx;\n+\tstruct cvmx_gmxx_bad_reg_s cn38xxp2;\n+\tstruct cvmx_gmxx_bad_reg_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 inb_nxa : 4;\n+\t\tu64 statovr : 1;\n+\t\tu64 loststat : 4;\n+\t\tu64 reserved_6_21 : 16;\n+\t\tu64 out_ovr : 4;\n+\t\tu64 reserved_0_1 : 2;\n+\t} cn52xx;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx cn52xxp1;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx cn56xx;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;\n+\tstruct cvmx_gmxx_bad_reg_s cn58xx;\n+\tstruct cvmx_gmxx_bad_reg_s cn58xxp1;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx cn61xx;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx cn63xx;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx cn63xxp1;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx cn66xx;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx cn68xx;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx cn68xxp1;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx cn70xx;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx cn70xxp1;\n+\tstruct cvmx_gmxx_bad_reg_cn52xx cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_bad_reg cvmx_gmxx_bad_reg_t;\n+\n+/**\n+ * cvmx_gmx#_bist\n+ *\n+ * GMX_BIST = GMX BIST Results\n+ *\n+ */\n+union cvmx_gmxx_bist {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_bist_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 status : 25;\n+\t} s;\n+\tstruct cvmx_gmxx_bist_cn30xx {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 status : 10;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_bist_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_bist_cn30xx cn38xx;\n+\tstruct cvmx_gmxx_bist_cn30xx cn38xxp2;\n+\tstruct cvmx_gmxx_bist_cn50xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 status : 12;\n+\t} cn50xx;\n+\tstruct cvmx_gmxx_bist_cn52xx {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 status : 16;\n+\t} cn52xx;\n+\tstruct cvmx_gmxx_bist_cn52xx cn52xxp1;\n+\tstruct cvmx_gmxx_bist_cn52xx cn56xx;\n+\tstruct cvmx_gmxx_bist_cn52xx cn56xxp1;\n+\tstruct cvmx_gmxx_bist_cn58xx {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 status : 17;\n+\t} cn58xx;\n+\tstruct cvmx_gmxx_bist_cn58xx cn58xxp1;\n+\tstruct cvmx_gmxx_bist_s cn61xx;\n+\tstruct cvmx_gmxx_bist_s cn63xx;\n+\tstruct cvmx_gmxx_bist_s cn63xxp1;\n+\tstruct cvmx_gmxx_bist_s cn66xx;\n+\tstruct cvmx_gmxx_bist_s cn68xx;\n+\tstruct cvmx_gmxx_bist_s cn68xxp1;\n+\tstruct cvmx_gmxx_bist_s cn70xx;\n+\tstruct cvmx_gmxx_bist_s cn70xxp1;\n+\tstruct cvmx_gmxx_bist_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_bist cvmx_gmxx_bist_t;\n+\n+/**\n+ * cvmx_gmx#_bpid_map#\n+ *\n+ * Notes:\n+ * GMX will build BPID_VECTOR<15:0> using the 16 GMX_BPID_MAP entries and the BPID\n+ * state from IPD.  In XAUI/RXAUI mode when PFC/CBFC/HiGig2 is used, the\n+ * BPID_VECTOR becomes the logical backpressure.  In XAUI/RXAUI mode when\n+ * PFC/CBFC/HiGig2 is not used or when in 4xSGMII mode, the BPID_VECTOR can be used\n+ * with the GMX_BPID_MSK register to determine the physical backpressure.\n+ *\n+ * In XAUI/RXAUI mode, the entire BPID_VECTOR<15:0> is available determining physical\n+ * backpressure for the single XAUI/RXAUI interface.\n+ *\n+ * In SGMII mode, BPID_VECTOR is broken up as follows:\n+ *    SGMII interface0 uses BPID_VECTOR<3:0>\n+ *    SGMII interface1 uses BPID_VECTOR<7:4>\n+ *    SGMII interface2 uses BPID_VECTOR<11:8>\n+ *    SGMII interface3 uses BPID_VECTOR<15:12>\n+ *\n+ * In all SGMII configurations, and in some XAUI/RXAUI configurations, the\n+ * interface protocols only support physical backpressure. In these cases, a single\n+ * BPID will commonly drive the physical backpressure for the physical\n+ * interface. We provide example programmings for these simple cases.\n+ *\n+ * In XAUI/RXAUI mode where PFC/CBFC/HiGig2 is not used, an example programming\n+ * would be as follows:\n+ *\n+ *    @verbatim\n+ *    GMX_BPID_MAP0[VAL]    = 1;\n+ *    GMX_BPID_MAP0[BPID]   = xaui_bpid;\n+ *    GMX_BPID_MSK[MSK_OR]  = 1;\n+ *    GMX_BPID_MSK[MSK_AND] = 0;\n+ *    @endverbatim\n+ *\n+ * In SGMII mode, an example programming would be as follows:\n+ *\n+ *    @verbatim\n+ *    for (i=0; i<4; i++) [\n+ *       if (GMX_PRTi_CFG[EN]) [\n+ *          GMX_BPID_MAP(i*4)[VAL]    = 1;\n+ *          GMX_BPID_MAP(i*4)[BPID]   = sgmii_bpid(i);\n+ *          GMX_BPID_MSK[MSK_OR]      = (1 << (i*4)) | GMX_BPID_MSK[MSK_OR];\n+ *       ]\n+ *    ]\n+ *    GMX_BPID_MSK[MSK_AND] = 0;\n+ *    @endverbatim\n+ */\n+union cvmx_gmxx_bpid_mapx {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_bpid_mapx_s {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 status : 1;\n+\t\tu64 reserved_9_15 : 7;\n+\t\tu64 val : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 bpid : 6;\n+\t} s;\n+\tstruct cvmx_gmxx_bpid_mapx_s cn68xx;\n+\tstruct cvmx_gmxx_bpid_mapx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_gmxx_bpid_mapx cvmx_gmxx_bpid_mapx_t;\n+\n+/**\n+ * cvmx_gmx#_bpid_msk\n+ */\n+union cvmx_gmxx_bpid_msk {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_bpid_msk_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 msk_or : 16;\n+\t\tu64 reserved_16_31 : 16;\n+\t\tu64 msk_and : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_bpid_msk_s cn68xx;\n+\tstruct cvmx_gmxx_bpid_msk_s cn68xxp1;\n+};\n+\n+typedef union cvmx_gmxx_bpid_msk cvmx_gmxx_bpid_msk_t;\n+\n+/**\n+ * cvmx_gmx#_clk_en\n+ *\n+ * DON'T PUT IN HRM*\n+ *\n+ */\n+union cvmx_gmxx_clk_en {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_clk_en_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 clk_en : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_clk_en_s cn52xx;\n+\tstruct cvmx_gmxx_clk_en_s cn52xxp1;\n+\tstruct cvmx_gmxx_clk_en_s cn56xx;\n+\tstruct cvmx_gmxx_clk_en_s cn56xxp1;\n+\tstruct cvmx_gmxx_clk_en_s cn61xx;\n+\tstruct cvmx_gmxx_clk_en_s cn63xx;\n+\tstruct cvmx_gmxx_clk_en_s cn63xxp1;\n+\tstruct cvmx_gmxx_clk_en_s cn66xx;\n+\tstruct cvmx_gmxx_clk_en_s cn68xx;\n+\tstruct cvmx_gmxx_clk_en_s cn68xxp1;\n+\tstruct cvmx_gmxx_clk_en_s cn70xx;\n+\tstruct cvmx_gmxx_clk_en_s cn70xxp1;\n+\tstruct cvmx_gmxx_clk_en_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_clk_en cvmx_gmxx_clk_en_t;\n+\n+/**\n+ * cvmx_gmx#_ebp_dis\n+ */\n+union cvmx_gmxx_ebp_dis {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_ebp_dis_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 dis : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_ebp_dis_s cn68xx;\n+\tstruct cvmx_gmxx_ebp_dis_s cn68xxp1;\n+};\n+\n+typedef union cvmx_gmxx_ebp_dis cvmx_gmxx_ebp_dis_t;\n+\n+/**\n+ * cvmx_gmx#_ebp_msk\n+ */\n+union cvmx_gmxx_ebp_msk {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_ebp_msk_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 msk : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_ebp_msk_s cn68xx;\n+\tstruct cvmx_gmxx_ebp_msk_s cn68xxp1;\n+};\n+\n+typedef union cvmx_gmxx_ebp_msk cvmx_gmxx_ebp_msk_t;\n+\n+/**\n+ * cvmx_gmx#_hg2_control\n+ *\n+ * Notes:\n+ * The HiGig2 TX and RX enable would normally be both set together for HiGig2 messaging. However\n+ * setting just the TX or RX bit will result in only the HG2 message transmit or the receive\n+ * capability.\n+ * PHYS_EN and LOGL_EN bits when 1, allow link pause or back pressure to PKO as per received\n+ * HiGig2 message. When 0, link pause and back pressure to PKO in response to received messages\n+ * are disabled.\n+ *\n+ * GMX*_TX_XAUI_CTL[HG_EN] must be set to one(to enable HiGig) whenever either HG2TX_EN or HG2RX_EN\n+ * are set.\n+ *\n+ * GMX*_RX0_UDD_SKP[LEN] must be set to 16 (to select HiGig2) whenever either HG2TX_EN or HG2RX_EN\n+ * are set.\n+ *\n+ * GMX*_TX_OVR_BP[EN<0>] must be set to one and GMX*_TX_OVR_BP[BP<0>] must be cleared to zero\n+ * (to forcibly disable HW-automatic 802.3 pause packet generation) with the HiGig2 Protocol when\n+ * GMX*_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated by GMX*_TX_XAUI_CTL[HG_EN]=1\n+ * and GMX*_RX0_UDD_SKP[LEN]=16.) The HW can only auto-generate backpressure via HiGig2 messages\n+ * (optionally, when HG2TX_EN=1) with the HiGig2 protocol.\n+ */\n+union cvmx_gmxx_hg2_control {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_hg2_control_s {\n+\t\tu64 reserved_19_63 : 45;\n+\t\tu64 hg2tx_en : 1;\n+\t\tu64 hg2rx_en : 1;\n+\t\tu64 phys_en : 1;\n+\t\tu64 logl_en : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_hg2_control_s cn52xx;\n+\tstruct cvmx_gmxx_hg2_control_s cn52xxp1;\n+\tstruct cvmx_gmxx_hg2_control_s cn56xx;\n+\tstruct cvmx_gmxx_hg2_control_s cn61xx;\n+\tstruct cvmx_gmxx_hg2_control_s cn63xx;\n+\tstruct cvmx_gmxx_hg2_control_s cn63xxp1;\n+\tstruct cvmx_gmxx_hg2_control_s cn66xx;\n+\tstruct cvmx_gmxx_hg2_control_s cn68xx;\n+\tstruct cvmx_gmxx_hg2_control_s cn68xxp1;\n+\tstruct cvmx_gmxx_hg2_control_s cn70xx;\n+\tstruct cvmx_gmxx_hg2_control_s cn70xxp1;\n+\tstruct cvmx_gmxx_hg2_control_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_hg2_control cvmx_gmxx_hg2_control_t;\n+\n+/**\n+ * cvmx_gmx#_inf_mode\n+ *\n+ * GMX_INF_MODE = Interface Mode\n+ *\n+ */\n+union cvmx_gmxx_inf_mode {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_inf_mode_s {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 rate : 4;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 speed : 4;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 mode : 3;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 p0mii : 1;\n+\t\tu64 en : 1;\n+\t\tu64 type : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_inf_mode_cn30xx {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 p0mii : 1;\n+\t\tu64 en : 1;\n+\t\tu64 type : 1;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_inf_mode_cn31xx {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 en : 1;\n+\t\tu64 type : 1;\n+\t} cn31xx;\n+\tstruct cvmx_gmxx_inf_mode_cn31xx cn38xx;\n+\tstruct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;\n+\tstruct cvmx_gmxx_inf_mode_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_inf_mode_cn52xx {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 speed : 2;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 mode : 2;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 en : 1;\n+\t\tu64 type : 1;\n+\t} cn52xx;\n+\tstruct cvmx_gmxx_inf_mode_cn52xx cn52xxp1;\n+\tstruct cvmx_gmxx_inf_mode_cn52xx cn56xx;\n+\tstruct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;\n+\tstruct cvmx_gmxx_inf_mode_cn31xx cn58xx;\n+\tstruct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;\n+\tstruct cvmx_gmxx_inf_mode_cn61xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 speed : 4;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 mode : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 en : 1;\n+\t\tu64 type : 1;\n+\t} cn61xx;\n+\tstruct cvmx_gmxx_inf_mode_cn61xx cn63xx;\n+\tstruct cvmx_gmxx_inf_mode_cn61xx cn63xxp1;\n+\tstruct cvmx_gmxx_inf_mode_cn66xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 rate : 4;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 speed : 4;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 mode : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 en : 1;\n+\t\tu64 type : 1;\n+\t} cn66xx;\n+\tstruct cvmx_gmxx_inf_mode_cn68xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 speed : 4;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 mode : 3;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 en : 1;\n+\t\tu64 type : 1;\n+\t} cn68xx;\n+\tstruct cvmx_gmxx_inf_mode_cn68xx cn68xxp1;\n+\tstruct cvmx_gmxx_inf_mode_cn70xx {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 mode : 2;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 en : 1;\n+\t\tu64 reserved_0_0 : 1;\n+\t} cn70xx;\n+\tstruct cvmx_gmxx_inf_mode_cn70xx cn70xxp1;\n+\tstruct cvmx_gmxx_inf_mode_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_inf_mode cvmx_gmxx_inf_mode_t;\n+\n+/**\n+ * cvmx_gmx#_nxa_adr\n+ *\n+ * GMX_NXA_ADR = NXA Port Address\n+ *\n+ */\n+union cvmx_gmxx_nxa_adr {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_nxa_adr_s {\n+\t\tu64 reserved_23_63 : 41;\n+\t\tu64 pipe : 7;\n+\t\tu64 reserved_6_15 : 10;\n+\t\tu64 prt : 6;\n+\t} s;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 prt : 6;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn38xx;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn38xxp2;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn52xx;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn52xxp1;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn56xx;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn56xxp1;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn58xx;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn58xxp1;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn61xx;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn63xx;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn63xxp1;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn66xx;\n+\tstruct cvmx_gmxx_nxa_adr_s cn68xx;\n+\tstruct cvmx_gmxx_nxa_adr_s cn68xxp1;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn70xx;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cn70xxp1;\n+\tstruct cvmx_gmxx_nxa_adr_cn30xx cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_nxa_adr cvmx_gmxx_nxa_adr_t;\n+\n+/**\n+ * cvmx_gmx#_pipe_status\n+ *\n+ * DON'T PUT IN HRM*\n+ *\n+ */\n+union cvmx_gmxx_pipe_status {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_pipe_status_s {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 ovr : 4;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 bp : 4;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 stop : 4;\n+\t} s;\n+\tstruct cvmx_gmxx_pipe_status_s cn68xx;\n+\tstruct cvmx_gmxx_pipe_status_s cn68xxp1;\n+};\n+\n+typedef union cvmx_gmxx_pipe_status cvmx_gmxx_pipe_status_t;\n+\n+/**\n+ * cvmx_gmx#_prt#_cbfc_ctl\n+ *\n+ * ** HG2 message CSRs end\n+ *\n+ */\n+union cvmx_gmxx_prtx_cbfc_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_prtx_cbfc_ctl_s {\n+\t\tu64 phys_en : 16;\n+\t\tu64 logl_en : 16;\n+\t\tu64 phys_bp : 16;\n+\t\tu64 reserved_4_15 : 12;\n+\t\tu64 bck_en : 1;\n+\t\tu64 drp_en : 1;\n+\t\tu64 tx_en : 1;\n+\t\tu64 rx_en : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;\n+\tstruct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;\n+\tstruct cvmx_gmxx_prtx_cbfc_ctl_s cn61xx;\n+\tstruct cvmx_gmxx_prtx_cbfc_ctl_s cn63xx;\n+\tstruct cvmx_gmxx_prtx_cbfc_ctl_s cn63xxp1;\n+\tstruct cvmx_gmxx_prtx_cbfc_ctl_s cn66xx;\n+\tstruct cvmx_gmxx_prtx_cbfc_ctl_s cn68xx;\n+\tstruct cvmx_gmxx_prtx_cbfc_ctl_s cn68xxp1;\n+\tstruct cvmx_gmxx_prtx_cbfc_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_prtx_cbfc_ctl_s cn70xxp1;\n+\tstruct cvmx_gmxx_prtx_cbfc_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_prtx_cbfc_ctl cvmx_gmxx_prtx_cbfc_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_prt#_cfg\n+ *\n+ * GMX_PRT_CFG = Port description\n+ *\n+ */\n+union cvmx_gmxx_prtx_cfg {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_prtx_cfg_s {\n+\t\tu64 reserved_22_63 : 42;\n+\t\tu64 pknd : 6;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 tx_idle : 1;\n+\t\tu64 rx_idle : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 speed_msb : 1;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 slottime : 1;\n+\t\tu64 duplex : 1;\n+\t\tu64 speed : 1;\n+\t\tu64 en : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_prtx_cfg_cn30xx {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 slottime : 1;\n+\t\tu64 duplex : 1;\n+\t\tu64 speed : 1;\n+\t\tu64 en : 1;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_prtx_cfg_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;\n+\tstruct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;\n+\tstruct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_prtx_cfg_cn52xx {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 tx_idle : 1;\n+\t\tu64 rx_idle : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 speed_msb : 1;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 slottime : 1;\n+\t\tu64 duplex : 1;\n+\t\tu64 speed : 1;\n+\t\tu64 en : 1;\n+\t} cn52xx;\n+\tstruct cvmx_gmxx_prtx_cfg_cn52xx cn52xxp1;\n+\tstruct cvmx_gmxx_prtx_cfg_cn52xx cn56xx;\n+\tstruct cvmx_gmxx_prtx_cfg_cn52xx cn56xxp1;\n+\tstruct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;\n+\tstruct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;\n+\tstruct cvmx_gmxx_prtx_cfg_cn52xx cn61xx;\n+\tstruct cvmx_gmxx_prtx_cfg_cn52xx cn63xx;\n+\tstruct cvmx_gmxx_prtx_cfg_cn52xx cn63xxp1;\n+\tstruct cvmx_gmxx_prtx_cfg_cn52xx cn66xx;\n+\tstruct cvmx_gmxx_prtx_cfg_s cn68xx;\n+\tstruct cvmx_gmxx_prtx_cfg_s cn68xxp1;\n+\tstruct cvmx_gmxx_prtx_cfg_cn52xx cn70xx;\n+\tstruct cvmx_gmxx_prtx_cfg_cn52xx cn70xxp1;\n+\tstruct cvmx_gmxx_prtx_cfg_cn52xx cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_prtx_cfg cvmx_gmxx_prtx_cfg_t;\n+\n+/**\n+ * cvmx_gmx#_qsgmii_ctl\n+ */\n+union cvmx_gmxx_qsgmii_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_qsgmii_ctl_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 disparity : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_qsgmii_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_qsgmii_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_gmxx_qsgmii_ctl cvmx_gmxx_qsgmii_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_adr_cam0\n+ *\n+ * GMX_RX_ADR_CAM = Address Filtering Control\n+ *\n+ */\n+union cvmx_gmxx_rxx_adr_cam0 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s {\n+\t\tu64 adr : 64;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam0_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_adr_cam0 cvmx_gmxx_rxx_adr_cam0_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_adr_cam1\n+ *\n+ * GMX_RX_ADR_CAM = Address Filtering Control\n+ *\n+ */\n+union cvmx_gmxx_rxx_adr_cam1 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s {\n+\t\tu64 adr : 64;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam1_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_adr_cam1 cvmx_gmxx_rxx_adr_cam1_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_adr_cam2\n+ *\n+ * GMX_RX_ADR_CAM = Address Filtering Control\n+ *\n+ */\n+union cvmx_gmxx_rxx_adr_cam2 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s {\n+\t\tu64 adr : 64;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam2_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_adr_cam2 cvmx_gmxx_rxx_adr_cam2_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_adr_cam3\n+ *\n+ * GMX_RX_ADR_CAM = Address Filtering Control\n+ *\n+ */\n+union cvmx_gmxx_rxx_adr_cam3 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s {\n+\t\tu64 adr : 64;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam3_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_adr_cam3 cvmx_gmxx_rxx_adr_cam3_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_adr_cam4\n+ *\n+ * GMX_RX_ADR_CAM = Address Filtering Control\n+ *\n+ */\n+union cvmx_gmxx_rxx_adr_cam4 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s {\n+\t\tu64 adr : 64;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam4_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_adr_cam4 cvmx_gmxx_rxx_adr_cam4_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_adr_cam5\n+ *\n+ * GMX_RX_ADR_CAM = Address Filtering Control\n+ *\n+ */\n+union cvmx_gmxx_rxx_adr_cam5 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s {\n+\t\tu64 adr : 64;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam5_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_adr_cam5 cvmx_gmxx_rxx_adr_cam5_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_adr_cam_all_en\n+ *\n+ * GMX_RX_ADR_CAM_ALL_EN = Address Filtering Control Enable\n+ *\n+ */\n+union cvmx_gmxx_rxx_adr_cam_all_en {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_adr_cam_all_en_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 en : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_all_en_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_all_en_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_adr_cam_all_en cvmx_gmxx_rxx_adr_cam_all_en_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_adr_cam_en\n+ *\n+ * GMX_RX_ADR_CAM_EN = Address Filtering Control Enable\n+ *\n+ */\n+union cvmx_gmxx_rxx_adr_cam_en {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 en : 8;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_cam_en_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_adr_cam_en cvmx_gmxx_rxx_adr_cam_en_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_adr_ctl\n+ *\n+ * GMX_RX_ADR_CTL = Address Filtering Control\n+ *\n+ *\n+ * Notes:\n+ * * ALGORITHM\n+ *   Here is some pseudo code that represents the address filter behavior.\n+ *\n+ *      @verbatim\n+ *      bool dmac_addr_filter(uint8 prt, uint48 dmac) [\n+ *        ASSERT(prt >= 0 && prt <= 3);\n+ *        if (is_bcst(dmac))                               // broadcast accept\n+ *          return (GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);\n+ *        if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 1)   // multicast reject\n+ *          return REJECT;\n+ *        if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 2)   // multicast accept\n+ *          return ACCEPT;\n+ *\n+ *        cam_hit = 0;\n+ *\n+ *        for (i=0; i<32; i++) [\n+ *          if (GMX_RX[prt]_ADR_CAM_ALL_EN[EN<i>] == 0)\n+ *            continue;\n+ *          uint48 unswizzled_mac_adr = 0x0;\n+ *          for (j=5; j>=0; j--) [\n+ *             unswizzled_mac_adr = (unswizzled_mac_adr << 8) | GMX_RX[i>>3]_ADR_CAM[j][ADR<(i&7)*8+7:(i&7)*8>];\n+ *          ]\n+ *          if (unswizzled_mac_adr == dmac) [\n+ *            cam_hit = 1;\n+ *            break;\n+ *          ]\n+ *        ]\n+ *\n+ *        if (cam_hit)\n+ *          return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);\n+ *        else\n+ *          return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);\n+ *      ]\n+ *      @endverbatim\n+ *\n+ * * XAUI Mode\n+ *\n+ *   In XAUI mode, only GMX_RX0_ADR_CTL is used.  GMX_RX[1,2,3]_ADR_CTL should not be used.\n+ */\n+union cvmx_gmxx_rxx_adr_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 cam_mode : 1;\n+\t\tu64 mcst : 2;\n+\t\tu64 bcst : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_adr_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_adr_ctl cvmx_gmxx_rxx_adr_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_decision\n+ *\n+ * GMX_RX_DECISION = The byte count to decide when to accept or filter a packet\n+ *\n+ *\n+ * Notes:\n+ * As each byte in a packet is received by GMX, the L2 byte count is compared\n+ * against the GMX_RX_DECISION[CNT].  The L2 byte count is the number of bytes\n+ * from the beginning of the L2 header (DMAC).  In normal operation, the L2\n+ * header begins after the PREAMBLE+SFD (GMX_RX_FRM_CTL[PRE_CHK]=1) and any\n+ * optional UDD skip data (GMX_RX_UDD_SKP[LEN]).\n+ *\n+ * When GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the\n+ * packet and would require UDD skip length to account for them.\n+ *\n+ *                                                 L2 Size\n+ * Port Mode             <GMX_RX_DECISION bytes (default=24)       >=GMX_RX_DECISION bytes (default=24)\n+ *\n+ * Full Duplex           accept packet                             apply filters\n+ *                       no filtering is applied                   accept packet based on DMAC and PAUSE packet filters\n+ *\n+ * Half Duplex           drop packet                               apply filters\n+ *                       packet is unconditionally dropped         accept packet based on DMAC\n+ *\n+ * where l2_size = MAX(0, total_packet_size - GMX_RX_UDD_SKP[LEN] - ((GMX_RX_FRM_CTL[PRE_CHK]==1)*8)\n+ */\n+union cvmx_gmxx_rxx_decision {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_decision_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 cnt : 5;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_decision_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_decision_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_decision_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_decision_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_decision_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_decision_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_decision_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_decision_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_decision_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_decision_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_decision_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_decision_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_decision_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_decision_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_decision_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_decision_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_decision_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_decision_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_decision_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_decision_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_decision cvmx_gmxx_rxx_decision_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_frm_chk\n+ *\n+ * GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame\n+ *\n+ *\n+ * Notes:\n+ * If GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW.\n+ *\n+ * In XAUI mode prt0 is used for checking.\n+ */\n+union cvmx_gmxx_rxx_frm_chk {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_frm_chk_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_frm_chk_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_frm_chk_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_frm_chk_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn50xx {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_6_6 : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 reserved_0_0 : 1;\n+\t} cn50xx;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn52xx {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 reserved_0_0 : 1;\n+\t} cn52xx;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_frm_chk_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn61xx {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} cn61xx;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xx;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn61xx cn66xx;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xx;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn61xx cn70xx;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn61xx cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_frm_chk_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_frm_chk cvmx_gmxx_rxx_frm_chk_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_frm_ctl\n+ *\n+ * GMX_RX_FRM_CTL = Frame Control\n+ *\n+ *\n+ * Notes:\n+ * * PRE_STRP\n+ *   When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP\n+ *   determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane\n+ *   core as part of the packet.\n+ *\n+ *   In either mode, the PREAMBLE+SFD bytes are not counted toward the packet\n+ *   size when checking against the MIN and MAX bounds.  Furthermore, the bytes\n+ *   are skipped when locating the start of the L2 header for DMAC and Control\n+ *   frame recognition.\n+ *\n+ * * CTL_BCK/CTL_DRP\n+ *   These bits control how the HW handles incoming PAUSE packets.  Here are\n+ *   the most common modes of operation:\n+ *     CTL_BCK=1,CTL_DRP=1   - HW does it all\n+ *     CTL_BCK=0,CTL_DRP=0   - SW sees all pause frames\n+ *     CTL_BCK=0,CTL_DRP=1   - all pause frames are completely ignored\n+ *\n+ *   These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode.\n+ *   Since PAUSE packets only apply to fulldup operation, any PAUSE packet\n+ *   would constitute an exception which should be handled by the processing\n+ *   cores.  PAUSE packets should not be forwarded.\n+ */\n+union cvmx_gmxx_rxx_frm_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 ptp_mode : 1;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 null_dis : 1;\n+\t\tu64 pre_align : 1;\n+\t\tu64 pad_len : 1;\n+\t\tu64 vlan_len : 1;\n+\t\tu64 pre_free : 1;\n+\t\tu64 ctl_smac : 1;\n+\t\tu64 ctl_mcst : 1;\n+\t\tu64 ctl_bck : 1;\n+\t\tu64 ctl_drp : 1;\n+\t\tu64 pre_strp : 1;\n+\t\tu64 pre_chk : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn30xx {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 pad_len : 1;\n+\t\tu64 vlan_len : 1;\n+\t\tu64 pre_free : 1;\n+\t\tu64 ctl_smac : 1;\n+\t\tu64 ctl_mcst : 1;\n+\t\tu64 ctl_bck : 1;\n+\t\tu64 ctl_drp : 1;\n+\t\tu64 pre_strp : 1;\n+\t\tu64 pre_chk : 1;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn31xx {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 vlan_len : 1;\n+\t\tu64 pre_free : 1;\n+\t\tu64 ctl_smac : 1;\n+\t\tu64 ctl_mcst : 1;\n+\t\tu64 ctl_bck : 1;\n+\t\tu64 ctl_drp : 1;\n+\t\tu64 pre_strp : 1;\n+\t\tu64 pre_chk : 1;\n+\t} cn31xx;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn50xx {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 null_dis : 1;\n+\t\tu64 pre_align : 1;\n+\t\tu64 reserved_7_8 : 2;\n+\t\tu64 pre_free : 1;\n+\t\tu64 ctl_smac : 1;\n+\t\tu64 ctl_mcst : 1;\n+\t\tu64 ctl_bck : 1;\n+\t\tu64 ctl_drp : 1;\n+\t\tu64 pre_strp : 1;\n+\t\tu64 pre_chk : 1;\n+\t} cn50xx;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 pre_align : 1;\n+\t\tu64 reserved_7_8 : 2;\n+\t\tu64 pre_free : 1;\n+\t\tu64 ctl_smac : 1;\n+\t\tu64 ctl_mcst : 1;\n+\t\tu64 ctl_bck : 1;\n+\t\tu64 ctl_drp : 1;\n+\t\tu64 pre_strp : 1;\n+\t\tu64 pre_chk : 1;\n+\t} cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn58xx {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 null_dis : 1;\n+\t\tu64 pre_align : 1;\n+\t\tu64 pad_len : 1;\n+\t\tu64 vlan_len : 1;\n+\t\tu64 pre_free : 1;\n+\t\tu64 ctl_smac : 1;\n+\t\tu64 ctl_mcst : 1;\n+\t\tu64 ctl_bck : 1;\n+\t\tu64 ctl_drp : 1;\n+\t\tu64 pre_strp : 1;\n+\t\tu64 pre_chk : 1;\n+\t} cn58xx;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn61xx {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 ptp_mode : 1;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 null_dis : 1;\n+\t\tu64 pre_align : 1;\n+\t\tu64 reserved_7_8 : 2;\n+\t\tu64 pre_free : 1;\n+\t\tu64 ctl_smac : 1;\n+\t\tu64 ctl_mcst : 1;\n+\t\tu64 ctl_bck : 1;\n+\t\tu64 ctl_drp : 1;\n+\t\tu64 pre_strp : 1;\n+\t\tu64 pre_chk : 1;\n+\t} cn61xx;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xx;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn61xx cn66xx;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xx;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn61xx cn70xx;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn61xx cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_frm_ctl_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_frm_ctl cvmx_gmxx_rxx_frm_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_frm_max\n+ *\n+ * GMX_RX_FRM_MAX = Frame Max length\n+ *\n+ *\n+ * Notes:\n+ * In spi4 mode, all spi4 ports use prt0 for checking.\n+ *\n+ * When changing the LEN field, be sure that LEN does not exceed\n+ * GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that\n+ * are within the maximum length parameter to be rejected because they exceed\n+ * the GMX_RX_JABBER[CNT] limit.\n+ */\n+union cvmx_gmxx_rxx_frm_max {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_frm_max_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 len : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_frm_max_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_frm_max_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_frm_max_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_frm_max_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_frm_max_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_frm_max_s cn58xxp1;\n+};\n+\n+typedef union cvmx_gmxx_rxx_frm_max cvmx_gmxx_rxx_frm_max_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_frm_min\n+ *\n+ * GMX_RX_FRM_MIN = Frame Min length\n+ *\n+ *\n+ * Notes:\n+ * In spi4 mode, all spi4 ports use prt0 for checking.\n+ *\n+ */\n+union cvmx_gmxx_rxx_frm_min {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_frm_min_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 len : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_frm_min_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_frm_min_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_frm_min_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_frm_min_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_frm_min_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_frm_min_s cn58xxp1;\n+};\n+\n+typedef union cvmx_gmxx_rxx_frm_min cvmx_gmxx_rxx_frm_min_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_ifg\n+ *\n+ * GMX_RX_IFG = RX Min IFG\n+ *\n+ */\n+union cvmx_gmxx_rxx_ifg {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_ifg_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 ifg : 4;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_ifg_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_ifg_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_ifg cvmx_gmxx_rxx_ifg_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_int_en\n+ *\n+ * GMX_RX_INT_EN = Interrupt Enable\n+ *\n+ *\n+ * Notes:\n+ * In XAUI mode prt0 is used for checking.\n+ *\n+ */\n+union cvmx_gmxx_rxx_int_en {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_int_en_s {\n+\t\tu64 reserved_30_63 : 34;\n+\t\tu64 wol : 1;\n+\t\tu64 hg2cc : 1;\n+\t\tu64 hg2fld : 1;\n+\t\tu64 undat : 1;\n+\t\tu64 uneop : 1;\n+\t\tu64 unsop : 1;\n+\t\tu64 bad_term : 1;\n+\t\tu64 bad_seq : 1;\n+\t\tu64 rem_fault : 1;\n+\t\tu64 loc_fault : 1;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 phy_dupx : 1;\n+\t\tu64 phy_spd : 1;\n+\t\tu64 phy_link : 1;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_int_en_cn30xx {\n+\t\tu64 reserved_19_63 : 45;\n+\t\tu64 phy_dupx : 1;\n+\t\tu64 phy_spd : 1;\n+\t\tu64 phy_link : 1;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;\n+\tstruct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_int_en_cn50xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 phy_dupx : 1;\n+\t\tu64 phy_spd : 1;\n+\t\tu64 phy_link : 1;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_6_6 : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 reserved_0_0 : 1;\n+\t} cn50xx;\n+\tstruct cvmx_gmxx_rxx_int_en_cn52xx {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 hg2cc : 1;\n+\t\tu64 hg2fld : 1;\n+\t\tu64 undat : 1;\n+\t\tu64 uneop : 1;\n+\t\tu64 unsop : 1;\n+\t\tu64 bad_term : 1;\n+\t\tu64 bad_seq : 1;\n+\t\tu64 rem_fault : 1;\n+\t\tu64 loc_fault : 1;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 reserved_16_18 : 3;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 reserved_9_9 : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 reserved_0_0 : 1;\n+\t} cn52xx;\n+\tstruct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;\n+\tstruct cvmx_gmxx_rxx_int_en_cn56xxp1 {\n+\t\tu64 reserved_27_63 : 37;\n+\t\tu64 undat : 1;\n+\t\tu64 uneop : 1;\n+\t\tu64 unsop : 1;\n+\t\tu64 bad_term : 1;\n+\t\tu64 bad_seq : 1;\n+\t\tu64 rem_fault : 1;\n+\t\tu64 loc_fault : 1;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 reserved_16_18 : 3;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 reserved_9_9 : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 reserved_0_0 : 1;\n+\t} cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_int_en_cn58xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 phy_dupx : 1;\n+\t\tu64 phy_spd : 1;\n+\t\tu64 phy_link : 1;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} cn58xx;\n+\tstruct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_int_en_cn61xx {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 hg2cc : 1;\n+\t\tu64 hg2fld : 1;\n+\t\tu64 undat : 1;\n+\t\tu64 uneop : 1;\n+\t\tu64 unsop : 1;\n+\t\tu64 bad_term : 1;\n+\t\tu64 bad_seq : 1;\n+\t\tu64 rem_fault : 1;\n+\t\tu64 loc_fault : 1;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 reserved_16_18 : 3;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 reserved_9_9 : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} cn61xx;\n+\tstruct cvmx_gmxx_rxx_int_en_cn61xx cn63xx;\n+\tstruct cvmx_gmxx_rxx_int_en_cn61xx cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_int_en_cn61xx cn66xx;\n+\tstruct cvmx_gmxx_rxx_int_en_cn61xx cn68xx;\n+\tstruct cvmx_gmxx_rxx_int_en_cn61xx cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_int_en_cn70xx {\n+\t\tu64 reserved_30_63 : 34;\n+\t\tu64 wol : 1;\n+\t\tu64 hg2cc : 1;\n+\t\tu64 hg2fld : 1;\n+\t\tu64 undat : 1;\n+\t\tu64 uneop : 1;\n+\t\tu64 unsop : 1;\n+\t\tu64 bad_term : 1;\n+\t\tu64 bad_seq : 1;\n+\t\tu64 rem_fault : 1;\n+\t\tu64 loc_fault : 1;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 reserved_16_18 : 3;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 reserved_9_9 : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} cn70xx;\n+\tstruct cvmx_gmxx_rxx_int_en_cn70xx cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_int_en_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_int_en cvmx_gmxx_rxx_int_en_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_int_reg\n+ *\n+ * GMX_RX_INT_REG = Interrupt Register\n+ *\n+ *\n+ * Notes:\n+ * (1) exceptions will only be raised to the control processor if the\n+ *     corresponding bit in the GMX_RX_INT_EN register is set.\n+ *\n+ * (2) exception conditions 10:0 can also set the rcv/opcode in the received\n+ *     packet's workQ entry.  The GMX_RX_FRM_CHK register provides a bit mask\n+ *     for configuring which conditions set the error.\n+ *\n+ * (3) in half duplex operation, the expectation is that collisions will appear\n+ *     as either MINERR o r CAREXT errors.\n+ *\n+ * (4) JABBER - An RX Jabber error indicates that a packet was received which\n+ *              is longer than the maximum allowed packet as defined by the\n+ *              system.  GMX will truncate the packet at the JABBER count.\n+ *              Failure to do so could lead to system instabilty.\n+ *\n+ * (5) NIBERR - This error is illegal at 1000Mbs speeds\n+ *              (GMX_RX_PRT_CFG[SPEED]==0) and will never assert.\n+ *\n+ * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS >\n+ *              GMX_RX_FRM_MAX.  For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS\n+ *              > GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED.\n+ *\n+ * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < 64\n+ *\n+ * (8) ALNERR - Indicates that the packet received was not an integer number of\n+ *              bytes.  If FCS checking is enabled, ALNERR will only assert if\n+ *              the FCS is bad.  If FCS checking is disabled, ALNERR will\n+ *              assert in all non-integer frame cases.\n+ *\n+ * (9) Collisions - Collisions can only occur in half-duplex mode.  A collision\n+ *                  is assumed by the receiver when the slottime\n+ *                  (GMX_PRT_CFG[SLOTTIME]) is not satisfied.  In 10/100 mode,\n+ *                  this will result in a frame < SLOTTIME.  In 1000 mode, it\n+ *                  could result either in frame < SLOTTIME or a carrier extend\n+ *                  error with the SLOTTIME.  These conditions are visible by...\n+ *\n+ *                  . transfer ended before slottime - COLDET\n+ *                  . carrier extend error           - CAREXT\n+ *\n+ * (A) LENERR - Length errors occur when the received packet does not match the\n+ *              length field.  LENERR is only checked for packets between 64\n+ *              and 1500 bytes.  For untagged frames, the length must exact\n+ *              match.  For tagged frames the length or length+4 must match.\n+ *\n+ * (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence.\n+ *              Does not check the number of PREAMBLE cycles.\n+ *\n+ * (C) OVRERR -\n+ *\n+ *              OVRERR is an architectural assertion check internal to GMX to\n+ *              make sure no assumption was violated.  In a correctly operating\n+ *              system, this interrupt can never fire.\n+ *\n+ *              GMX has an internal arbiter which selects which of 4 ports to\n+ *              buffer in the main RX FIFO.  If we normally buffer 8 bytes,\n+ *              then each port will typically push a tick every 8 cycles - if\n+ *              the packet interface is going as fast as possible.  If there\n+ *              are four ports, they push every two cycles.  So that's the\n+ *              assumption.  That the inbound module will always be able to\n+ *              consume the tick before another is produced.  If that doesn't\n+ *              happen - that's when OVRERR will assert.\n+ *\n+ * (D) In XAUI mode prt0 is used for interrupt logging.\n+ */\n+union cvmx_gmxx_rxx_int_reg {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_int_reg_s {\n+\t\tu64 reserved_30_63 : 34;\n+\t\tu64 wol : 1;\n+\t\tu64 hg2cc : 1;\n+\t\tu64 hg2fld : 1;\n+\t\tu64 undat : 1;\n+\t\tu64 uneop : 1;\n+\t\tu64 unsop : 1;\n+\t\tu64 bad_term : 1;\n+\t\tu64 bad_seq : 1;\n+\t\tu64 rem_fault : 1;\n+\t\tu64 loc_fault : 1;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 phy_dupx : 1;\n+\t\tu64 phy_spd : 1;\n+\t\tu64 phy_link : 1;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn30xx {\n+\t\tu64 reserved_19_63 : 45;\n+\t\tu64 phy_dupx : 1;\n+\t\tu64 phy_spd : 1;\n+\t\tu64 phy_link : 1;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn50xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 phy_dupx : 1;\n+\t\tu64 phy_spd : 1;\n+\t\tu64 phy_link : 1;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_6_6 : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 reserved_0_0 : 1;\n+\t} cn50xx;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn52xx {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 hg2cc : 1;\n+\t\tu64 hg2fld : 1;\n+\t\tu64 undat : 1;\n+\t\tu64 uneop : 1;\n+\t\tu64 unsop : 1;\n+\t\tu64 bad_term : 1;\n+\t\tu64 bad_seq : 1;\n+\t\tu64 rem_fault : 1;\n+\t\tu64 loc_fault : 1;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 reserved_16_18 : 3;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 reserved_9_9 : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 reserved_0_0 : 1;\n+\t} cn52xx;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn56xxp1 {\n+\t\tu64 reserved_27_63 : 37;\n+\t\tu64 undat : 1;\n+\t\tu64 uneop : 1;\n+\t\tu64 unsop : 1;\n+\t\tu64 bad_term : 1;\n+\t\tu64 bad_seq : 1;\n+\t\tu64 rem_fault : 1;\n+\t\tu64 loc_fault : 1;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 reserved_16_18 : 3;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 reserved_9_9 : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 reserved_0_0 : 1;\n+\t} cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn58xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 phy_dupx : 1;\n+\t\tu64 phy_spd : 1;\n+\t\tu64 phy_link : 1;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} cn58xx;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn61xx {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 hg2cc : 1;\n+\t\tu64 hg2fld : 1;\n+\t\tu64 undat : 1;\n+\t\tu64 uneop : 1;\n+\t\tu64 unsop : 1;\n+\t\tu64 bad_term : 1;\n+\t\tu64 bad_seq : 1;\n+\t\tu64 rem_fault : 1;\n+\t\tu64 loc_fault : 1;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 reserved_16_18 : 3;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 reserved_9_9 : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} cn61xx;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn61xx cn63xx;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn61xx cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn61xx cn66xx;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn61xx cn68xx;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn61xx cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn70xx {\n+\t\tu64 reserved_30_63 : 34;\n+\t\tu64 wol : 1;\n+\t\tu64 hg2cc : 1;\n+\t\tu64 hg2fld : 1;\n+\t\tu64 undat : 1;\n+\t\tu64 uneop : 1;\n+\t\tu64 unsop : 1;\n+\t\tu64 bad_term : 1;\n+\t\tu64 bad_seq : 1;\n+\t\tu64 rem_fault : 1;\n+\t\tu64 loc_fault : 1;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 reserved_16_18 : 3;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 reserved_9_9 : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} cn70xx;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn70xx cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_int_reg_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_int_reg cvmx_gmxx_rxx_int_reg_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_jabber\n+ *\n+ * GMX_RX_JABBER = The max size packet after which GMX will truncate\n+ *\n+ *\n+ * Notes:\n+ * CNT must be 8-byte aligned such that CNT[2:0] == 0\n+ *\n+ * The packet that will be sent to the packet input logic will have an\n+ * additionl 8 bytes if GMX_RX_FRM_CTL[PRE_CHK] is set and\n+ * GMX_RX_FRM_CTL[PRE_STRP] is clear.  The max packet that will be sent is\n+ * defined as...\n+ *\n+ *      max_sized_packet = GMX_RX_JABBER[CNT]+((GMX_RX_FRM_CTL[PRE_CHK] & !GMX_RX_FRM_CTL[PRE_STRP])*8)\n+ *\n+ * In XAUI mode prt0 is used for checking.\n+ */\n+union cvmx_gmxx_rxx_jabber {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_jabber_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 cnt : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_jabber_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_jabber_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_jabber cvmx_gmxx_rxx_jabber_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_pause_drop_time\n+ *\n+ * GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition\n+ *\n+ */\n+union cvmx_gmxx_rxx_pause_drop_time {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 status : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_pause_drop_time_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_pause_drop_time cvmx_gmxx_rxx_pause_drop_time_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_rx_inbnd\n+ *\n+ * GMX_RX_INBND = RGMII InBand Link Status\n+ *\n+ *\n+ * Notes:\n+ * These fields are only valid if the attached PHY is operating in RGMII mode\n+ * and supports the optional in-band status (see section 3.4.1 of the RGMII\n+ * specification, version 1.3 for more information).\n+ */\n+union cvmx_gmxx_rxx_rx_inbnd {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_rx_inbnd_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 duplex : 1;\n+\t\tu64 speed : 2;\n+\t\tu64 status : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_rx_inbnd_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_rx_inbnd_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_rx_inbnd_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_rx_inbnd_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_rx_inbnd_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1;\n+};\n+\n+typedef union cvmx_gmxx_rxx_rx_inbnd cvmx_gmxx_rxx_rx_inbnd_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_stats_ctl\n+ *\n+ * GMX_RX_STATS_CTL = RX Stats Control register\n+ *\n+ */\n+union cvmx_gmxx_rxx_stats_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 rd_clr : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_stats_ctl cvmx_gmxx_rxx_stats_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_stats_octs\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_rxx_stats_octs {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_stats_octs cvmx_gmxx_rxx_stats_octs_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_stats_octs_ctl\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_rxx_stats_octs_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_stats_octs_ctl cvmx_gmxx_rxx_stats_octs_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_stats_octs_dmac\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_rxx_stats_octs_dmac {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_dmac_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_stats_octs_dmac cvmx_gmxx_rxx_stats_octs_dmac_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_stats_octs_drp\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_rxx_stats_octs_drp {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_octs_drp_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_stats_octs_drp cvmx_gmxx_rxx_stats_octs_drp_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_stats_pkts\n+ *\n+ * Count of good received packets - packets that are not recognized as PAUSE\n+ * packets, dropped due the DMAC filter, dropped due FIFO full status, or\n+ * have any other OPCODE (FCS, Length, etc).\n+ */\n+union cvmx_gmxx_rxx_stats_pkts {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_stats_pkts cvmx_gmxx_rxx_stats_pkts_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_stats_pkts_bad\n+ *\n+ * Count of all packets received with some error that were not dropped\n+ * either due to the dmac filter or lack of room in the receive FIFO.\n+ */\n+union cvmx_gmxx_rxx_stats_pkts_bad {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_bad_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_stats_pkts_bad cvmx_gmxx_rxx_stats_pkts_bad_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_stats_pkts_ctl\n+ *\n+ * Count of all packets received that were recognized as Flow Control or\n+ * PAUSE packets.  PAUSE packets with any kind of error are counted in\n+ * GMX_RX_STATS_PKTS_BAD.  Pause packets can be optionally dropped or\n+ * forwarded based on the GMX_RX_FRM_CTL[CTL_DRP] bit.  This count\n+ * increments regardless of whether the packet is dropped.  Pause packets\n+ * will never be counted in GMX_RX_STATS_PKTS.  Packets dropped due the dmac\n+ * filter will be counted in GMX_RX_STATS_PKTS_DMAC and not here.\n+ */\n+union cvmx_gmxx_rxx_stats_pkts_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_stats_pkts_ctl cvmx_gmxx_rxx_stats_pkts_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_stats_pkts_dmac\n+ *\n+ * Count of all packets received that were dropped by the dmac filter.\n+ * Packets that match the DMAC will be dropped and counted here regardless\n+ * of if they were bad packets.  These packets will never be counted in\n+ * GMX_RX_STATS_PKTS.\n+ * Some packets that were not able to satisify the DECISION_CNT may not\n+ * actually be dropped by Octeon, but they will be counted here as if they\n+ * were dropped.\n+ */\n+union cvmx_gmxx_rxx_stats_pkts_dmac {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_dmac_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_stats_pkts_dmac cvmx_gmxx_rxx_stats_pkts_dmac_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_stats_pkts_drp\n+ *\n+ * Count of all packets received that were dropped due to a full receive FIFO.\n+ * This counts both partial packets in which there was enough space in the RX\n+ * FIFO to begin to buffer and the packet and total drops in which no packet was\n+ * sent to PKI.  This counts good and bad packets received - all packets dropped\n+ * by the FIFO.  It does not count packets dropped by the dmac or pause packet\n+ * filters.\n+ */\n+union cvmx_gmxx_rxx_stats_pkts_drp {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_stats_pkts_drp_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_stats_pkts_drp cvmx_gmxx_rxx_stats_pkts_drp_t;\n+\n+/**\n+ * cvmx_gmx#_rx#_udd_skp\n+ *\n+ * GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data\n+ *\n+ *\n+ * Notes:\n+ * (1) The skip bytes are part of the packet and will be sent down the NCB\n+ *     packet interface and will be handled by PKI.\n+ *\n+ * (2) The system can determine if the UDD bytes are included in the FCS check\n+ *     by using the FCSSEL field - if the FCS check is enabled.\n+ *\n+ * (3) Assume that the preamble/sfd is always at the start of the frame - even\n+ *     before UDD bytes.  In most cases, there will be no preamble in these\n+ *     cases since it will be packet interface in direct communication to\n+ *     another packet interface (MAC to MAC) without a PHY involved.\n+ *\n+ * (4) We can still do address filtering and control packet filtering is the\n+ *     user desires.\n+ *\n+ * (5) UDD_SKP must be 0 in half-duplex operation unless\n+ *     GMX_RX_FRM_CTL[PRE_CHK] is clear.  If GMX_RX_FRM_CTL[PRE_CHK] is clear,\n+ *     then UDD_SKP will normally be 8.\n+ *\n+ * (6) In all cases, the UDD bytes will be sent down the packet interface as\n+ *     part of the packet.  The UDD bytes are never stripped from the actual\n+ *     packet.\n+ *\n+ * (7) If LEN != 0, then GMX_RX_FRM_CHK[LENERR] will be disabled and GMX_RX_INT_REG[LENERR] will be zero\n+ */\n+union cvmx_gmxx_rxx_udd_skp {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 fcssel : 1;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 len : 7;\n+\t} s;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn30xx;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn31xx;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn38xx;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn38xxp2;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn50xx;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn52xx;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn52xxp1;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn56xx;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn56xxp1;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn58xx;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn58xxp1;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn61xx;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn63xx;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn63xxp1;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn66xx;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn68xx;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn70xx;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cn70xxp1;\n+\tstruct cvmx_gmxx_rxx_udd_skp_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rxx_udd_skp cvmx_gmxx_rxx_udd_skp_t;\n+\n+/**\n+ * cvmx_gmx#_rx_bp_drop#\n+ *\n+ * GMX_RX_BP_DROP = FIFO mark for packet drop\n+ *\n+ *\n+ * Notes:\n+ * The actual watermark is dynamic with respect to the GMX_RX_PRTS\n+ * register.  The GMX_RX_PRTS controls the depth of the port's\n+ * FIFO so as ports are added or removed, the drop point may change.\n+ *\n+ * In XAUI mode prt0 is used for checking.\n+ */\n+union cvmx_gmxx_rx_bp_dropx {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 mark : 6;\n+\t} s;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn30xx;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn31xx;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn38xx;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn38xxp2;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn50xx;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn52xx;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn52xxp1;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn56xx;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn56xxp1;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn58xx;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn58xxp1;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn61xx;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn63xx;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn63xxp1;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn66xx;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn68xx;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn68xxp1;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn70xx;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cn70xxp1;\n+\tstruct cvmx_gmxx_rx_bp_dropx_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rx_bp_dropx cvmx_gmxx_rx_bp_dropx_t;\n+\n+/**\n+ * cvmx_gmx#_rx_bp_off#\n+ *\n+ * GMX_RX_BP_OFF = Lowater mark for packet drop\n+ *\n+ *\n+ * Notes:\n+ * In XAUI mode, prt0 is used for checking.\n+ *\n+ */\n+union cvmx_gmxx_rx_bp_offx {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rx_bp_offx_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 mark : 6;\n+\t} s;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn30xx;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn31xx;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn38xx;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn38xxp2;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn50xx;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn52xx;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn52xxp1;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn56xx;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn56xxp1;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn58xx;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn58xxp1;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn61xx;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn63xx;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn63xxp1;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn66xx;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn68xx;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn68xxp1;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn70xx;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cn70xxp1;\n+\tstruct cvmx_gmxx_rx_bp_offx_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rx_bp_offx cvmx_gmxx_rx_bp_offx_t;\n+\n+/**\n+ * cvmx_gmx#_rx_bp_on#\n+ *\n+ * GMX_RX_BP_ON = Hiwater mark for port/interface backpressure\n+ *\n+ *\n+ * Notes:\n+ * In XAUI mode, prt0 is used for checking.\n+ *\n+ */\n+union cvmx_gmxx_rx_bp_onx {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rx_bp_onx_s {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 mark : 11;\n+\t} s;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 mark : 9;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn38xx;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn38xxp2;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn52xx;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn52xxp1;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn56xx;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn56xxp1;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn58xx;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn58xxp1;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn61xx;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn63xx;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn63xxp1;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn66xx;\n+\tstruct cvmx_gmxx_rx_bp_onx_s cn68xx;\n+\tstruct cvmx_gmxx_rx_bp_onx_s cn68xxp1;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn70xx;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cn70xxp1;\n+\tstruct cvmx_gmxx_rx_bp_onx_cn30xx cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rx_bp_onx cvmx_gmxx_rx_bp_onx_t;\n+\n+/**\n+ * cvmx_gmx#_rx_hg2_status\n+ *\n+ * ** HG2 message CSRs\n+ *\n+ */\n+union cvmx_gmxx_rx_hg2_status {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rx_hg2_status_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 phtim2go : 16;\n+\t\tu64 xof : 16;\n+\t\tu64 lgtim2go : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_rx_hg2_status_s cn52xx;\n+\tstruct cvmx_gmxx_rx_hg2_status_s cn52xxp1;\n+\tstruct cvmx_gmxx_rx_hg2_status_s cn56xx;\n+\tstruct cvmx_gmxx_rx_hg2_status_s cn61xx;\n+\tstruct cvmx_gmxx_rx_hg2_status_s cn63xx;\n+\tstruct cvmx_gmxx_rx_hg2_status_s cn63xxp1;\n+\tstruct cvmx_gmxx_rx_hg2_status_s cn66xx;\n+\tstruct cvmx_gmxx_rx_hg2_status_s cn68xx;\n+\tstruct cvmx_gmxx_rx_hg2_status_s cn68xxp1;\n+\tstruct cvmx_gmxx_rx_hg2_status_s cn70xx;\n+\tstruct cvmx_gmxx_rx_hg2_status_s cn70xxp1;\n+\tstruct cvmx_gmxx_rx_hg2_status_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rx_hg2_status cvmx_gmxx_rx_hg2_status_t;\n+\n+/**\n+ * cvmx_gmx#_rx_pass_en\n+ *\n+ * GMX_RX_PASS_EN = Packet pass through mode enable\n+ *\n+ * When both Octane ports are running in Spi4 mode, packets can be directly\n+ * passed from one SPX interface to the other without being processed by the\n+ * core or PP's.  The register has one bit for each port to enable the pass\n+ * through feature.\n+ *\n+ * Notes:\n+ * (1) Can only be used in dual Spi4 configs\n+ *\n+ * (2) The mapped pass through output port cannot be the destination port for\n+ *     any Octane core traffic.\n+ */\n+union cvmx_gmxx_rx_pass_en {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rx_pass_en_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 en : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_rx_pass_en_s cn38xx;\n+\tstruct cvmx_gmxx_rx_pass_en_s cn38xxp2;\n+\tstruct cvmx_gmxx_rx_pass_en_s cn58xx;\n+\tstruct cvmx_gmxx_rx_pass_en_s cn58xxp1;\n+};\n+\n+typedef union cvmx_gmxx_rx_pass_en cvmx_gmxx_rx_pass_en_t;\n+\n+/**\n+ * cvmx_gmx#_rx_pass_map#\n+ *\n+ * GMX_RX_PASS_MAP = Packet pass through port map\n+ *\n+ */\n+union cvmx_gmxx_rx_pass_mapx {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rx_pass_mapx_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 dprt : 4;\n+\t} s;\n+\tstruct cvmx_gmxx_rx_pass_mapx_s cn38xx;\n+\tstruct cvmx_gmxx_rx_pass_mapx_s cn38xxp2;\n+\tstruct cvmx_gmxx_rx_pass_mapx_s cn58xx;\n+\tstruct cvmx_gmxx_rx_pass_mapx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_gmxx_rx_pass_mapx cvmx_gmxx_rx_pass_mapx_t;\n+\n+/**\n+ * cvmx_gmx#_rx_prt_info\n+ *\n+ * GMX_RX_PRT_INFO = Report the RX status for port\n+ *\n+ *\n+ * Notes:\n+ * In XAUI mode, only the lsb (corresponding to port0) of DROP and COMMIT are used.\n+ *\n+ */\n+union cvmx_gmxx_rx_prt_info {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rx_prt_info_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 drop : 16;\n+\t\tu64 commit : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_rx_prt_info_cn30xx {\n+\t\tu64 reserved_19_63 : 45;\n+\t\tu64 drop : 3;\n+\t\tu64 reserved_3_15 : 13;\n+\t\tu64 commit : 3;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_rx_prt_info_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_rx_prt_info_s cn38xx;\n+\tstruct cvmx_gmxx_rx_prt_info_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_rx_prt_info_cn52xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 drop : 4;\n+\t\tu64 reserved_4_15 : 12;\n+\t\tu64 commit : 4;\n+\t} cn52xx;\n+\tstruct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1;\n+\tstruct cvmx_gmxx_rx_prt_info_cn52xx cn56xx;\n+\tstruct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1;\n+\tstruct cvmx_gmxx_rx_prt_info_s cn58xx;\n+\tstruct cvmx_gmxx_rx_prt_info_s cn58xxp1;\n+\tstruct cvmx_gmxx_rx_prt_info_cn52xx cn61xx;\n+\tstruct cvmx_gmxx_rx_prt_info_cn52xx cn63xx;\n+\tstruct cvmx_gmxx_rx_prt_info_cn52xx cn63xxp1;\n+\tstruct cvmx_gmxx_rx_prt_info_cn52xx cn66xx;\n+\tstruct cvmx_gmxx_rx_prt_info_cn52xx cn68xx;\n+\tstruct cvmx_gmxx_rx_prt_info_cn52xx cn68xxp1;\n+\tstruct cvmx_gmxx_rx_prt_info_cn52xx cn70xx;\n+\tstruct cvmx_gmxx_rx_prt_info_cn52xx cn70xxp1;\n+\tstruct cvmx_gmxx_rx_prt_info_cnf71xx {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 drop : 2;\n+\t\tu64 reserved_2_15 : 14;\n+\t\tu64 commit : 2;\n+\t} cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rx_prt_info cvmx_gmxx_rx_prt_info_t;\n+\n+/**\n+ * cvmx_gmx#_rx_prts\n+ *\n+ * GMX_RX_PRTS = Number of FIFOs to carve the RX buffer into\n+ *\n+ *\n+ * Notes:\n+ * GMX_RX_PRTS[PRTS] must be set to '1' in XAUI mode.\n+ *\n+ */\n+union cvmx_gmxx_rx_prts {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rx_prts_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 prts : 3;\n+\t} s;\n+\tstruct cvmx_gmxx_rx_prts_s cn30xx;\n+\tstruct cvmx_gmxx_rx_prts_s cn31xx;\n+\tstruct cvmx_gmxx_rx_prts_s cn38xx;\n+\tstruct cvmx_gmxx_rx_prts_s cn38xxp2;\n+\tstruct cvmx_gmxx_rx_prts_s cn50xx;\n+\tstruct cvmx_gmxx_rx_prts_s cn52xx;\n+\tstruct cvmx_gmxx_rx_prts_s cn52xxp1;\n+\tstruct cvmx_gmxx_rx_prts_s cn56xx;\n+\tstruct cvmx_gmxx_rx_prts_s cn56xxp1;\n+\tstruct cvmx_gmxx_rx_prts_s cn58xx;\n+\tstruct cvmx_gmxx_rx_prts_s cn58xxp1;\n+\tstruct cvmx_gmxx_rx_prts_s cn61xx;\n+\tstruct cvmx_gmxx_rx_prts_s cn63xx;\n+\tstruct cvmx_gmxx_rx_prts_s cn63xxp1;\n+\tstruct cvmx_gmxx_rx_prts_s cn66xx;\n+\tstruct cvmx_gmxx_rx_prts_s cn68xx;\n+\tstruct cvmx_gmxx_rx_prts_s cn68xxp1;\n+\tstruct cvmx_gmxx_rx_prts_s cn70xx;\n+\tstruct cvmx_gmxx_rx_prts_s cn70xxp1;\n+\tstruct cvmx_gmxx_rx_prts_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rx_prts cvmx_gmxx_rx_prts_t;\n+\n+/**\n+ * cvmx_gmx#_rx_tx_status\n+ *\n+ * GMX_RX_TX_STATUS = GMX RX/TX Status\n+ *\n+ */\n+union cvmx_gmxx_rx_tx_status {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rx_tx_status_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 tx : 3;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 rx : 3;\n+\t} s;\n+\tstruct cvmx_gmxx_rx_tx_status_s cn30xx;\n+\tstruct cvmx_gmxx_rx_tx_status_s cn31xx;\n+\tstruct cvmx_gmxx_rx_tx_status_s cn50xx;\n+};\n+\n+typedef union cvmx_gmxx_rx_tx_status cvmx_gmxx_rx_tx_status_t;\n+\n+/**\n+ * cvmx_gmx#_rx_xaui_bad_col\n+ */\n+union cvmx_gmxx_rx_xaui_bad_col {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 val : 1;\n+\t\tu64 state : 3;\n+\t\tu64 lane_rxc : 4;\n+\t\tu64 lane_rxd : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cn52xx;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cn56xx;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cn61xx;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cn63xx;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cn63xxp1;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cn66xx;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cn68xx;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cn68xxp1;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cn70xx;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cn70xxp1;\n+\tstruct cvmx_gmxx_rx_xaui_bad_col_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rx_xaui_bad_col cvmx_gmxx_rx_xaui_bad_col_t;\n+\n+/**\n+ * cvmx_gmx#_rx_xaui_ctl\n+ */\n+union cvmx_gmxx_rx_xaui_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 status : 2;\n+\t} s;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cn52xx;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cn56xx;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cn61xx;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cn63xx;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cn63xxp1;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cn66xx;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cn68xx;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cn68xxp1;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cn70xxp1;\n+\tstruct cvmx_gmxx_rx_xaui_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_rx_xaui_ctl cvmx_gmxx_rx_xaui_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_rxaui_ctl\n+ */\n+union cvmx_gmxx_rxaui_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_rxaui_ctl_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 disparity : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_rxaui_ctl_s cn68xx;\n+\tstruct cvmx_gmxx_rxaui_ctl_s cn68xxp1;\n+\tstruct cvmx_gmxx_rxaui_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_rxaui_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_gmxx_rxaui_ctl cvmx_gmxx_rxaui_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_smac#\n+ *\n+ * GMX_SMAC = Packet SMAC\n+ *\n+ */\n+union cvmx_gmxx_smacx {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_smacx_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 smac : 48;\n+\t} s;\n+\tstruct cvmx_gmxx_smacx_s cn30xx;\n+\tstruct cvmx_gmxx_smacx_s cn31xx;\n+\tstruct cvmx_gmxx_smacx_s cn38xx;\n+\tstruct cvmx_gmxx_smacx_s cn38xxp2;\n+\tstruct cvmx_gmxx_smacx_s cn50xx;\n+\tstruct cvmx_gmxx_smacx_s cn52xx;\n+\tstruct cvmx_gmxx_smacx_s cn52xxp1;\n+\tstruct cvmx_gmxx_smacx_s cn56xx;\n+\tstruct cvmx_gmxx_smacx_s cn56xxp1;\n+\tstruct cvmx_gmxx_smacx_s cn58xx;\n+\tstruct cvmx_gmxx_smacx_s cn58xxp1;\n+\tstruct cvmx_gmxx_smacx_s cn61xx;\n+\tstruct cvmx_gmxx_smacx_s cn63xx;\n+\tstruct cvmx_gmxx_smacx_s cn63xxp1;\n+\tstruct cvmx_gmxx_smacx_s cn66xx;\n+\tstruct cvmx_gmxx_smacx_s cn68xx;\n+\tstruct cvmx_gmxx_smacx_s cn68xxp1;\n+\tstruct cvmx_gmxx_smacx_s cn70xx;\n+\tstruct cvmx_gmxx_smacx_s cn70xxp1;\n+\tstruct cvmx_gmxx_smacx_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_smacx cvmx_gmxx_smacx_t;\n+\n+/**\n+ * cvmx_gmx#_soft_bist\n+ *\n+ * GMX_SOFT_BIST = Software BIST Control\n+ *\n+ */\n+union cvmx_gmxx_soft_bist {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_soft_bist_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 start_bist : 1;\n+\t\tu64 clear_bist : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_soft_bist_s cn63xx;\n+\tstruct cvmx_gmxx_soft_bist_s cn63xxp1;\n+\tstruct cvmx_gmxx_soft_bist_s cn66xx;\n+\tstruct cvmx_gmxx_soft_bist_s cn68xx;\n+\tstruct cvmx_gmxx_soft_bist_s cn68xxp1;\n+};\n+\n+typedef union cvmx_gmxx_soft_bist cvmx_gmxx_soft_bist_t;\n+\n+/**\n+ * cvmx_gmx#_stat_bp\n+ *\n+ * GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation\n+ *\n+ *\n+ * Notes:\n+ * It has no relationship with the TX FIFO per se.  The TX engine sends packets\n+ * from PKO and upon completion, sends a command to the TX stats block for an\n+ * update based on the packet size.  The stats operation can take a few cycles -\n+ * normally not enough to be visible considering the 64B min packet size that is\n+ * ethernet convention.\n+ *\n+ * In the rare case in which SW attempted to schedule really, really, small packets\n+ * or the sclk (6xxx) is running ass-slow, then the stats updates may not happen in\n+ * real time and can back up the TX engine.\n+ *\n+ * This counter is the number of cycles in which the TX engine was stalled.  In\n+ * normal operation, it should always be zeros.\n+ */\n+union cvmx_gmxx_stat_bp {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_stat_bp_s {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 bp : 1;\n+\t\tu64 cnt : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_stat_bp_s cn30xx;\n+\tstruct cvmx_gmxx_stat_bp_s cn31xx;\n+\tstruct cvmx_gmxx_stat_bp_s cn38xx;\n+\tstruct cvmx_gmxx_stat_bp_s cn38xxp2;\n+\tstruct cvmx_gmxx_stat_bp_s cn50xx;\n+\tstruct cvmx_gmxx_stat_bp_s cn52xx;\n+\tstruct cvmx_gmxx_stat_bp_s cn52xxp1;\n+\tstruct cvmx_gmxx_stat_bp_s cn56xx;\n+\tstruct cvmx_gmxx_stat_bp_s cn56xxp1;\n+\tstruct cvmx_gmxx_stat_bp_s cn58xx;\n+\tstruct cvmx_gmxx_stat_bp_s cn58xxp1;\n+\tstruct cvmx_gmxx_stat_bp_s cn61xx;\n+\tstruct cvmx_gmxx_stat_bp_s cn63xx;\n+\tstruct cvmx_gmxx_stat_bp_s cn63xxp1;\n+\tstruct cvmx_gmxx_stat_bp_s cn66xx;\n+\tstruct cvmx_gmxx_stat_bp_s cn68xx;\n+\tstruct cvmx_gmxx_stat_bp_s cn68xxp1;\n+\tstruct cvmx_gmxx_stat_bp_s cn70xx;\n+\tstruct cvmx_gmxx_stat_bp_s cn70xxp1;\n+\tstruct cvmx_gmxx_stat_bp_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_stat_bp cvmx_gmxx_stat_bp_t;\n+\n+/**\n+ * cvmx_gmx#_tb_reg\n+ *\n+ * DON'T PUT IN HRM*\n+ *\n+ */\n+union cvmx_gmxx_tb_reg {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tb_reg_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 wr_magic : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_tb_reg_s cn61xx;\n+\tstruct cvmx_gmxx_tb_reg_s cn66xx;\n+\tstruct cvmx_gmxx_tb_reg_s cn68xx;\n+\tstruct cvmx_gmxx_tb_reg_s cn70xx;\n+\tstruct cvmx_gmxx_tb_reg_s cn70xxp1;\n+\tstruct cvmx_gmxx_tb_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tb_reg cvmx_gmxx_tb_reg_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_append\n+ *\n+ * GMX_TX_APPEND = Packet TX Append Control\n+ *\n+ */\n+union cvmx_gmxx_txx_append {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_append_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 force_fcs : 1;\n+\t\tu64 fcs : 1;\n+\t\tu64 pad : 1;\n+\t\tu64 preamble : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_append_s cn30xx;\n+\tstruct cvmx_gmxx_txx_append_s cn31xx;\n+\tstruct cvmx_gmxx_txx_append_s cn38xx;\n+\tstruct cvmx_gmxx_txx_append_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_append_s cn50xx;\n+\tstruct cvmx_gmxx_txx_append_s cn52xx;\n+\tstruct cvmx_gmxx_txx_append_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_append_s cn56xx;\n+\tstruct cvmx_gmxx_txx_append_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_append_s cn58xx;\n+\tstruct cvmx_gmxx_txx_append_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_append_s cn61xx;\n+\tstruct cvmx_gmxx_txx_append_s cn63xx;\n+\tstruct cvmx_gmxx_txx_append_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_append_s cn66xx;\n+\tstruct cvmx_gmxx_txx_append_s cn68xx;\n+\tstruct cvmx_gmxx_txx_append_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_append_s cn70xx;\n+\tstruct cvmx_gmxx_txx_append_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_append_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_append cvmx_gmxx_txx_append_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_bck_crdt\n+ *\n+ * gmi_tx_bck to gmi_tx_out credit count register\n+ *\n+ */\n+union cvmx_gmxx_txx_bck_crdt {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_bck_crdt_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 cnt : 4;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_bck_crdt_s cn70xx;\n+\tstruct cvmx_gmxx_txx_bck_crdt_s cn70xxp1;\n+};\n+\n+typedef union cvmx_gmxx_txx_bck_crdt cvmx_gmxx_txx_bck_crdt_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_burst\n+ *\n+ * GMX_TX_BURST = Packet TX Burst Counter\n+ *\n+ */\n+union cvmx_gmxx_txx_burst {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_burst_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 burst : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_burst_s cn30xx;\n+\tstruct cvmx_gmxx_txx_burst_s cn31xx;\n+\tstruct cvmx_gmxx_txx_burst_s cn38xx;\n+\tstruct cvmx_gmxx_txx_burst_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_burst_s cn50xx;\n+\tstruct cvmx_gmxx_txx_burst_s cn52xx;\n+\tstruct cvmx_gmxx_txx_burst_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_burst_s cn56xx;\n+\tstruct cvmx_gmxx_txx_burst_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_burst_s cn58xx;\n+\tstruct cvmx_gmxx_txx_burst_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_burst_s cn61xx;\n+\tstruct cvmx_gmxx_txx_burst_s cn63xx;\n+\tstruct cvmx_gmxx_txx_burst_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_burst_s cn66xx;\n+\tstruct cvmx_gmxx_txx_burst_s cn68xx;\n+\tstruct cvmx_gmxx_txx_burst_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_burst_s cn70xx;\n+\tstruct cvmx_gmxx_txx_burst_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_burst_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_burst cvmx_gmxx_txx_burst_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_cbfc_xoff\n+ */\n+union cvmx_gmxx_txx_cbfc_xoff {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_cbfc_xoff_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 xoff : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_cbfc_xoff_s cn52xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xoff_s cn56xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xoff_s cn61xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xoff_s cn63xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xoff_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_cbfc_xoff_s cn66xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xoff_s cn68xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xoff_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_cbfc_xoff_s cn70xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xoff_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_cbfc_xoff_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_cbfc_xoff cvmx_gmxx_txx_cbfc_xoff_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_cbfc_xon\n+ */\n+union cvmx_gmxx_txx_cbfc_xon {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_cbfc_xon_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 xon : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_cbfc_xon_s cn52xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xon_s cn56xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xon_s cn61xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xon_s cn63xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xon_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_cbfc_xon_s cn66xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xon_s cn68xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xon_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_cbfc_xon_s cn70xx;\n+\tstruct cvmx_gmxx_txx_cbfc_xon_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_cbfc_xon_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_cbfc_xon cvmx_gmxx_txx_cbfc_xon_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_clk\n+ *\n+ * Per Port\n+ *\n+ *\n+ * GMX_TX_CLK = RGMII TX Clock Generation Register\n+ *\n+ * Notes:\n+ * Programming Restrictions:\n+ *  (1) In RGMII mode, if GMX_PRT_CFG[SPEED]==0, then CLK_CNT must be > 1.\n+ *  (2) In MII mode, CLK_CNT == 1\n+ *  (3) In RGMII or GMII mode, if CLK_CNT==0, Octeon will not generate a tx clock.\n+ *\n+ * RGMII Example:\n+ *  Given a 125MHz PLL reference clock...\n+ *   CLK_CNT ==  1 ==> 125.0MHz TXC clock period (8ns* 1)\n+ *   CLK_CNT ==  5 ==>  25.0MHz TXC clock period (8ns* 5)\n+ *   CLK_CNT == 50 ==>   2.5MHz TXC clock period (8ns*50)\n+ */\n+union cvmx_gmxx_txx_clk {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_clk_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 clk_cnt : 6;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_clk_s cn30xx;\n+\tstruct cvmx_gmxx_txx_clk_s cn31xx;\n+\tstruct cvmx_gmxx_txx_clk_s cn38xx;\n+\tstruct cvmx_gmxx_txx_clk_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_clk_s cn50xx;\n+\tstruct cvmx_gmxx_txx_clk_s cn58xx;\n+\tstruct cvmx_gmxx_txx_clk_s cn58xxp1;\n+};\n+\n+typedef union cvmx_gmxx_txx_clk cvmx_gmxx_txx_clk_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_ctl\n+ *\n+ * GMX_TX_CTL = TX Control register\n+ *\n+ */\n+union cvmx_gmxx_txx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_ctl_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 xsdef_en : 1;\n+\t\tu64 xscol_en : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_ctl_s cn30xx;\n+\tstruct cvmx_gmxx_txx_ctl_s cn31xx;\n+\tstruct cvmx_gmxx_txx_ctl_s cn38xx;\n+\tstruct cvmx_gmxx_txx_ctl_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_ctl_s cn50xx;\n+\tstruct cvmx_gmxx_txx_ctl_s cn52xx;\n+\tstruct cvmx_gmxx_txx_ctl_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_ctl_s cn56xx;\n+\tstruct cvmx_gmxx_txx_ctl_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_ctl_s cn58xx;\n+\tstruct cvmx_gmxx_txx_ctl_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_ctl_s cn61xx;\n+\tstruct cvmx_gmxx_txx_ctl_s cn63xx;\n+\tstruct cvmx_gmxx_txx_ctl_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_ctl_s cn66xx;\n+\tstruct cvmx_gmxx_txx_ctl_s cn68xx;\n+\tstruct cvmx_gmxx_txx_ctl_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_txx_ctl_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_ctl cvmx_gmxx_txx_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_jam_mode\n+ */\n+union cvmx_gmxx_txx_jam_mode {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_jam_mode_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 mode : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_jam_mode_s cn70xx;\n+\tstruct cvmx_gmxx_txx_jam_mode_s cn70xxp1;\n+};\n+\n+typedef union cvmx_gmxx_txx_jam_mode cvmx_gmxx_txx_jam_mode_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_min_pkt\n+ *\n+ * GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size)\n+ *\n+ */\n+union cvmx_gmxx_txx_min_pkt {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_min_pkt_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 min_size : 8;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn30xx;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn31xx;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn38xx;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn50xx;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn52xx;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn56xx;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn58xx;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn61xx;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn63xx;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn66xx;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn68xx;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn70xx;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_min_pkt_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_min_pkt cvmx_gmxx_txx_min_pkt_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_pause_pkt_interval\n+ *\n+ * GMX_TX_PAUSE_PKT_INTERVAL = Packet TX Pause Packet transmission interval - how often PAUSE packets will be sent\n+ *\n+ *\n+ * Notes:\n+ * Choosing proper values of GMX_TX_PAUSE_PKT_TIME[TIME] and\n+ * GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system\n+ * designer.  It is suggested that TIME be much greater than INTERVAL and\n+ * GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE\n+ * count and then when the backpressure condition is lifted, a PAUSE packet\n+ * with TIME==0 will be sent indicating that Octane is ready for additional\n+ * data.\n+ *\n+ * If the system chooses to not set GMX_TX_PAUSE_ZERO[SEND], then it is\n+ * suggested that TIME and INTERVAL are programmed such that they satisify the\n+ * following rule...\n+ *\n+ *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)\n+ *\n+ * where largest_pkt_size is that largest packet that the system can send\n+ * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size\n+ * of the PAUSE packet (normally 64B).\n+ */\n+union cvmx_gmxx_txx_pause_pkt_interval {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 interval : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn61xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn66xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn68xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn70xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_pause_pkt_interval_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_pause_pkt_interval cvmx_gmxx_txx_pause_pkt_interval_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_pause_pkt_time\n+ *\n+ * GMX_TX_PAUSE_PKT_TIME = Packet TX Pause Packet pause_time field\n+ *\n+ *\n+ * Notes:\n+ * Choosing proper values of GMX_TX_PAUSE_PKT_TIME[TIME] and\n+ * GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system\n+ * designer.  It is suggested that TIME be much greater than INTERVAL and\n+ * GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE\n+ * count and then when the backpressure condition is lifted, a PAUSE packet\n+ * with TIME==0 will be sent indicating that Octane is ready for additional\n+ * data.\n+ *\n+ * If the system chooses to not set GMX_TX_PAUSE_ZERO[SEND], then it is\n+ * suggested that TIME and INTERVAL are programmed such that they satisify the\n+ * following rule...\n+ *\n+ *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)\n+ *\n+ * where largest_pkt_size is that largest packet that the system can send\n+ * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size\n+ * of the PAUSE packet (normally 64B).\n+ */\n+union cvmx_gmxx_txx_pause_pkt_time {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 time : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn61xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn63xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn66xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn68xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn70xx;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_pause_pkt_time_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_pause_pkt_time cvmx_gmxx_txx_pause_pkt_time_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_pause_togo\n+ *\n+ * GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure\n+ *\n+ */\n+union cvmx_gmxx_txx_pause_togo {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_pause_togo_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 msg_time : 16;\n+\t\tu64 time : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_pause_togo_cn30xx {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 time : 16;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;\n+\tstruct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;\n+\tstruct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_txx_pause_togo_s cn52xx;\n+\tstruct cvmx_gmxx_txx_pause_togo_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_pause_togo_s cn56xx;\n+\tstruct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;\n+\tstruct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;\n+\tstruct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;\n+\tstruct cvmx_gmxx_txx_pause_togo_s cn61xx;\n+\tstruct cvmx_gmxx_txx_pause_togo_s cn63xx;\n+\tstruct cvmx_gmxx_txx_pause_togo_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_pause_togo_s cn66xx;\n+\tstruct cvmx_gmxx_txx_pause_togo_s cn68xx;\n+\tstruct cvmx_gmxx_txx_pause_togo_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_pause_togo_s cn70xx;\n+\tstruct cvmx_gmxx_txx_pause_togo_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_pause_togo_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_pause_togo cvmx_gmxx_txx_pause_togo_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_pause_zero\n+ *\n+ * GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure\n+ *\n+ */\n+union cvmx_gmxx_txx_pause_zero {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_pause_zero_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 send : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn30xx;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn31xx;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn38xx;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn50xx;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn52xx;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn56xx;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn58xx;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn61xx;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn63xx;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn66xx;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn68xx;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn70xx;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_pause_zero_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_pause_zero cvmx_gmxx_txx_pause_zero_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_pipe\n+ */\n+union cvmx_gmxx_txx_pipe {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_pipe_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 ign_bp : 1;\n+\t\tu64 reserved_21_31 : 11;\n+\t\tu64 nump : 5;\n+\t\tu64 reserved_7_15 : 9;\n+\t\tu64 base : 7;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_pipe_s cn68xx;\n+\tstruct cvmx_gmxx_txx_pipe_s cn68xxp1;\n+};\n+\n+typedef union cvmx_gmxx_txx_pipe cvmx_gmxx_txx_pipe_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_sgmii_ctl\n+ */\n+union cvmx_gmxx_txx_sgmii_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 align : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cn52xx;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cn56xx;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cn61xx;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cn63xx;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cn66xx;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cn68xx;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_sgmii_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_sgmii_ctl cvmx_gmxx_txx_sgmii_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_slot\n+ *\n+ * GMX_TX_SLOT = Packet TX Slottime Counter\n+ *\n+ */\n+union cvmx_gmxx_txx_slot {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_slot_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 slot : 10;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_slot_s cn30xx;\n+\tstruct cvmx_gmxx_txx_slot_s cn31xx;\n+\tstruct cvmx_gmxx_txx_slot_s cn38xx;\n+\tstruct cvmx_gmxx_txx_slot_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_slot_s cn50xx;\n+\tstruct cvmx_gmxx_txx_slot_s cn52xx;\n+\tstruct cvmx_gmxx_txx_slot_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_slot_s cn56xx;\n+\tstruct cvmx_gmxx_txx_slot_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_slot_s cn58xx;\n+\tstruct cvmx_gmxx_txx_slot_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_slot_s cn61xx;\n+\tstruct cvmx_gmxx_txx_slot_s cn63xx;\n+\tstruct cvmx_gmxx_txx_slot_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_slot_s cn66xx;\n+\tstruct cvmx_gmxx_txx_slot_s cn68xx;\n+\tstruct cvmx_gmxx_txx_slot_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_slot_s cn70xx;\n+\tstruct cvmx_gmxx_txx_slot_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_slot_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_slot cvmx_gmxx_txx_slot_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_soft_pause\n+ *\n+ * GMX_TX_SOFT_PAUSE = Packet TX Software Pause\n+ *\n+ */\n+union cvmx_gmxx_txx_soft_pause {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_soft_pause_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 time : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn30xx;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn31xx;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn38xx;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn50xx;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn52xx;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn56xx;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn58xx;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn61xx;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn63xx;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn66xx;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn68xx;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn70xx;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_soft_pause_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_soft_pause cvmx_gmxx_txx_soft_pause_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_stat0\n+ *\n+ * GMX_TX_STAT0 = GMX_TX_STATS_XSDEF / GMX_TX_STATS_XSCOL\n+ *\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_txx_stat0 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_stat0_s {\n+\t\tu64 xsdef : 32;\n+\t\tu64 xscol : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_stat0_s cn30xx;\n+\tstruct cvmx_gmxx_txx_stat0_s cn31xx;\n+\tstruct cvmx_gmxx_txx_stat0_s cn38xx;\n+\tstruct cvmx_gmxx_txx_stat0_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_stat0_s cn50xx;\n+\tstruct cvmx_gmxx_txx_stat0_s cn52xx;\n+\tstruct cvmx_gmxx_txx_stat0_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_stat0_s cn56xx;\n+\tstruct cvmx_gmxx_txx_stat0_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_stat0_s cn58xx;\n+\tstruct cvmx_gmxx_txx_stat0_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_stat0_s cn61xx;\n+\tstruct cvmx_gmxx_txx_stat0_s cn63xx;\n+\tstruct cvmx_gmxx_txx_stat0_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_stat0_s cn66xx;\n+\tstruct cvmx_gmxx_txx_stat0_s cn68xx;\n+\tstruct cvmx_gmxx_txx_stat0_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_stat0_s cn70xx;\n+\tstruct cvmx_gmxx_txx_stat0_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_stat0_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_stat0 cvmx_gmxx_txx_stat0_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_stat1\n+ *\n+ * GMX_TX_STAT1 = GMX_TX_STATS_SCOL  / GMX_TX_STATS_MCOL\n+ *\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_txx_stat1 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_stat1_s {\n+\t\tu64 scol : 32;\n+\t\tu64 mcol : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_stat1_s cn30xx;\n+\tstruct cvmx_gmxx_txx_stat1_s cn31xx;\n+\tstruct cvmx_gmxx_txx_stat1_s cn38xx;\n+\tstruct cvmx_gmxx_txx_stat1_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_stat1_s cn50xx;\n+\tstruct cvmx_gmxx_txx_stat1_s cn52xx;\n+\tstruct cvmx_gmxx_txx_stat1_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_stat1_s cn56xx;\n+\tstruct cvmx_gmxx_txx_stat1_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_stat1_s cn58xx;\n+\tstruct cvmx_gmxx_txx_stat1_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_stat1_s cn61xx;\n+\tstruct cvmx_gmxx_txx_stat1_s cn63xx;\n+\tstruct cvmx_gmxx_txx_stat1_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_stat1_s cn66xx;\n+\tstruct cvmx_gmxx_txx_stat1_s cn68xx;\n+\tstruct cvmx_gmxx_txx_stat1_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_stat1_s cn70xx;\n+\tstruct cvmx_gmxx_txx_stat1_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_stat1_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_stat1 cvmx_gmxx_txx_stat1_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_stat2\n+ *\n+ * GMX_TX_STAT2 = GMX_TX_STATS_OCTS\n+ *\n+ *\n+ * Notes:\n+ * - Octect counts are the sum of all data transmitted on the wire including\n+ *   packet data, pad bytes, fcs bytes, pause bytes, and jam bytes.  The octect\n+ *   counts do not include PREAMBLE byte or EXTEND cycles.\n+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_txx_stat2 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_stat2_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 octs : 48;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_stat2_s cn30xx;\n+\tstruct cvmx_gmxx_txx_stat2_s cn31xx;\n+\tstruct cvmx_gmxx_txx_stat2_s cn38xx;\n+\tstruct cvmx_gmxx_txx_stat2_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_stat2_s cn50xx;\n+\tstruct cvmx_gmxx_txx_stat2_s cn52xx;\n+\tstruct cvmx_gmxx_txx_stat2_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_stat2_s cn56xx;\n+\tstruct cvmx_gmxx_txx_stat2_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_stat2_s cn58xx;\n+\tstruct cvmx_gmxx_txx_stat2_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_stat2_s cn61xx;\n+\tstruct cvmx_gmxx_txx_stat2_s cn63xx;\n+\tstruct cvmx_gmxx_txx_stat2_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_stat2_s cn66xx;\n+\tstruct cvmx_gmxx_txx_stat2_s cn68xx;\n+\tstruct cvmx_gmxx_txx_stat2_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_stat2_s cn70xx;\n+\tstruct cvmx_gmxx_txx_stat2_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_stat2_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_stat2 cvmx_gmxx_txx_stat2_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_stat3\n+ *\n+ * GMX_TX_STAT3 = GMX_TX_STATS_PKTS\n+ *\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_txx_stat3 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_stat3_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 pkts : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_stat3_s cn30xx;\n+\tstruct cvmx_gmxx_txx_stat3_s cn31xx;\n+\tstruct cvmx_gmxx_txx_stat3_s cn38xx;\n+\tstruct cvmx_gmxx_txx_stat3_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_stat3_s cn50xx;\n+\tstruct cvmx_gmxx_txx_stat3_s cn52xx;\n+\tstruct cvmx_gmxx_txx_stat3_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_stat3_s cn56xx;\n+\tstruct cvmx_gmxx_txx_stat3_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_stat3_s cn58xx;\n+\tstruct cvmx_gmxx_txx_stat3_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_stat3_s cn61xx;\n+\tstruct cvmx_gmxx_txx_stat3_s cn63xx;\n+\tstruct cvmx_gmxx_txx_stat3_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_stat3_s cn66xx;\n+\tstruct cvmx_gmxx_txx_stat3_s cn68xx;\n+\tstruct cvmx_gmxx_txx_stat3_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_stat3_s cn70xx;\n+\tstruct cvmx_gmxx_txx_stat3_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_stat3_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_stat3 cvmx_gmxx_txx_stat3_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_stat4\n+ *\n+ * GMX_TX_STAT4 = GMX_TX_STATS_HIST1 (64) / GMX_TX_STATS_HIST0 (<64)\n+ *\n+ *\n+ * Notes:\n+ * - Packet length is the sum of all data transmitted on the wire for the given\n+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam\n+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.\n+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_txx_stat4 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_stat4_s {\n+\t\tu64 hist1 : 32;\n+\t\tu64 hist0 : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_stat4_s cn30xx;\n+\tstruct cvmx_gmxx_txx_stat4_s cn31xx;\n+\tstruct cvmx_gmxx_txx_stat4_s cn38xx;\n+\tstruct cvmx_gmxx_txx_stat4_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_stat4_s cn50xx;\n+\tstruct cvmx_gmxx_txx_stat4_s cn52xx;\n+\tstruct cvmx_gmxx_txx_stat4_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_stat4_s cn56xx;\n+\tstruct cvmx_gmxx_txx_stat4_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_stat4_s cn58xx;\n+\tstruct cvmx_gmxx_txx_stat4_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_stat4_s cn61xx;\n+\tstruct cvmx_gmxx_txx_stat4_s cn63xx;\n+\tstruct cvmx_gmxx_txx_stat4_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_stat4_s cn66xx;\n+\tstruct cvmx_gmxx_txx_stat4_s cn68xx;\n+\tstruct cvmx_gmxx_txx_stat4_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_stat4_s cn70xx;\n+\tstruct cvmx_gmxx_txx_stat4_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_stat4_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_stat4 cvmx_gmxx_txx_stat4_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_stat5\n+ *\n+ * GMX_TX_STAT5 = GMX_TX_STATS_HIST3 (128- 255) / GMX_TX_STATS_HIST2 (65- 127)\n+ *\n+ *\n+ * Notes:\n+ * - Packet length is the sum of all data transmitted on the wire for the given\n+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam\n+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.\n+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_txx_stat5 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_stat5_s {\n+\t\tu64 hist3 : 32;\n+\t\tu64 hist2 : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_stat5_s cn30xx;\n+\tstruct cvmx_gmxx_txx_stat5_s cn31xx;\n+\tstruct cvmx_gmxx_txx_stat5_s cn38xx;\n+\tstruct cvmx_gmxx_txx_stat5_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_stat5_s cn50xx;\n+\tstruct cvmx_gmxx_txx_stat5_s cn52xx;\n+\tstruct cvmx_gmxx_txx_stat5_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_stat5_s cn56xx;\n+\tstruct cvmx_gmxx_txx_stat5_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_stat5_s cn58xx;\n+\tstruct cvmx_gmxx_txx_stat5_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_stat5_s cn61xx;\n+\tstruct cvmx_gmxx_txx_stat5_s cn63xx;\n+\tstruct cvmx_gmxx_txx_stat5_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_stat5_s cn66xx;\n+\tstruct cvmx_gmxx_txx_stat5_s cn68xx;\n+\tstruct cvmx_gmxx_txx_stat5_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_stat5_s cn70xx;\n+\tstruct cvmx_gmxx_txx_stat5_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_stat5_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_stat5 cvmx_gmxx_txx_stat5_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_stat6\n+ *\n+ * GMX_TX_STAT6 = GMX_TX_STATS_HIST5 (512-1023) / GMX_TX_STATS_HIST4 (256-511)\n+ *\n+ *\n+ * Notes:\n+ * - Packet length is the sum of all data transmitted on the wire for the given\n+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam\n+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.\n+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_txx_stat6 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_stat6_s {\n+\t\tu64 hist5 : 32;\n+\t\tu64 hist4 : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_stat6_s cn30xx;\n+\tstruct cvmx_gmxx_txx_stat6_s cn31xx;\n+\tstruct cvmx_gmxx_txx_stat6_s cn38xx;\n+\tstruct cvmx_gmxx_txx_stat6_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_stat6_s cn50xx;\n+\tstruct cvmx_gmxx_txx_stat6_s cn52xx;\n+\tstruct cvmx_gmxx_txx_stat6_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_stat6_s cn56xx;\n+\tstruct cvmx_gmxx_txx_stat6_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_stat6_s cn58xx;\n+\tstruct cvmx_gmxx_txx_stat6_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_stat6_s cn61xx;\n+\tstruct cvmx_gmxx_txx_stat6_s cn63xx;\n+\tstruct cvmx_gmxx_txx_stat6_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_stat6_s cn66xx;\n+\tstruct cvmx_gmxx_txx_stat6_s cn68xx;\n+\tstruct cvmx_gmxx_txx_stat6_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_stat6_s cn70xx;\n+\tstruct cvmx_gmxx_txx_stat6_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_stat6_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_stat6 cvmx_gmxx_txx_stat6_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_stat7\n+ *\n+ * GMX_TX_STAT7 = GMX_TX_STATS_HIST7 (1024-1518) / GMX_TX_STATS_HIST6 (>1518)\n+ *\n+ *\n+ * Notes:\n+ * - Packet length is the sum of all data transmitted on the wire for the given\n+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam\n+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.\n+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_txx_stat7 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_stat7_s {\n+\t\tu64 hist7 : 32;\n+\t\tu64 hist6 : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_stat7_s cn30xx;\n+\tstruct cvmx_gmxx_txx_stat7_s cn31xx;\n+\tstruct cvmx_gmxx_txx_stat7_s cn38xx;\n+\tstruct cvmx_gmxx_txx_stat7_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_stat7_s cn50xx;\n+\tstruct cvmx_gmxx_txx_stat7_s cn52xx;\n+\tstruct cvmx_gmxx_txx_stat7_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_stat7_s cn56xx;\n+\tstruct cvmx_gmxx_txx_stat7_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_stat7_s cn58xx;\n+\tstruct cvmx_gmxx_txx_stat7_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_stat7_s cn61xx;\n+\tstruct cvmx_gmxx_txx_stat7_s cn63xx;\n+\tstruct cvmx_gmxx_txx_stat7_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_stat7_s cn66xx;\n+\tstruct cvmx_gmxx_txx_stat7_s cn68xx;\n+\tstruct cvmx_gmxx_txx_stat7_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_stat7_s cn70xx;\n+\tstruct cvmx_gmxx_txx_stat7_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_stat7_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_stat7 cvmx_gmxx_txx_stat7_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_stat8\n+ *\n+ * GMX_TX_STAT8 = GMX_TX_STATS_MCST  / GMX_TX_STATS_BCST\n+ *\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the\n+ *   packet.  GMX assumes that the DMAC lies in the first 6 bytes of the packet\n+ *   as per the 802.3 frame definition.  If the system requires additional data\n+ *   before the L2 header, then the MCST and BCST counters may not reflect\n+ *   reality and should be ignored by software.\n+ */\n+union cvmx_gmxx_txx_stat8 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_stat8_s {\n+\t\tu64 mcst : 32;\n+\t\tu64 bcst : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_stat8_s cn30xx;\n+\tstruct cvmx_gmxx_txx_stat8_s cn31xx;\n+\tstruct cvmx_gmxx_txx_stat8_s cn38xx;\n+\tstruct cvmx_gmxx_txx_stat8_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_stat8_s cn50xx;\n+\tstruct cvmx_gmxx_txx_stat8_s cn52xx;\n+\tstruct cvmx_gmxx_txx_stat8_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_stat8_s cn56xx;\n+\tstruct cvmx_gmxx_txx_stat8_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_stat8_s cn58xx;\n+\tstruct cvmx_gmxx_txx_stat8_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_stat8_s cn61xx;\n+\tstruct cvmx_gmxx_txx_stat8_s cn63xx;\n+\tstruct cvmx_gmxx_txx_stat8_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_stat8_s cn66xx;\n+\tstruct cvmx_gmxx_txx_stat8_s cn68xx;\n+\tstruct cvmx_gmxx_txx_stat8_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_stat8_s cn70xx;\n+\tstruct cvmx_gmxx_txx_stat8_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_stat8_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_stat8 cvmx_gmxx_txx_stat8_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_stat9\n+ *\n+ * GMX_TX_STAT9 = GMX_TX_STATS_UNDFLW / GMX_TX_STATS_CTL\n+ *\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ */\n+union cvmx_gmxx_txx_stat9 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_stat9_s {\n+\t\tu64 undflw : 32;\n+\t\tu64 ctl : 32;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_stat9_s cn30xx;\n+\tstruct cvmx_gmxx_txx_stat9_s cn31xx;\n+\tstruct cvmx_gmxx_txx_stat9_s cn38xx;\n+\tstruct cvmx_gmxx_txx_stat9_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_stat9_s cn50xx;\n+\tstruct cvmx_gmxx_txx_stat9_s cn52xx;\n+\tstruct cvmx_gmxx_txx_stat9_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_stat9_s cn56xx;\n+\tstruct cvmx_gmxx_txx_stat9_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_stat9_s cn58xx;\n+\tstruct cvmx_gmxx_txx_stat9_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_stat9_s cn61xx;\n+\tstruct cvmx_gmxx_txx_stat9_s cn63xx;\n+\tstruct cvmx_gmxx_txx_stat9_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_stat9_s cn66xx;\n+\tstruct cvmx_gmxx_txx_stat9_s cn68xx;\n+\tstruct cvmx_gmxx_txx_stat9_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_stat9_s cn70xx;\n+\tstruct cvmx_gmxx_txx_stat9_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_stat9_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_stat9 cvmx_gmxx_txx_stat9_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_stats_ctl\n+ *\n+ * GMX_TX_STATS_CTL = TX Stats Control register\n+ *\n+ */\n+union cvmx_gmxx_txx_stats_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 rd_clr : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn30xx;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn31xx;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn38xx;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn38xxp2;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn50xx;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn52xx;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn52xxp1;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn56xx;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn56xxp1;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn58xx;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn58xxp1;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn61xx;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn63xx;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn63xxp1;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn66xx;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn68xx;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cn70xxp1;\n+\tstruct cvmx_gmxx_txx_stats_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_stats_ctl cvmx_gmxx_txx_stats_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_tx#_thresh\n+ *\n+ * Per Port\n+ * GMX_TX_THRESH = Packet TX Threshold\n+ */\n+union cvmx_gmxx_txx_thresh {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_txx_thresh_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 cnt : 10;\n+\t} s;\n+\tstruct cvmx_gmxx_txx_thresh_cn30xx {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 cnt : 7;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_txx_thresh_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 cnt : 9;\n+\t} cn38xx;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn38xxp2;\n+\tstruct cvmx_gmxx_txx_thresh_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn52xx;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn52xxp1;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn56xx;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn56xxp1;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn58xx;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn58xxp1;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn61xx;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn63xx;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn63xxp1;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn66xx;\n+\tstruct cvmx_gmxx_txx_thresh_s cn68xx;\n+\tstruct cvmx_gmxx_txx_thresh_s cn68xxp1;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn70xx;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cn70xxp1;\n+\tstruct cvmx_gmxx_txx_thresh_cn38xx cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_txx_thresh cvmx_gmxx_txx_thresh_t;\n+\n+/**\n+ * cvmx_gmx#_tx_bp\n+ *\n+ * GMX_TX_BP = Packet Interface TX BackPressure Register\n+ *\n+ *\n+ * Notes:\n+ * In XAUI mode, only the lsb (corresponding to port0) of BP is used.\n+ *\n+ */\n+union cvmx_gmxx_tx_bp {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_bp_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 bp : 4;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_bp_cn30xx {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 bp : 3;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_tx_bp_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_tx_bp_s cn38xx;\n+\tstruct cvmx_gmxx_tx_bp_s cn38xxp2;\n+\tstruct cvmx_gmxx_tx_bp_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_tx_bp_s cn52xx;\n+\tstruct cvmx_gmxx_tx_bp_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_bp_s cn56xx;\n+\tstruct cvmx_gmxx_tx_bp_s cn56xxp1;\n+\tstruct cvmx_gmxx_tx_bp_s cn58xx;\n+\tstruct cvmx_gmxx_tx_bp_s cn58xxp1;\n+\tstruct cvmx_gmxx_tx_bp_s cn61xx;\n+\tstruct cvmx_gmxx_tx_bp_s cn63xx;\n+\tstruct cvmx_gmxx_tx_bp_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_bp_s cn66xx;\n+\tstruct cvmx_gmxx_tx_bp_s cn68xx;\n+\tstruct cvmx_gmxx_tx_bp_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_bp_s cn70xx;\n+\tstruct cvmx_gmxx_tx_bp_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_bp_cnf71xx {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 bp : 2;\n+\t} cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_bp cvmx_gmxx_tx_bp_t;\n+\n+/**\n+ * cvmx_gmx#_tx_clk_msk#\n+ *\n+ * GMX_TX_CLK_MSK = GMX Clock Select\n+ *\n+ */\n+union cvmx_gmxx_tx_clk_mskx {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_clk_mskx_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 msk : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_clk_mskx_s cn30xx;\n+\tstruct cvmx_gmxx_tx_clk_mskx_s cn50xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_clk_mskx cvmx_gmxx_tx_clk_mskx_t;\n+\n+/**\n+ * cvmx_gmx#_tx_col_attempt\n+ *\n+ * GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame\n+ *\n+ */\n+union cvmx_gmxx_tx_col_attempt {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_col_attempt_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 limit : 5;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn30xx;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn31xx;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn38xx;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn38xxp2;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn50xx;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn52xx;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn56xx;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn56xxp1;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn58xx;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn58xxp1;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn61xx;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn63xx;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn66xx;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn68xx;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn70xx;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_col_attempt_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_col_attempt cvmx_gmxx_tx_col_attempt_t;\n+\n+/**\n+ * cvmx_gmx#_tx_corrupt\n+ *\n+ * GMX_TX_CORRUPT = TX - Corrupt TX packets with the ERR bit set\n+ *\n+ *\n+ * Notes:\n+ * Packets sent from PKO with the ERR wire asserted will be corrupted by\n+ * the transmitter if CORRUPT[prt] is set (XAUI uses prt==0).\n+ *\n+ * Corruption means that GMX will send a bad FCS value.  If GMX_TX_APPEND[FCS]\n+ * is clear then no FCS is sent and the GMX cannot corrupt it.  The corrupt FCS\n+ * value is 0xeeeeeeee for SGMII/1000Base-X and 4 bytes of the error\n+ * propagation code in XAUI mode.\n+ */\n+union cvmx_gmxx_tx_corrupt {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_corrupt_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 corrupt : 4;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_corrupt_cn30xx {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 corrupt : 3;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_tx_corrupt_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn38xx;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn38xxp2;\n+\tstruct cvmx_gmxx_tx_corrupt_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn52xx;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn56xx;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn56xxp1;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn58xx;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn58xxp1;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn61xx;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn63xx;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn66xx;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn68xx;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn70xx;\n+\tstruct cvmx_gmxx_tx_corrupt_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_corrupt_cnf71xx {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 corrupt : 2;\n+\t} cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_corrupt cvmx_gmxx_tx_corrupt_t;\n+\n+/**\n+ * cvmx_gmx#_tx_hg2_reg1\n+ *\n+ * Notes:\n+ * The TX_XOF[15:0] field in GMX(0)_TX_HG2_REG1 and the TX_XON[15:0] field in\n+ * GMX(0)_TX_HG2_REG2 register map to the same 16 physical flops. When written with address of\n+ * GMX(0)_TX_HG2_REG1, it will exhibit write 1 to set behavior and when written with address of\n+ * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.\n+ * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.\n+ */\n+union cvmx_gmxx_tx_hg2_reg1 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 tx_xof : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s cn52xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s cn56xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s cn61xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s cn63xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s cn66xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s cn68xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s cn70xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_hg2_reg1_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_hg2_reg1 cvmx_gmxx_tx_hg2_reg1_t;\n+\n+/**\n+ * cvmx_gmx#_tx_hg2_reg2\n+ *\n+ * Notes:\n+ * The TX_XOF[15:0] field in GMX(0)_TX_HG2_REG1 and the TX_XON[15:0] field in\n+ * GMX(0)_TX_HG2_REG2 register map to the same 16 physical flops. When written with address  of\n+ * GMX(0)_TX_HG2_REG1, it will exhibit write 1 to set behavior and when written with address of\n+ * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.\n+ * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.\n+ */\n+union cvmx_gmxx_tx_hg2_reg2 {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 tx_xon : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s cn52xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s cn56xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s cn61xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s cn63xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s cn66xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s cn68xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s cn70xx;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_hg2_reg2_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_hg2_reg2 cvmx_gmxx_tx_hg2_reg2_t;\n+\n+/**\n+ * cvmx_gmx#_tx_ifg\n+ *\n+ * GMX_TX_IFG = Packet TX Interframe Gap\n+ *\n+ *\n+ * Notes:\n+ * * Programming IFG1 and IFG2.\n+ *\n+ * For 10/100/1000Mbs half-duplex systems that require IEEE 802.3\n+ * compatibility, IFG1 must be in the range of 1-8, IFG2 must be in the range\n+ * of 4-12, and the IFG1+IFG2 sum must be 12.\n+ *\n+ * For 10/100/1000Mbs full-duplex systems that require IEEE 802.3\n+ * compatibility, IFG1 must be in the range of 1-11, IFG2 must be in the range\n+ * of 1-11, and the IFG1+IFG2 sum must be 12.\n+ *\n+ * For XAUI/10Gbs systems that require IEEE 802.3 compatibility, the\n+ * IFG1+IFG2 sum must be 12.  IFG1[1:0] and IFG2[1:0] must be zero.\n+ *\n+ * For all other systems, IFG1 and IFG2 can be any value in the range of\n+ * 1-15.  Allowing for a total possible IFG sum of 2-30.\n+ */\n+union cvmx_gmxx_tx_ifg {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_ifg_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 ifg2 : 4;\n+\t\tu64 ifg1 : 4;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_ifg_s cn30xx;\n+\tstruct cvmx_gmxx_tx_ifg_s cn31xx;\n+\tstruct cvmx_gmxx_tx_ifg_s cn38xx;\n+\tstruct cvmx_gmxx_tx_ifg_s cn38xxp2;\n+\tstruct cvmx_gmxx_tx_ifg_s cn50xx;\n+\tstruct cvmx_gmxx_tx_ifg_s cn52xx;\n+\tstruct cvmx_gmxx_tx_ifg_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_ifg_s cn56xx;\n+\tstruct cvmx_gmxx_tx_ifg_s cn56xxp1;\n+\tstruct cvmx_gmxx_tx_ifg_s cn58xx;\n+\tstruct cvmx_gmxx_tx_ifg_s cn58xxp1;\n+\tstruct cvmx_gmxx_tx_ifg_s cn61xx;\n+\tstruct cvmx_gmxx_tx_ifg_s cn63xx;\n+\tstruct cvmx_gmxx_tx_ifg_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_ifg_s cn66xx;\n+\tstruct cvmx_gmxx_tx_ifg_s cn68xx;\n+\tstruct cvmx_gmxx_tx_ifg_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_ifg_s cn70xx;\n+\tstruct cvmx_gmxx_tx_ifg_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_ifg_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_ifg cvmx_gmxx_tx_ifg_t;\n+\n+/**\n+ * cvmx_gmx#_tx_int_en\n+ *\n+ * GMX_TX_INT_EN = Interrupt Enable\n+ *\n+ *\n+ * Notes:\n+ * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.\n+ *\n+ */\n+union cvmx_gmxx_tx_int_en {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_int_en_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 xchange : 1;\n+\t\tu64 ptp_lost : 4;\n+\t\tu64 late_col : 4;\n+\t\tu64 xsdef : 4;\n+\t\tu64 xscol : 4;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 undflw : 4;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_int_en_cn30xx {\n+\t\tu64 reserved_19_63 : 45;\n+\t\tu64 late_col : 3;\n+\t\tu64 reserved_15_15 : 1;\n+\t\tu64 xsdef : 3;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 xscol : 3;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 undflw : 3;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_tx_int_en_cn31xx {\n+\t\tu64 reserved_15_63 : 49;\n+\t\tu64 xsdef : 3;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 xscol : 3;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 undflw : 3;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn31xx;\n+\tstruct cvmx_gmxx_tx_int_en_cn38xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 late_col : 4;\n+\t\tu64 xsdef : 4;\n+\t\tu64 xscol : 4;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 undflw : 4;\n+\t\tu64 ncb_nxa : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn38xx;\n+\tstruct cvmx_gmxx_tx_int_en_cn38xxp2 {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 xsdef : 4;\n+\t\tu64 xscol : 4;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 undflw : 4;\n+\t\tu64 ncb_nxa : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn38xxp2;\n+\tstruct cvmx_gmxx_tx_int_en_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_tx_int_en_cn52xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 late_col : 4;\n+\t\tu64 xsdef : 4;\n+\t\tu64 xscol : 4;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 undflw : 4;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn52xx;\n+\tstruct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1;\n+\tstruct cvmx_gmxx_tx_int_en_cn52xx cn56xx;\n+\tstruct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1;\n+\tstruct cvmx_gmxx_tx_int_en_cn38xx cn58xx;\n+\tstruct cvmx_gmxx_tx_int_en_cn38xx cn58xxp1;\n+\tstruct cvmx_gmxx_tx_int_en_s cn61xx;\n+\tstruct cvmx_gmxx_tx_int_en_cn63xx {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 ptp_lost : 4;\n+\t\tu64 late_col : 4;\n+\t\tu64 xsdef : 4;\n+\t\tu64 xscol : 4;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 undflw : 4;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn63xx;\n+\tstruct cvmx_gmxx_tx_int_en_cn63xx cn63xxp1;\n+\tstruct cvmx_gmxx_tx_int_en_s cn66xx;\n+\tstruct cvmx_gmxx_tx_int_en_cn68xx {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 xchange : 1;\n+\t\tu64 ptp_lost : 4;\n+\t\tu64 late_col : 4;\n+\t\tu64 xsdef : 4;\n+\t\tu64 xscol : 4;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 undflw : 4;\n+\t\tu64 pko_nxp : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn68xx;\n+\tstruct cvmx_gmxx_tx_int_en_cn68xx cn68xxp1;\n+\tstruct cvmx_gmxx_tx_int_en_s cn70xx;\n+\tstruct cvmx_gmxx_tx_int_en_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_int_en_cnf71xx {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 xchange : 1;\n+\t\tu64 reserved_22_23 : 2;\n+\t\tu64 ptp_lost : 2;\n+\t\tu64 reserved_18_19 : 2;\n+\t\tu64 late_col : 2;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 xsdef : 2;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tu64 xscol : 2;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 undflw : 2;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_int_en cvmx_gmxx_tx_int_en_t;\n+\n+/**\n+ * cvmx_gmx#_tx_int_reg\n+ *\n+ * GMX_TX_INT_REG = Interrupt Register\n+ *\n+ *\n+ * Notes:\n+ * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.\n+ *\n+ */\n+union cvmx_gmxx_tx_int_reg {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_int_reg_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 xchange : 1;\n+\t\tu64 ptp_lost : 4;\n+\t\tu64 late_col : 4;\n+\t\tu64 xsdef : 4;\n+\t\tu64 xscol : 4;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 undflw : 4;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_int_reg_cn30xx {\n+\t\tu64 reserved_19_63 : 45;\n+\t\tu64 late_col : 3;\n+\t\tu64 reserved_15_15 : 1;\n+\t\tu64 xsdef : 3;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 xscol : 3;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 undflw : 3;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_tx_int_reg_cn31xx {\n+\t\tu64 reserved_15_63 : 49;\n+\t\tu64 xsdef : 3;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 xscol : 3;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 undflw : 3;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn31xx;\n+\tstruct cvmx_gmxx_tx_int_reg_cn38xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 late_col : 4;\n+\t\tu64 xsdef : 4;\n+\t\tu64 xscol : 4;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 undflw : 4;\n+\t\tu64 ncb_nxa : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn38xx;\n+\tstruct cvmx_gmxx_tx_int_reg_cn38xxp2 {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 xsdef : 4;\n+\t\tu64 xscol : 4;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 undflw : 4;\n+\t\tu64 ncb_nxa : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn38xxp2;\n+\tstruct cvmx_gmxx_tx_int_reg_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_tx_int_reg_cn52xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 late_col : 4;\n+\t\tu64 xsdef : 4;\n+\t\tu64 xscol : 4;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 undflw : 4;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn52xx;\n+\tstruct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1;\n+\tstruct cvmx_gmxx_tx_int_reg_cn52xx cn56xx;\n+\tstruct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1;\n+\tstruct cvmx_gmxx_tx_int_reg_cn38xx cn58xx;\n+\tstruct cvmx_gmxx_tx_int_reg_cn38xx cn58xxp1;\n+\tstruct cvmx_gmxx_tx_int_reg_s cn61xx;\n+\tstruct cvmx_gmxx_tx_int_reg_cn63xx {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 ptp_lost : 4;\n+\t\tu64 late_col : 4;\n+\t\tu64 xsdef : 4;\n+\t\tu64 xscol : 4;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 undflw : 4;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn63xx;\n+\tstruct cvmx_gmxx_tx_int_reg_cn63xx cn63xxp1;\n+\tstruct cvmx_gmxx_tx_int_reg_s cn66xx;\n+\tstruct cvmx_gmxx_tx_int_reg_cn68xx {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 xchange : 1;\n+\t\tu64 ptp_lost : 4;\n+\t\tu64 late_col : 4;\n+\t\tu64 xsdef : 4;\n+\t\tu64 xscol : 4;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 undflw : 4;\n+\t\tu64 pko_nxp : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn68xx;\n+\tstruct cvmx_gmxx_tx_int_reg_cn68xx cn68xxp1;\n+\tstruct cvmx_gmxx_tx_int_reg_s cn70xx;\n+\tstruct cvmx_gmxx_tx_int_reg_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_int_reg_cnf71xx {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 xchange : 1;\n+\t\tu64 reserved_22_23 : 2;\n+\t\tu64 ptp_lost : 2;\n+\t\tu64 reserved_18_19 : 2;\n+\t\tu64 late_col : 2;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 xsdef : 2;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tu64 xscol : 2;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 undflw : 2;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_int_reg cvmx_gmxx_tx_int_reg_t;\n+\n+/**\n+ * cvmx_gmx#_tx_jam\n+ *\n+ * GMX_TX_JAM = Packet TX Jam Pattern\n+ *\n+ */\n+union cvmx_gmxx_tx_jam {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_jam_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 jam : 8;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_jam_s cn30xx;\n+\tstruct cvmx_gmxx_tx_jam_s cn31xx;\n+\tstruct cvmx_gmxx_tx_jam_s cn38xx;\n+\tstruct cvmx_gmxx_tx_jam_s cn38xxp2;\n+\tstruct cvmx_gmxx_tx_jam_s cn50xx;\n+\tstruct cvmx_gmxx_tx_jam_s cn52xx;\n+\tstruct cvmx_gmxx_tx_jam_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_jam_s cn56xx;\n+\tstruct cvmx_gmxx_tx_jam_s cn56xxp1;\n+\tstruct cvmx_gmxx_tx_jam_s cn58xx;\n+\tstruct cvmx_gmxx_tx_jam_s cn58xxp1;\n+\tstruct cvmx_gmxx_tx_jam_s cn61xx;\n+\tstruct cvmx_gmxx_tx_jam_s cn63xx;\n+\tstruct cvmx_gmxx_tx_jam_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_jam_s cn66xx;\n+\tstruct cvmx_gmxx_tx_jam_s cn68xx;\n+\tstruct cvmx_gmxx_tx_jam_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_jam_s cn70xx;\n+\tstruct cvmx_gmxx_tx_jam_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_jam_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_jam cvmx_gmxx_tx_jam_t;\n+\n+/**\n+ * cvmx_gmx#_tx_lfsr\n+ *\n+ * GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff\n+ *\n+ */\n+union cvmx_gmxx_tx_lfsr {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_lfsr_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 lfsr : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn30xx;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn31xx;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn38xx;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn38xxp2;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn50xx;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn52xx;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn56xx;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn56xxp1;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn58xx;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn58xxp1;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn61xx;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn63xx;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn66xx;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn68xx;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn70xx;\n+\tstruct cvmx_gmxx_tx_lfsr_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_lfsr_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_lfsr cvmx_gmxx_tx_lfsr_t;\n+\n+/**\n+ * cvmx_gmx#_tx_ovr_bp\n+ *\n+ * GMX_TX_OVR_BP = Packet Interface TX Override BackPressure\n+ *\n+ *\n+ * Notes:\n+ * In XAUI mode, only the lsb (corresponding to port0) of EN, BP, and IGN_FULL are used.\n+ *\n+ * GMX*_TX_OVR_BP[EN<0>] must be set to one and GMX*_TX_OVR_BP[BP<0>] must be cleared to zero\n+ * (to forcibly disable HW-automatic 802.3 pause packet generation) with the HiGig2 Protocol\n+ * when GMX*_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated by\n+ * GMX*_TX_XAUI_CTL[HG_EN]=1 and GMX*_RX0_UDD_SKP[LEN]=16.) HW can only auto-generate backpressure\n+ * through HiGig2 messages (optionally, when GMX*_HG2_CONTROL[HG2TX_EN]=1) with the HiGig2\n+ * protocol.\n+ */\n+union cvmx_gmxx_tx_ovr_bp {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 tx_prt_bp : 16;\n+\t\tu64 reserved_12_31 : 20;\n+\t\tu64 en : 4;\n+\t\tu64 bp : 4;\n+\t\tu64 ign_full : 4;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_ovr_bp_cn30xx {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 en : 3;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 bp : 3;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 ign_full : 3;\n+\t} cn30xx;\n+\tstruct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx;\n+\tstruct cvmx_gmxx_tx_ovr_bp_cn38xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 en : 4;\n+\t\tu64 bp : 4;\n+\t\tu64 ign_full : 4;\n+\t} cn38xx;\n+\tstruct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2;\n+\tstruct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s cn52xx;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s cn56xx;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s cn56xxp1;\n+\tstruct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx;\n+\tstruct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s cn61xx;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s cn63xx;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s cn66xx;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s cn68xx;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s cn70xx;\n+\tstruct cvmx_gmxx_tx_ovr_bp_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_ovr_bp_cnf71xx {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 tx_prt_bp : 16;\n+\t\tu64 reserved_10_31 : 22;\n+\t\tu64 en : 2;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 bp : 2;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 ign_full : 2;\n+\t} cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_ovr_bp cvmx_gmxx_tx_ovr_bp_t;\n+\n+/**\n+ * cvmx_gmx#_tx_pause_pkt_dmac\n+ *\n+ * GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field\n+ *\n+ */\n+union cvmx_gmxx_tx_pause_pkt_dmac {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 dmac : 48;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn61xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn66xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn70xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_pause_pkt_dmac_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_pause_pkt_dmac cvmx_gmxx_tx_pause_pkt_dmac_t;\n+\n+/**\n+ * cvmx_gmx#_tx_pause_pkt_type\n+ *\n+ * GMX_TX_PAUSE_PKT_TYPE = Packet Interface TX Pause Packet TYPE field\n+ *\n+ */\n+union cvmx_gmxx_tx_pause_pkt_type {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 type : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn30xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn31xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn38xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn50xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn52xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn56xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn61xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn63xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn66xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn68xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn70xx;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_pause_pkt_type_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_pause_pkt_type cvmx_gmxx_tx_pause_pkt_type_t;\n+\n+/**\n+ * cvmx_gmx#_tx_prts\n+ *\n+ * Common\n+ * GMX_TX_PRTS = TX Ports\n+ */\n+union cvmx_gmxx_tx_prts {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_prts_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 prts : 5;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_prts_s cn30xx;\n+\tstruct cvmx_gmxx_tx_prts_s cn31xx;\n+\tstruct cvmx_gmxx_tx_prts_s cn38xx;\n+\tstruct cvmx_gmxx_tx_prts_s cn38xxp2;\n+\tstruct cvmx_gmxx_tx_prts_s cn50xx;\n+\tstruct cvmx_gmxx_tx_prts_s cn52xx;\n+\tstruct cvmx_gmxx_tx_prts_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_prts_s cn56xx;\n+\tstruct cvmx_gmxx_tx_prts_s cn56xxp1;\n+\tstruct cvmx_gmxx_tx_prts_s cn58xx;\n+\tstruct cvmx_gmxx_tx_prts_s cn58xxp1;\n+\tstruct cvmx_gmxx_tx_prts_s cn61xx;\n+\tstruct cvmx_gmxx_tx_prts_s cn63xx;\n+\tstruct cvmx_gmxx_tx_prts_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_prts_s cn66xx;\n+\tstruct cvmx_gmxx_tx_prts_s cn68xx;\n+\tstruct cvmx_gmxx_tx_prts_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_prts_s cn70xx;\n+\tstruct cvmx_gmxx_tx_prts_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_prts_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_prts cvmx_gmxx_tx_prts_t;\n+\n+/**\n+ * cvmx_gmx#_tx_spi_ctl\n+ *\n+ * GMX_TX_SPI_CTL = Spi4 TX ModesSpi4\n+ *\n+ */\n+union cvmx_gmxx_tx_spi_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_spi_ctl_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 tpa_clr : 1;\n+\t\tu64 cont_pkt : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_spi_ctl_s cn38xx;\n+\tstruct cvmx_gmxx_tx_spi_ctl_s cn38xxp2;\n+\tstruct cvmx_gmxx_tx_spi_ctl_s cn58xx;\n+\tstruct cvmx_gmxx_tx_spi_ctl_s cn58xxp1;\n+};\n+\n+typedef union cvmx_gmxx_tx_spi_ctl cvmx_gmxx_tx_spi_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_tx_spi_drain\n+ *\n+ * GMX_TX_SPI_DRAIN = Drain out Spi TX FIFO\n+ *\n+ */\n+union cvmx_gmxx_tx_spi_drain {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_spi_drain_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 drain : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_spi_drain_s cn38xx;\n+\tstruct cvmx_gmxx_tx_spi_drain_s cn58xx;\n+\tstruct cvmx_gmxx_tx_spi_drain_s cn58xxp1;\n+};\n+\n+typedef union cvmx_gmxx_tx_spi_drain cvmx_gmxx_tx_spi_drain_t;\n+\n+/**\n+ * cvmx_gmx#_tx_spi_max\n+ *\n+ * GMX_TX_SPI_MAX = RGMII TX Spi4 MAX\n+ *\n+ */\n+union cvmx_gmxx_tx_spi_max {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_spi_max_s {\n+\t\tu64 reserved_23_63 : 41;\n+\t\tu64 slice : 7;\n+\t\tu64 max2 : 8;\n+\t\tu64 max1 : 8;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_spi_max_cn38xx {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 max2 : 8;\n+\t\tu64 max1 : 8;\n+\t} cn38xx;\n+\tstruct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2;\n+\tstruct cvmx_gmxx_tx_spi_max_s cn58xx;\n+\tstruct cvmx_gmxx_tx_spi_max_s cn58xxp1;\n+};\n+\n+typedef union cvmx_gmxx_tx_spi_max cvmx_gmxx_tx_spi_max_t;\n+\n+/**\n+ * cvmx_gmx#_tx_spi_round#\n+ *\n+ * GMX_TX_SPI_ROUND = Controls SPI4 TX Arbitration\n+ *\n+ */\n+union cvmx_gmxx_tx_spi_roundx {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_spi_roundx_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 round : 16;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_spi_roundx_s cn58xx;\n+\tstruct cvmx_gmxx_tx_spi_roundx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_gmxx_tx_spi_roundx cvmx_gmxx_tx_spi_roundx_t;\n+\n+/**\n+ * cvmx_gmx#_tx_spi_thresh\n+ *\n+ * GMX_TX_SPI_THRESH = RGMII TX Spi4 Transmit Threshold\n+ *\n+ *\n+ * Notes:\n+ * Note: zero will map to 0x20\n+ *\n+ * This will normally creates Spi4 traffic bursts at least THRESH in length.\n+ * If dclk > eclk, then this rule may not always hold and Octeon may split\n+ * transfers into smaller bursts - some of which could be as short as 16B.\n+ * Octeon will never violate the Spi4.2 spec and send a non-EOP burst that is\n+ * not a multiple of 16B.\n+ */\n+union cvmx_gmxx_tx_spi_thresh {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_spi_thresh_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 thresh : 6;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_spi_thresh_s cn38xx;\n+\tstruct cvmx_gmxx_tx_spi_thresh_s cn38xxp2;\n+\tstruct cvmx_gmxx_tx_spi_thresh_s cn58xx;\n+\tstruct cvmx_gmxx_tx_spi_thresh_s cn58xxp1;\n+};\n+\n+typedef union cvmx_gmxx_tx_spi_thresh cvmx_gmxx_tx_spi_thresh_t;\n+\n+/**\n+ * cvmx_gmx#_tx_xaui_ctl\n+ */\n+union cvmx_gmxx_tx_xaui_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 hg_pause_hgi : 2;\n+\t\tu64 hg_en : 1;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 ls_byp : 1;\n+\t\tu64 ls : 2;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 uni_en : 1;\n+\t\tu64 dic_en : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cn52xx;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cn56xx;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cn61xx;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cn63xx;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cn63xxp1;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cn66xx;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cn68xx;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cn68xxp1;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cn70xxp1;\n+\tstruct cvmx_gmxx_tx_xaui_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_tx_xaui_ctl cvmx_gmxx_tx_xaui_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_wol_ctl\n+ */\n+union cvmx_gmxx_wol_ctl {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_wol_ctl_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 magic_en : 4;\n+\t\tu64 reserved_20_31 : 12;\n+\t\tu64 direct_en : 4;\n+\t\tu64 reserved_1_15 : 15;\n+\t\tu64 en : 1;\n+\t} s;\n+\tstruct cvmx_gmxx_wol_ctl_s cn70xx;\n+\tstruct cvmx_gmxx_wol_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_gmxx_wol_ctl cvmx_gmxx_wol_ctl_t;\n+\n+/**\n+ * cvmx_gmx#_xaui_ext_loopback\n+ */\n+union cvmx_gmxx_xaui_ext_loopback {\n+\tu64 u64;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 en : 1;\n+\t\tu64 thresh : 4;\n+\t} s;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cn52xx;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cn56xx;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cn61xx;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cn63xx;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cn63xxp1;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cn66xx;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cn68xx;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cn68xxp1;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cn70xx;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cn70xxp1;\n+\tstruct cvmx_gmxx_xaui_ext_loopback_s cnf71xx;\n+};\n+\n+typedef union cvmx_gmxx_xaui_ext_loopback cvmx_gmxx_xaui_ext_loopback_t;\n+\n+#endif\n",
    "prefixes": [
        "v1",
        "11/50"
    ]
}