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GET /api/patches/1415040/?format=api
{ "id": 1415040, "url": "http://patchwork.ozlabs.org/api/patches/1415040/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-3-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-3-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:24", "name": "[v1,02/50] mips: octeon: Add misc cvmx-helper header files", "commit_ref": "a497c6594aa128774e0a3be8c5ef93a14455710b", "pull_url": null, "state": "accepted", "archived": false, "hash": "fd3fe229188aae74ad9957948ec6c9ea4f595b69", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-3-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1415040/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1415040/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=Plo/2cSj;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4CsxM90gBVz9sSn\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:39:17 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id D894B8266F;\n\tFri, 11 Dec 2020 17:38:21 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 19B82827A0; Fri, 11 Dec 2020 17:07:35 +0100 (CET)", "from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 6C1E882684\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:23 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org\n [IPv6:2001:67c:2050:105:465:1:1:0])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id 30E1EA0BBF;\n Fri, 11 Dec 2020 17:06:23 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter05.heinlein-hosting.de (spamfilter05.heinlein-hosting.de\n [80.241.56.123]) (amavisd-new, port 10030)\n with ESMTP id EC02z1dnfDKh; Fri, 11 Dec 2020 17:06:13 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607704702;\n\tbh=eWLeTXEA9lwwzZxtaZeoMmjsTiq7km0sy7k/539fGUg=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=Plo/2cSjl/Flfgb65LA0SCXlvrsUkwpNC3mpMDk0YzRL+eI+/SGbv6kJlmJ2esvaX\n\t dITAXd/m1iHygNKy7wDfV/JbXptQ2QhrtWVtM1BigJpeLIxXzexkSXupHSQen8Xhgd\n\t lKgpfazL3aSmGfcYCGYo6YlPjRpNaeB0SpeCtubfi28lMMlJW1rSECIHrhmQggms36\n\t NITrdxIT+yYUNlUUkpC8wKBZYe0FjLzslRlAOIO5qXOhaYCIBGxJsqaCbttbdYIPwu\n\t Q8CU3g7Lt7lwq37C5z+TYdOBlyCORWo0PLr7qLf0MIaoBrU082yHEtb1fEMJuuOWWv\n\t NZcPLiIzM2H5w==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 02/50] mips: octeon: Add misc cvmx-helper header files", "Date": "Fri, 11 Dec 2020 17:05:24 +0100", "Message-Id": "<20201211160612.1498780-3-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-4.76 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "0DD201878", "X-Rspamd-UID": "9b3c1b", "X-Mailman-Approved-At": "Fri, 11 Dec 2020 17:38:11 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport misc cvmx-helper header files from 2013 U-Boot. They will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../include/mach/cvmx-helper-agl.h | 68 ++\n .../include/mach/cvmx-helper-bgx.h | 335 +++++++\n .../include/mach/cvmx-helper-board.h | 558 +++++++++++\n .../include/mach/cvmx-helper-cfg.h | 884 ++++++++++++++++++\n .../include/mach/cvmx-helper-errata.h | 50 +\n .../include/mach/cvmx-helper-fdt.h | 568 +++++++++++\n .../include/mach/cvmx-helper-fpa.h | 43 +\n .../include/mach/cvmx-helper-gpio.h | 427 +++++++++\n .../include/mach/cvmx-helper-ilk.h | 93 ++\n .../include/mach/cvmx-helper-ipd.h | 16 +\n .../include/mach/cvmx-helper-jtag.h | 84 ++\n .../include/mach/cvmx-helper-loop.h | 37 +\n .../include/mach/cvmx-helper-npi.h | 42 +\n .../include/mach/cvmx-helper-pki.h | 319 +++++++\n .../include/mach/cvmx-helper-pko.h | 51 +\n .../include/mach/cvmx-helper-pko3.h | 76 ++\n .../include/mach/cvmx-helper-rgmii.h | 99 ++\n .../include/mach/cvmx-helper-sfp.h | 437 +++++++++\n .../include/mach/cvmx-helper-sgmii.h | 81 ++\n .../include/mach/cvmx-helper-spi.h | 73 ++\n .../include/mach/cvmx-helper-srio.h | 72 ++\n .../include/mach/cvmx-helper-util.h | 412 ++++++++\n .../include/mach/cvmx-helper-xaui.h | 108 +++\n .../mach-octeon/include/mach/cvmx-helper.h | 565 +++++++++++\n 24 files changed, 5498 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-agl.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-bgx.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-board.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-cfg.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-errata.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-fdt.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-fpa.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-gpio.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-ilk.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-ipd.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-jtag.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-loop.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-npi.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-pko.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-pko3.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-rgmii.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-sfp.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-sgmii.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-spi.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-srio.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-util.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper-xaui.h\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-helper.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-agl.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-agl.h\nnew file mode 100644\nindex 0000000000..7a5e4d89d3\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-agl.h\n@@ -0,0 +1,68 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Functions for AGL (RGMII) initialization, configuration,\n+ * and monitoring.\n+ */\n+\n+#ifndef __CVMX_HELPER_AGL_H__\n+#define __CVMX_HELPER_AGL_H__\n+\n+int __cvmx_helper_agl_enumerate(int interface);\n+\n+int cvmx_helper_agl_get_port(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Probe a RGMII interface and determine the number of ports\n+ * connected to it. The RGMII interface should still be down\n+ * after this call.\n+ *\n+ * @param interface Interface to probe\n+ *\n+ * @return Number of ports on the interface. Zero to disable.\n+ */\n+int __cvmx_helper_agl_probe(int interface);\n+\n+/**\n+ * @INTERNAL\n+ * Bringup and enable a RGMII interface. After this call packet\n+ * I/O should be fully functional. This is called with IPD\n+ * enabled but PKO disabled.\n+ *\n+ * @param interface Interface to bring up\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_agl_enable(int interface);\n+\n+/**\n+ * @INTERNAL\n+ * Return the link state of an IPD/PKO port as returned by\n+ * auto negotiation. The result of this function may not match\n+ * Octeon's link config if auto negotiation has changed since\n+ * the last call to cvmx_helper_link_set().\n+ *\n+ * @param ipd_port IPD/PKO port to query\n+ *\n+ * @return Link state\n+ */\n+cvmx_helper_link_info_t __cvmx_helper_agl_link_get(int ipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * Configure an IPD/PKO port for the specified link state. This\n+ * function does not influence auto negotiation at the PHY level.\n+ * The passed link state must always match the link state returned\n+ * by cvmx_helper_link_get(). It is normally best to use\n+ * cvmx_helper_link_autoconf() instead.\n+ *\n+ * @param ipd_port IPD/PKO port to configure\n+ * @param link_info The new link state\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_agl_link_set(int ipd_port, cvmx_helper_link_info_t link_info);\n+\n+#endif /* __CVMX_HELPER_AGL_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-bgx.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-bgx.h\nnew file mode 100644\nindex 0000000000..ead6193ec0\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-bgx.h\n@@ -0,0 +1,335 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Functions to configure the BGX MAC.\n+ */\n+\n+#ifndef __CVMX_HELPER_BGX_H__\n+#define __CVMX_HELPER_BGX_H__\n+\n+#define CVMX_BGX_RX_FIFO_SIZE (64 * 1024)\n+#define CVMX_BGX_TX_FIFO_SIZE (32 * 1024)\n+\n+int __cvmx_helper_bgx_enumerate(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Disable the BGX port\n+ *\n+ * @param xipd_port IPD port of the BGX interface to disable\n+ */\n+void cvmx_helper_bgx_disable(int xipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * Probe a SGMII interface and determine the number of ports\n+ * connected to it. The SGMII/XAUI interface should still be down after\n+ * this call. This is used by interfaces using the bgx mac.\n+ *\n+ * @param xiface Interface to probe\n+ *\n+ * @return Number of ports on the interface. Zero to disable.\n+ */\n+int __cvmx_helper_bgx_probe(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Bringup and enable a SGMII interface. After this call packet\n+ * I/O should be fully functional. This is called with IPD\n+ * enabled but PKO disabled. This is used by interfaces using the\n+ * bgx mac.\n+ *\n+ * @param xiface Interface to bring up\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_bgx_sgmii_enable(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Return the link state of an IPD/PKO port as returned by\n+ * auto negotiation. The result of this function may not match\n+ * Octeon's link config if auto negotiation has changed since\n+ * the last call to cvmx_helper_link_set(). This is used by\n+ * interfaces using the bgx mac.\n+ *\n+ * @param xipd_port IPD/PKO port to query\n+ *\n+ * @return Link state\n+ */\n+cvmx_helper_link_info_t __cvmx_helper_bgx_sgmii_link_get(int xipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * Configure an IPD/PKO port for the specified link state. This\n+ * function does not influence auto negotiation at the PHY level.\n+ * The passed link state must always match the link state returned\n+ * by cvmx_helper_link_get(). It is normally best to use\n+ * cvmx_helper_link_autoconf() instead. This is used by interfaces\n+ * using the bgx mac.\n+ *\n+ * @param xipd_port IPD/PKO port to configure\n+ * @param link_info The new link state\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_bgx_sgmii_link_set(int xipd_port, cvmx_helper_link_info_t link_info);\n+\n+/**\n+ * @INTERNAL\n+ * Configure a port for internal and/or external loopback. Internal loopback\n+ * causes packets sent by the port to be received by Octeon. External loopback\n+ * causes packets received from the wire to sent out again. This is used by\n+ * interfaces using the bgx mac.\n+ *\n+ * @param xipd_port IPD/PKO port to loopback.\n+ * @param enable_internal\n+ * Non zero if you want internal loopback\n+ * @param enable_external\n+ * Non zero if you want external loopback\n+ *\n+ * @return Zero on success, negative on failure.\n+ */\n+int __cvmx_helper_bgx_sgmii_configure_loopback(int xipd_port, int enable_internal,\n+\t\t\t\t\t int enable_external);\n+\n+/**\n+ * @INTERNAL\n+ * Bringup and enable a XAUI interface. After this call packet\n+ * I/O should be fully functional. This is called with IPD\n+ * enabled but PKO disabled. This is used by interfaces using the\n+ * bgx mac.\n+ *\n+ * @param xiface Interface to bring up\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_bgx_xaui_enable(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Return the link state of an IPD/PKO port as returned by\n+ * auto negotiation. The result of this function may not match\n+ * Octeon's link config if auto negotiation has changed since\n+ * the last call to cvmx_helper_link_set(). This is used by\n+ * interfaces using the bgx mac.\n+ *\n+ * @param xipd_port IPD/PKO port to query\n+ *\n+ * @return Link state\n+ */\n+cvmx_helper_link_info_t __cvmx_helper_bgx_xaui_link_get(int xipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * Configure an IPD/PKO port for the specified link state. This\n+ * function does not influence auto negotiation at the PHY level.\n+ * The passed link state must always match the link state returned\n+ * by cvmx_helper_link_get(). It is normally best to use\n+ * cvmx_helper_link_autoconf() instead. This is used by interfaces\n+ * using the bgx mac.\n+ *\n+ * @param xipd_port IPD/PKO port to configure\n+ * @param link_info The new link state\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_bgx_xaui_link_set(int xipd_port, cvmx_helper_link_info_t link_info);\n+\n+/**\n+ * @INTERNAL\n+ * Configure a port for internal and/or external loopback. Internal loopback\n+ * causes packets sent by the port to be received by Octeon. External loopback\n+ * causes packets received from the wire to sent out again. This is used by\n+ * interfaces using the bgx mac.\n+ *\n+ * @param xipd_port IPD/PKO port to loopback.\n+ * @param enable_internal\n+ * Non zero if you want internal loopback\n+ * @param enable_external\n+ * Non zero if you want external loopback\n+ *\n+ * @return Zero on success, negative on failure.\n+ */\n+int __cvmx_helper_bgx_xaui_configure_loopback(int xipd_port, int enable_internal,\n+\t\t\t\t\t int enable_external);\n+\n+int __cvmx_helper_bgx_mixed_enable(int xiface);\n+\n+cvmx_helper_link_info_t __cvmx_helper_bgx_mixed_link_get(int xipd_port);\n+\n+int __cvmx_helper_bgx_mixed_link_set(int xipd_port, cvmx_helper_link_info_t link_info);\n+\n+int __cvmx_helper_bgx_mixed_configure_loopback(int xipd_port, int enable_internal,\n+\t\t\t\t\t int enable_external);\n+\n+cvmx_helper_interface_mode_t cvmx_helper_bgx_get_mode(int xiface, int index);\n+\n+/**\n+ * @INTERNAL\n+ * Configure Priority-Based Flow Control (a.k.a. PFC/CBFC)\n+ * on a specific BGX interface/port.\n+ */\n+void __cvmx_helper_bgx_xaui_config_pfc(unsigned int node, unsigned int interface, unsigned int port,\n+\t\t\t\t bool pfc_enable);\n+\n+/**\n+ * This function control how the hardware handles incoming PAUSE\n+ * packets. The most common modes of operation:\n+ * ctl_bck = 1, ctl_drp = 1: hardware handles everything\n+ * ctl_bck = 0, ctl_drp = 0: software sees all PAUSE frames\n+ * ctl_bck = 0, ctl_drp = 1: all PAUSE frames are completely ignored\n+ * @param node\t\tnode number.\n+ * @param interface\tinterface number\n+ * @param port\t\tport number\n+ * @param ctl_bck\t1: Forward PAUSE information to TX block\n+ * @param ctl_drp\t1: Drop control PAUSE frames.\n+ */\n+void cvmx_helper_bgx_rx_pause_ctl(unsigned int node, unsigned int interface, unsigned int port,\n+\t\t\t\t unsigned int ctl_bck, unsigned int ctl_drp);\n+\n+/**\n+ * This function configures the receive action taken for multicast, broadcast\n+ * and dmac filter match packets.\n+ * @param node\t\tnode number.\n+ * @param interface\tinterface number\n+ * @param port\t\tport number\n+ * @param cam_accept\t0: reject packets on dmac filter match\n+ * 1: accept packet on dmac filter match\n+ * @param mcast_mode\t0x0 = Force reject all multicast packets\n+ * 0x1 = Force accept all multicast packets\n+ * 0x2 = Use the address filter CAM\n+ * @param bcast_accept 0 = Reject all broadcast packets\n+ * 1 = Accept all broadcast packets\n+ */\n+void cvmx_helper_bgx_rx_adr_ctl(unsigned int node, unsigned int interface, unsigned int port,\n+\t\t\t\tunsigned int cam_accept, unsigned int mcast_mode,\n+\t\t\t\tunsigned int bcast_accept);\n+\n+/**\n+ * Function to control the generation of FCS, padding by the BGX\n+ *\n+ */\n+void cvmx_helper_bgx_tx_options(unsigned int node, unsigned int interface, unsigned int index,\n+\t\t\t\tbool fcs_enable, bool pad_enable);\n+\n+/**\n+ * Set mac for the ipd_port\n+ *\n+ * @param xipd_port ipd_port to set the mac\n+ * @param bcst If set, accept all broadcast packets\n+ * @param mcst Multicast mode\n+ *\t\t 0 = Force reject all multicast packets\n+ *\t\t 1 = Force accept all multicast packets\n+ *\t\t 2 = use the address filter CAM.\n+ * @param mac mac address for the ipd_port\n+ */\n+void cvmx_helper_bgx_set_mac(int xipd_port, int bcst, int mcst, u64 mac);\n+\n+int __cvmx_helper_bgx_port_init(int xipd_port, int phy_pres);\n+void cvmx_helper_bgx_set_jabber(int xiface, unsigned int index, unsigned int size);\n+int cvmx_helper_bgx_shutdown_port(int xiface, int index);\n+int cvmx_bgx_set_backpressure_override(int xiface, unsigned int port_mask);\n+int __cvmx_helper_bgx_fifo_size(int xiface, unsigned int lmac);\n+\n+/**\n+ * Returns if an interface is RGMII or not\n+ *\n+ * @param xiface\txinterface to check\n+ * @param index\t\tport index (must be 0 for rgmii)\n+ *\n+ * @return\ttrue if RGMII, false otherwise\n+ */\n+static inline bool cvmx_helper_bgx_is_rgmii(int xiface, int index)\n+{\n+\tunion cvmx_bgxx_cmrx_config cmr_config;\n+\n+\tif (!OCTEON_IS_MODEL(OCTEON_CN73XX) || index != 0)\n+\t\treturn false;\n+\tcmr_config.u64 = csr_rd(CVMX_BGXX_CMRX_CONFIG(index, xiface));\n+\treturn cmr_config.s.lmac_type == 5;\n+}\n+\n+/**\n+ * Probes the BGX Super Path (SMU/SPU) mode\n+ *\n+ * @param xiface\tglobal interface number\n+ * @param index\t\tinterface index\n+ *\n+ * @return\ttrue, if Super-MAC/PCS mode, false -- otherwise\n+ */\n+bool cvmx_helper_bgx_is_smu(int xiface, int index);\n+\n+/**\n+ * @INTERNAL\n+ * Configure parameters of PAUSE packet.\n+ *\n+ * @param xipd_port\t\tGlobal IPD port (node + IPD port).\n+ * @param smac\t\t\tSource MAC address.\n+ * @param dmac\t\t\tDestination MAC address.\n+ * @param type\t\t\tPAUSE packet type.\n+ * @param time\t\t\tPause time for PAUSE packets (number of 512 bit-times).\n+ * @param interval\t\tInterval between PAUSE packets (number of 512 bit-times).\n+ * @return Zero on success, negative on failure.\n+ */\n+int cvmx_bgx_set_pause_pkt_param(int xipd_port, u64 smac, u64 dmac, unsigned int type,\n+\t\t\t\t unsigned int time, unsigned int interval);\n+\n+/**\n+ * @INTERNAL\n+ * Setup the BGX flow-control mode.\n+ *\n+ * @param xipd_port\t\tGlobal IPD port (node + IPD port).\n+ * @param type\t\t\tFlow-control type/protocol.\n+ * @param mode\t\t\tFlow-control mode.\n+ * @return Zero on success, negative on failure.\n+ */\n+int cvmx_bgx_set_flowctl_mode(int xipd_port, cvmx_qos_proto_t qos, cvmx_qos_pkt_mode_t mode);\n+\n+/**\n+ * Enables or disables autonegotiation for an interface.\n+ *\n+ * @param\txiface\tinterface to set autonegotiation\n+ * @param\tindex\tport index\n+ * @param\tenable\ttrue to enable autonegotiation, false to disable it\n+ *\n+ * @return\t0 for success, -1 on error.\n+ */\n+int cvmx_helper_set_autonegotiation(int xiface, int index, bool enable);\n+\n+/**\n+ * Enables or disables forward error correction\n+ *\n+ * @param\txiface\tinterface\n+ * @param\tindex\tport index\n+ * @param\tenable\tset to true to enable FEC, false to disable\n+ *\n+ * @return\t0 for success, -1 on error\n+ *\n+ * @NOTE:\tIf autonegotiation is enabled then autonegotiation will be\n+ *\t\trestarted for negotiating FEC.\n+ */\n+int cvmx_helper_set_fec(int xiface, int index, bool enable);\n+\n+#ifdef CVMX_DUMP_BGX\n+/**\n+ * Dump BGX configuration for node 0\n+ */\n+int cvmx_dump_bgx_config(unsigned int bgx);\n+/**\n+ * Dump BGX status for node 0\n+ */\n+int cvmx_dump_bgx_status(unsigned int bgx);\n+/**\n+ * Dump BGX configuration\n+ */\n+int cvmx_dump_bgx_config_node(unsigned int node, unsigned int bgx);\n+/**\n+ * Dump BGX status\n+ */\n+int cvmx_dump_bgx_status_node(unsigned int node, unsigned int bgx);\n+\n+#endif\n+\n+#endif\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-board.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-board.h\nnew file mode 100644\nindex 0000000000..d7a7b7d227\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-board.h\n@@ -0,0 +1,558 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Helper functions to abstract board specific data about\n+ * network ports from the rest of the cvmx-helper files.\n+ */\n+\n+#ifndef __CVMX_HELPER_BOARD_H__\n+#define __CVMX_HELPER_BOARD_H__\n+\n+#define CVMX_VSC7224_NAME_LEN 16\n+\n+typedef enum {\n+\tUSB_CLOCK_TYPE_REF_12,\n+\tUSB_CLOCK_TYPE_REF_24,\n+\tUSB_CLOCK_TYPE_REF_48,\n+\tUSB_CLOCK_TYPE_CRYSTAL_12,\n+} cvmx_helper_board_usb_clock_types_t;\n+\n+typedef enum cvmx_phy_type {\n+\tBROADCOM_GENERIC_PHY,\n+\tMARVELL_GENERIC_PHY,\n+\tCORTINA_PHY, /** Now Inphi */\n+\tAQUANTIA_PHY,\n+\tGENERIC_8023_C22_PHY,\n+\tGENERIC_8023_C45_PHY,\n+\tINBAND_PHY,\n+\tQUALCOMM_S17,\t /** Qualcomm QCA833X switch */\n+\tVITESSE_VSC8490_PHY, /** Vitesse VSC8490 is non-standard for SGMII */\n+\tFAKE_PHY,\t /** Unsupported or no PHY, use GPIOs for LEDs */\n+} cvmx_phy_type_t;\n+\n+/** Used to record the host mode used by the Cortina CS4321 PHY */\n+typedef enum {\n+\tCVMX_PHY_HOST_MODE_UNKNOWN,\n+\tCVMX_PHY_HOST_MODE_SGMII,\n+\tCVMX_PHY_HOST_MODE_QSGMII,\n+\tCVMX_PHY_HOST_MODE_XAUI,\n+\tCVMX_PHY_HOST_MODE_RXAUI,\n+} cvmx_phy_host_mode_t;\n+\n+typedef enum {\n+\tset_phy_link_flags_autoneg = 0x1,\n+\tset_phy_link_flags_flow_control_dont_touch = 0x0 << 1,\n+\tset_phy_link_flags_flow_control_enable = 0x1 << 1,\n+\tset_phy_link_flags_flow_control_disable = 0x2 << 1,\n+\tset_phy_link_flags_flow_control_mask = 0x3 << 1,\n+} cvmx_helper_board_set_phy_link_flags_types_t;\n+\n+/**\n+ * The EBB6600 board uses a MDIO mux device to select between the two QLM\n+ * modules since both QLM modules share the same PHY addresses. The\n+ * MDIO mux is controlled via GPIO by a GPIO device that is also on\n+ * the TWSI bus rather than native OCTEON GPIO libes.\n+ *\n+ * To further complicate matters, the TWSI GPIO device sits behind\n+ * a TWSI mux device as well, making accessing the MDIO devices on\n+ * this board a very complex operation involving writing to the TWSI mux,\n+ * followed by the MDIO mux device.\n+ */\n+/** Maximum number of GPIO devices used to control the MDIO mux */\n+#define CVMX_PHY_MUX_MAX_GPIO 2\n+\n+/** Type of MDIO mux device, currently OTHER isn't supported */\n+typedef enum {\n+\tSN74CBTLV3253, /** SN74CBTLV3253 I2C device */\n+\tOTHER\t /** Unknown/other */\n+} cvmx_phy_mux_type_t;\n+\n+/** Type of GPIO line controlling MDIO mux */\n+typedef enum {\n+\tGPIO_OCTEON, /** Native OCTEON */\n+\tGPIO_PCA8574 /** TWSI mux device */\n+} cvmx_phy_gpio_type_t;\n+\n+/* Forward declarations */\n+struct cvmx_fdt_sfp_info; /** Defined in cvmx-helper-fdt.h */\n+struct cvmx_vsc7224;\n+struct cvmx_fdt_gpio_info; /** Defined in cvmx-helper-fdt.h */\n+struct cvmx_fdt_i2c_bus_info; /** Defined in cvmx-helper-fdt.h */\n+struct cvmx_phy_info;\n+struct cvmx_fdt_i2c_bus_info;\n+struct cvmx_fdt_gpio_info;\n+struct cvmx_fdt_gpio_led;\n+\n+/**\n+ * @INTERNAL\n+ * This data structure is used when the port LEDs are wired up to Octeon's GPIO\n+ * lines instead of to a traditional PHY.\n+ */\n+struct cvmx_phy_gpio_leds {\n+\tstruct cvmx_phy_gpio_leds *next; /** For when ports are grouped together */\n+\tu64 last_rx_count;\t\t /** Counters used to check for activity */\n+\tu64 last_tx_count;\t\t /** Counters used to check for activity */\n+\tu64 last_activity_poll_time;\t /** Last time activity was polled */\n+\tu64 last_link_poll_time;\t /** Last time link was polled */\n+\tint of_offset;\n+\tint link_poll_interval_ms; /** Link polling interval in ms */\n+\tint activity_poll_interval_ms; /** Activity polling interval in ms */\n+\tstruct cvmx_fdt_gpio_led *link_status;\n+\tstruct cvmx_fdt_gpio_led *error;\n+\tstruct cvmx_fdt_gpio_led *rx_activity;\n+\tstruct cvmx_fdt_gpio_led *tx_activity;\n+\tstruct cvmx_fdt_gpio_led *identify;\n+\n+\tstruct cvmx_fdt_gpio_info *link_status_gpio;\n+\tstruct cvmx_fdt_gpio_info *error_gpio;\n+\t/** Type of GPIO for error LED */\n+\t/** If GPIO expander, describe the bus to the expander */\n+\tstruct cvmx_fdt_gpio_info *rx_activity_gpio;\n+\tstruct cvmx_fdt_gpio_info *tx_activity_gpio;\n+\n+\tu16 rx_activity_hz; /** RX activity blink time in hz */\n+\tu16 tx_activity_hz; /** TX activity blink time in hz */\n+\t/**\n+\t * Set if activity and/or link is using an Inphi/Cortina CS4343 or\n+\t * compatible phy that requires software assistance. NULL if not used.\n+\t */\n+\tbool link_status_active_low; /** True if active link is active low */\n+\tbool error_status_active_low; /** True if error LED is active low */\n+\tbool error_active_low;\t /** True if error is active low */\n+\tbool rx_activity_active_low; /** True if rx activity is active low */\n+\tbool tx_activity_active_low; /** True if tx activity is active low */\n+\t/** Set true if LEDs are shared on an interface by all ports */\n+\tbool interface_leds;\n+\tint8_t rx_gpio_timer; /** GPIO clock generator timer [0-3] */\n+\tint8_t tx_gpio_timer; /** GPIO clock generator timer [0-3] */\n+\n+\t/** True if LOS signal activates error LED */\n+\tbool los_generate_error;\n+\t/** True if the error LED is hooked up to a GPIO expander */\n+\tbool error_gpio_expander;\n+\t/** True if the link and RX activity LEDs are shared */\n+\tbool link_and_rx_activity_shared;\n+\t/** True if the link and TX activity LEDs are shared */\n+\tbool link_and_tx_activity_shared;\n+\t/** True if the RX activity and TX activity LEDs are shared */\n+\tbool rx_and_tx_activity_shared;\n+\t/** True if link is driven directly by the hardware */\n+\tbool link_led_hw_link;\n+\tbool error_lit;\t /** True if ERROR LED is lit */\n+\tbool quad_sfp_mode; /** True if using four SFPs for XLAUI */\n+\t/** User-defined function to update the link LED */\n+\tvoid (*update_link_led)(int xiface, int index, cvmx_helper_link_info_t result);\n+\t/** User-defined function to update the rx activity LED */\n+\tvoid (*update_rx_activity_led)(struct cvmx_phy_gpio_leds *led, int xiface, int index,\n+\t\t\t\t bool check_time);\n+};\n+\n+/** This structure contains the tap values to use for various cable lengths */\n+struct cvmx_vsc7224_tap {\n+\tu16 len; /** Starting cable length for tap values */\n+\tu16 main_tap; /** Main tap value to use */\n+\tu16 pre_tap; /** Pre-tap value to use */\n+\tu16 post_tap; /** Post-tap value to use */\n+};\n+\n+/** Data structure for Microsemi VSC7224 channel */\n+struct cvmx_vsc7224_chan {\n+\tstruct cvmx_vsc7224_chan *next, *prev; /** Used for linking */\n+\tint ipd_port;\t\t\t /** IPD port this channel belongs to */\n+\tint xiface;\t\t\t /** xinterface of SFP */\n+\tint index;\t\t\t /** Port index of SFP */\n+\tint lane;\t\t\t /** Lane on port */\n+\tint of_offset;\t\t\t /** Offset of channel info in dt */\n+\tbool is_tx;\t\t\t /** True if is transmit channel */\n+\tbool maintap_disable;\t\t /** True to disable the main tap */\n+\tbool pretap_disable;\t\t /** True to disable pre-tap */\n+\tbool posttap_disable;\t\t /** True to disable post-tap */\n+\tint num_taps;\t\t\t /** Number of tap values */\n+\t/** (Q)SFP attached to this channel */\n+\tstruct cvmx_fdt_sfp_info *sfp_info;\n+\tstruct cvmx_vsc7224 *vsc7224; /** Pointer to parent */\n+\t/** Tap values for various lengths, must be at the end */\n+\tstruct cvmx_vsc7224_tap taps[0];\n+};\n+\n+/** Data structure for Microsemi VSC7224 reclocking chip */\n+struct cvmx_vsc7224 {\n+\tconst char *name; /** Name */\n+\t/** Pointer to cannel data */\n+\tstruct cvmx_vsc7224_chan *channel[4];\n+\t/** I2C bus device is connected to */\n+\tstruct cvmx_fdt_i2c_bus_info *i2c_bus;\n+\t/** Address of VSC7224 on i2c bus */\n+\tint i2c_addr;\n+\tstruct cvmx_fdt_gpio_info *los_gpio; /** LoS GPIO pin */\n+\tstruct cvmx_fdt_gpio_info *reset_gpio; /** Reset GPIO pin */\n+\tint of_offset;\t\t\t /** Offset in device tree */\n+};\n+\n+/** Data structure for Avago AVSP5410 gearbox phy */\n+struct cvmx_avsp5410 {\n+\tconst char *name; /** Name */\n+\t/** I2C bus device is connected to */\n+\tstruct cvmx_fdt_i2c_bus_info *i2c_bus;\n+\t/** Address of AVSP5410 on i2c bus */\n+\tint i2c_addr;\n+\tint of_offset;\t /** Offset in device tree */\n+\tint ipd_port;\t /** IPD port this phy belongs to */\n+\tint xiface;\t /** xinterface of SFP */\n+\tint index;\t /** Port index of SFP */\n+\tu64 prev_temp;\t /** Previous temparature recorded on Phy Core */\n+\tu64 prev_temp_mins; /** Mininutes when the prev temp check is done */\n+\t/** (Q)SFP attached to this phy */\n+\tstruct cvmx_fdt_sfp_info *sfp_info;\n+};\n+\n+struct cvmx_cs4343_info;\n+\n+/**\n+ * @INTERNAL\n+ *\n+ * Data structure containing Inphi CS4343 slice information\n+ */\n+struct cvmx_cs4343_slice_info {\n+\tconst char *name;\t /** Name of this slice in device tree */\n+\tstruct cvmx_cs4343_info *mphy; /** Pointer to mphy cs4343 */\n+\tstruct cvmx_phy_info *phy_info;\n+\tint of_offset;\t\t /** Offset in device tree */\n+\tint slice_no;\t\t /** Slice number */\n+\tint reg_offset;\t\t /** Offset for this slice */\n+\tu16 sr_stx_cmode_res;\t /** See Rainier device tree */\n+\tu16 sr_stx_drv_lower_cm; /** See Rainier device tree */\n+\tu16 sr_stx_level;\t /** See Rainier device tree */\n+\tu16 sr_stx_pre_peak;\t /** See Rainier device tree */\n+\tu16 sr_stx_muxsubrate_sel; /** See Rainier device tree */\n+\tu16 sr_stx_post_peak;\t /** See Rainier device tree */\n+\tu16 cx_stx_cmode_res;\t /** See Rainier device tree */\n+\tu16 cx_stx_drv_lower_cm; /** See Rainier device tree */\n+\tu16 cx_stx_level;\t /** See Rainier device tree */\n+\tu16 cx_stx_pre_peak;\t /** See Rainier device tree */\n+\tu16 cx_stx_muxsubrate_sel; /** See Rainier device tree */\n+\tu16 cx_stx_post_peak;\t /** See Rainier device tree */\n+\tu16 basex_stx_cmode_res; /** See Rainier device tree */\n+\tu16 basex_stx_drv_lower_cm; /** See Rainier device tree */\n+\tu16 basex_stx_level;\t /** See Rainier device tree */\n+\tu16 basex_stx_pre_peak;\t /** See Rainier device tree */\n+\tu16 basex_stx_muxsubrate_sel; /** See Rainier device tree */\n+\tu16 basex_stx_post_peak; /** See Rainier device tree */\n+\tint link_gpio;\t\t /** Link LED gpio pin number, -1 if none */\n+\tint error_gpio;\t\t /** Error LED GPIO pin or -1 if none */\n+\tint los_gpio;\t\t /** LoS input GPIO or -1 if none */\n+\tbool los_inverted;\t /** True if LoS input is inverted */\n+\tbool link_inverted;\t /** True if link output is inverted */\n+\tbool error_inverted;\t /** True if error output is inverted */\n+};\n+\n+/**\n+ * @INTERNAL\n+ *\n+ * Data structure for Cortina/Inphi CS4343 device\n+ */\n+struct cvmx_cs4343_info {\n+\tconst char *name; /** Name of Inphi/Cortina CS4343 in DT */\n+\tstruct cvmx_phy_info *phy_info;\n+\tstruct cvmx_cs4343_slice_info slice[4]; /** Slice information */\n+\tint of_offset;\n+};\n+\n+/**\n+ * @INTERNAL\n+ * This data structure is used to hold PHY information and is subject to change.\n+ * Please do not use this data structure directly.\n+ *\n+ * NOTE: The U-Boot OCTEON Ethernet drivers depends on this data structure for\n+ * the mux support.\n+ */\n+typedef struct cvmx_phy_info {\n+\tint phy_addr;\t /** MDIO address of PHY */\n+\tint phy_sub_addr; /** Sub-address (i.e. slice), used by Cortina */\n+\tint ipd_port;\t /** IPD port number for the PHY */\n+\t/** MDIO bus PHY connected to (even if behind mux) */\n+\tint mdio_unit;\n+\tint direct_connect;\t\t /** 1 if PHY is directly connected */\n+\tint gpio[CVMX_PHY_MUX_MAX_GPIO]; /** GPIOs used to control mux, -1 if not used */\n+\n+\t/** Type of GPIO. It can be a local OCTEON GPIO or a TWSI GPIO */\n+\tcvmx_phy_gpio_type_t gpio_type[CVMX_PHY_MUX_MAX_GPIO];\n+\n+\t/** Address of TWSI GPIO */\n+\tint cvmx_gpio_twsi[CVMX_PHY_MUX_MAX_GPIO];\n+\n+\t/** Value to put into the GPIO lines to select MDIO bus */\n+\tint gpio_value;\n+\tint gpio_parent_mux_twsi;\t/** -1 if not used, parent TWSI mux for ebb6600 */\n+\tint gpio_parent_mux_select;\t/** selector to use on parent TWSI mux */\n+\tcvmx_phy_type_t phy_type;\t/** Type of PHY */\n+\tcvmx_phy_mux_type_t mux_type;\t/** Type of MDIO mux */\n+\tint mux_twsi_addr;\t\t/** Address of the MDIO mux */\n+\tcvmx_phy_host_mode_t host_mode; /** Used by Cortina PHY */\n+\tvoid *phydev;\t\t\t/** Pointer to parent phy device */\n+\tint fdt_offset;\t\t\t/** Node in flat device tree */\n+\tint phy_i2c_bus;\t\t/** I2C bus for reclocking chips */\n+\tint phy_i2c_addr;\t\t/** I2C address of reclocking chip */\n+\tint num_vsc7224;\t\t/** Number of Microsemi VSC7224 devices */\n+\tstruct cvmx_vsc7224 *vsc7224;\t/** Info for VSC7224 devices */\n+\t/** SFP/QSFP descriptor */\n+\tstruct cvmx_fdt_sfp_info *sfp_info;\n+\t/** CS4343 slice information for SGMII/XFI. This is NULL in XLAUI mode */\n+\tstruct cvmx_cs4343_slice_info *cs4343_slice_info;\n+\t/** CS4343 mphy information for XLAUI */\n+\tstruct cvmx_cs4343_info *cs4343_info;\n+\t/** Pointer to function to return link information */\n+\tcvmx_helper_link_info_t (*link_function)(struct cvmx_phy_info *phy_info);\n+\t/**\n+\t * If there are LEDs driven by GPIO lines instead of by a PHY device\n+\t * then they are described here, otherwise gpio_leds should be NULL.\n+\t */\n+\tstruct cvmx_phy_gpio_leds *gpio_leds;\n+} cvmx_phy_info_t;\n+\n+/* Fake IPD port, the RGMII/MII interface may use different PHY, use this\n+ macro to return appropriate MIX address to read the PHY. */\n+#define CVMX_HELPER_BOARD_MGMT_IPD_PORT -10\n+\n+/**\n+ * Return the MII PHY address associated with the given IPD\n+ * port. A result of -1 means there isn't a MII capable PHY\n+ * connected to this port. On chips supporting multiple MII\n+ * busses the bus number is encoded in bits <15:8>.\n+ *\n+ * This function must be modified for every new Octeon board.\n+ * Internally it uses switch statements based on the cvmx_sysinfo\n+ * data to determine board types and revisions. It relies on the\n+ * fact that every Octeon board receives a unique board type\n+ * enumeration from the bootloader.\n+ *\n+ * @param ipd_port Octeon IPD port to get the MII address for.\n+ *\n+ * @return MII PHY address and bus number or -1.\n+ */\n+int cvmx_helper_board_get_mii_address(int ipd_port);\n+\n+/**\n+ * This function as a board specific method of changing the PHY\n+ * speed, duplex, and autonegotiation. This programs the PHY and\n+ * not Octeon. This can be used to force Octeon's links to\n+ * specific settings.\n+ *\n+ * @param phy_addr The address of the PHY to program\n+ * @param link_flags\n+ * Flags to control autonegotiation. Bit 0 is autonegotiation\n+ * enable/disable to maintain backward compatibility.\n+ * @param link_info Link speed to program. If the speed is zero and autonegotiation\n+ * is enabled, all possible negotiation speeds are advertised.\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int cvmx_helper_board_link_set_phy(int phy_addr,\n+\t\t\t\t cvmx_helper_board_set_phy_link_flags_types_t link_flags,\n+\t\t\t\t cvmx_helper_link_info_t link_info);\n+\n+/**\n+ * @INTERNAL\n+ * This function is the board specific method of determining an\n+ * ethernet ports link speed. Most Octeon boards have Marvell PHYs\n+ * and are handled by the fall through case. This function must be\n+ * updated for boards that don't have the normal Marvell PHYs.\n+ *\n+ * This function must be modified for every new Octeon board.\n+ * Internally it uses switch statements based on the cvmx_sysinfo\n+ * data to determine board types and revisions. It relies on the\n+ * fact that every Octeon board receives a unique board type\n+ * enumeration from the bootloader.\n+ *\n+ * @param ipd_port IPD input port associated with the port we want to get link\n+ * status for.\n+ *\n+ * @return The ports link status. If the link isn't fully resolved, this must\n+ * return zero.\n+ */\n+cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * This function is called by cvmx_helper_interface_probe() after it\n+ * determines the number of ports Octeon can support on a specific\n+ * interface. This function is the per board location to override\n+ * this value. It is called with the number of ports Octeon might\n+ * support and should return the number of actual ports on the\n+ * board.\n+ *\n+ * This function must be modified for every new Octeon board.\n+ * Internally it uses switch statements based on the cvmx_sysinfo\n+ * data to determine board types and revisions. It relies on the\n+ * fact that every Octeon board receives a unique board type\n+ * enumeration from the bootloader.\n+ *\n+ * @param interface Interface to probe\n+ * @param supported_ports\n+ * Number of ports Octeon supports.\n+ *\n+ * @return Number of ports the actual board supports. Many times this will\n+ * simple be \"support_ports\".\n+ */\n+int __cvmx_helper_board_interface_probe(int interface, int supported_ports);\n+\n+/**\n+ * @INTERNAL\n+ * Enable packet input/output from the hardware. This function is\n+ * called after by cvmx_helper_packet_hardware_enable() to\n+ * perform board specific initialization. For most boards\n+ * nothing is needed.\n+ *\n+ * @param interface Interface to enable\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_board_hardware_enable(int interface);\n+\n+/**\n+ * @INTERNAL\n+ * Gets the clock type used for the USB block based on board type.\n+ * Used by the USB code for auto configuration of clock type.\n+ *\n+ * @return USB clock type enumeration\n+ */\n+cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void);\n+\n+/**\n+ * @INTERNAL\n+ * Adjusts the number of available USB ports on Octeon based on board\n+ * specifics.\n+ *\n+ * @param supported_ports expected number of ports based on chip type;\n+ *\n+ *\n+ * @return number of available usb ports, based on board specifics.\n+ * Return value is supported_ports if function does not\n+ * override.\n+ */\n+int __cvmx_helper_board_usb_get_num_ports(int supported_ports);\n+\n+/**\n+ * @INTERNAL\n+ * Returns if a port is present on an interface\n+ *\n+ * @param fdt_addr - address fo flat device tree\n+ * @param ipd_port - IPD port number\n+ *\n+ * @return 1 if port is present, 0 if not present, -1 if error\n+ */\n+int __cvmx_helper_board_get_port_from_dt(void *fdt_addr, int ipd_port);\n+\n+/**\n+ * Return the host mode for the PHY. Currently only the Cortina CS4321 PHY\n+ * needs this.\n+ *\n+ * @param ipd_port - ipd port number to get the host mode for\n+ *\n+ * @return host mode for phy\n+ */\n+cvmx_phy_host_mode_t cvmx_helper_board_get_phy_host_mode(int ipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * This function outputs the cvmx_phy_info_t data structure for the specified\n+ * port.\n+ *\n+ * @param[out] - phy_info - phy info data structure\n+ * @param ipd_port - port to get phy info for\n+ *\n+ * @return 0 for success, -1 if info not available\n+ *\n+ * NOTE: The phy_info data structure is subject to change.\n+ */\n+int cvmx_helper_board_get_phy_info(cvmx_phy_info_t *phy_info, int ipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * Parse the device tree and set whether a port is valid or not.\n+ *\n+ * @param fdt_addr\tPointer to device tree\n+ *\n+ * @return 0 for success, -1 on error.\n+ */\n+int __cvmx_helper_parse_bgx_dt(const void *fdt_addr);\n+\n+/**\n+ * @INTERNAL\n+ * Parse the device tree and set whether a port is valid or not.\n+ *\n+ * @param fdt_addr\tPointer to device tree\n+ *\n+ * @return 0 for success, -1 on error.\n+ */\n+int __cvmx_helper_parse_bgx_rgmii_dt(const void *fdt_addr);\n+\n+/**\n+ * @INTERNAL\n+ * Updates any GPIO link LEDs if present\n+ *\n+ * @param xiface\tInterface number\n+ * @param index\t\tPort index\n+ * @param result\tLink status result\n+ */\n+void cvmx_helper_update_link_led(int xiface, int index, cvmx_helper_link_info_t result);\n+/**\n+ * Update the RX activity LED for the specified interface and port index\n+ *\n+ * @param xiface\tInterface number\n+ * @param index\t\tPort index\n+ * @parma check_time\tTrue if we should bail out before the polling interval\n+ */\n+void cvmx_update_rx_activity_led(int xiface, int index, bool check_time);\n+\n+/**\n+ * @INTERNAL\n+ * Figure out which mod_abs changed function to use based on the phy type\n+ *\n+ * @param\txiface\txinterface number\n+ * @param\tindex\tport index on interface\n+ *\n+ * @return\t0 for success, -1 on error\n+ *\n+ * This function figures out the proper mod_abs_changed function to use and\n+ * registers the appropriate function. This should be called after the device\n+ * tree has been fully parsed for the given port as well as after all SFP\n+ * slots and any Microsemi VSC7224 devices have been parsed in the device tree.\n+ */\n+int cvmx_helper_phy_register_mod_abs_changed(int xiface, int index);\n+\n+/**\n+ * @INTERNAL\n+ * Return loss of signal\n+ *\n+ * @param\txiface\txinterface number\n+ * @param\tindex\tport index on interface\n+ *\n+ * @return\t0 if signal present, 1 if loss of signal.\n+ *\n+ * @NOTE:\tA result of 0 is possible in some cases where the signal is\n+ *\t\tnot present.\n+ *\n+ * This is for use with __cvmx_qlm_rx_equilization\n+ */\n+int __cvmx_helper_get_los(int xiface, int index);\n+\n+/**\n+ * Given the address of the MDIO registers, output the CPU node and MDIO bus\n+ *\n+ * @param\taddr\t64-bit address of MDIO registers (from device tree)\n+ * @param[out]\tnode\tCPU node number (78xx)\n+ * @param[out]\tbus\tMDIO bus number\n+ */\n+void __cvmx_mdio_addr_to_node_bus(u64 addr, int *node, int *bus);\n+\n+/**\n+ * Turn on the error LED\n+ *\n+ * @param\tleds\tLEDs belonging to port\n+ * @param\terror\ttrue to turn on LED, false to turn off\n+ */\n+void cvmx_helper_leds_show_error(struct cvmx_phy_gpio_leds *leds, bool error);\n+\n+#endif /* __CVMX_HELPER_BOARD_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-cfg.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-cfg.h\nnew file mode 100644\nindex 0000000000..d4bd910b01\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-cfg.h\n@@ -0,0 +1,884 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Helper Functions for the Configuration Framework\n+ *\n+ * OCTEON_CN68XX introduces a flexible hw interface configuration\n+ * scheme. To cope with this change and the requirements of\n+ * configurability for other system resources, e.g., IPD/PIP pknd and\n+ * PKO ports and queues, a configuration framework for the SDK is\n+ * designed. It has two goals: first to recognize and establish the\n+ * default configuration and, second, to allow the user to define key\n+ * parameters in a high-level language.\n+ *\n+ * The helper functions query the QLM setup to help achieving the\n+ * first goal.\n+ *\n+ * The second goal is accomplished by generating\n+ * cvmx_helper_cfg_init() from a high-level lanaguage.\n+ */\n+\n+#ifndef __CVMX_HELPER_CFG_H__\n+#define __CVMX_HELPER_CFG_H__\n+\n+#include \"cvmx-helper-util.h\"\n+\n+#define CVMX_HELPER_CFG_MAX_PKO_PORT\t 128\n+#define CVMX_HELPER_CFG_MAX_PIP_BPID\t 64\n+#define CVMX_HELPER_CFG_MAX_PIP_PKND\t 64\n+#define CVMX_HELPER_CFG_MAX_PKO_QUEUES\t 256\n+#define CVMX_HELPER_CFG_MAX_PORT_PER_IFACE 256\n+\n+#define CVMX_HELPER_CFG_INVALID_VALUE -1\n+\n+#define cvmx_helper_cfg_assert(cond) \\\n+\tdo { \\\n+\t\tif (!(cond)) { \\\n+\t\t\tdebug(\"cvmx_helper_cfg_assert (%s) at %s:%d\\n\", #cond, __FILE__, \\\n+\t\t\t __LINE__); \\\n+\t\t} \\\n+\t} while (0)\n+\n+extern int cvmx_npi_max_pknds;\n+\n+/*\n+ * Config Options\n+ *\n+ * These options have to be set via cvmx_helper_cfg_opt_set() before calling the\n+ * routines that set up the hw. These routines process the options and set them\n+ * correctly to take effect at runtime.\n+ */\n+enum cvmx_helper_cfg_option {\n+\tCVMX_HELPER_CFG_OPT_USE_DWB, /*\n+\t\t\t\t\t * Global option to control if\n+\t\t\t\t\t * the SDK configures units (DMA,\n+\t\t\t\t\t * SSO, and PKO) to send don't\n+\t\t\t\t\t * write back (DWB) requests for\n+\t\t\t\t\t * freed buffers. Set to 1/0 to\n+\t\t\t\t\t * enable/disable DWB.\n+\t\t\t\t\t *\n+\t\t\t\t\t * For programs that fit inside\n+\t\t\t\t\t * L2, sending DWB just causes\n+\t\t\t\t\t * more L2 operations without\n+\t\t\t\t\t * benefit.\n+\t\t\t\t\t */\n+\n+\tCVMX_HELPER_CFG_OPT_MAX\n+};\n+\n+typedef enum cvmx_helper_cfg_option cvmx_helper_cfg_option_t;\n+\n+struct cvmx_phy_info;\n+struct cvmx_fdt_sfp_info;\n+struct cvmx_vsc7224_chan;\n+struct phy_device;\n+\n+struct cvmx_srio_port_param {\n+\t/** True to override SRIO CTLE zero setting */\n+\tbool srio_rx_ctle_zero_override : 1;\n+\t/** Equalization peaking control dft: 6 */\n+\tu8 srio_rx_ctle_zero : 4;\n+\t/** Set true to override CTLE taps */\n+\tbool srio_rx_ctle_agc_override : 1;\n+\tu8 srio_rx_agc_pre_ctle : 4;\t /** AGC pre-CTLE gain */\n+\tu8 srio_rx_agc_post_ctle : 4;\t /** AGC post-CTLE gain */\n+\tbool srio_tx_swing_override : 1; /** True to override TX Swing */\n+\tu8 srio_tx_swing : 5;\t\t /** TX Swing */\n+\tbool srio_tx_gain_override : 1;\t /** True to override TX gain */\n+\tu8 srio_tx_gain : 3;\t\t /** TX gain */\n+\tbool srio_tx_premptap_override : 1; /** True to override premptap values */\n+\tu8 srio_tx_premptap_pre : 4;\t /** Pre premptap value */\n+\tu8 srio_tx_premptap_post : 5;\t /** Post premptap value */\n+\tbool srio_tx_vboost_override : 1; /** True to override TX vboost setting */\n+\tbool srio_tx_vboost : 1;\t /** vboost setting (default 1) */\n+};\n+\n+/*\n+ * Per physical port\n+ * Note: This struct is passed between linux and SE apps.\n+ */\n+struct cvmx_cfg_port_param {\n+\tint port_fdt_node;\t\t/** Node offset in FDT of node */\n+\tint phy_fdt_node;\t\t/** Node offset in FDT of PHY */\n+\tstruct cvmx_phy_info *phy_info; /** Data structure with PHY information */\n+\tint8_t ccpp_pknd;\n+\tint8_t ccpp_bpid;\n+\tint8_t ccpp_pko_port_base;\n+\tint8_t ccpp_pko_num_ports;\n+\tu8 agl_rx_clk_skew;\t\t /** AGL rx clock skew setting (default 0) */\n+\tu8 rgmii_tx_clk_delay;\t\t /** RGMII TX clock delay value if not bypassed */\n+\tbool valid : 1;\t\t\t /** 1 = port valid, 0 = invalid */\n+\tbool sgmii_phy_mode : 1;\t /** 1 = port in PHY mode, 0 = MAC mode */\n+\tbool sgmii_1000x_mode : 1;\t /** 1 = 1000Base-X mode, 0 = SGMII mode */\n+\tbool agl_rx_clk_delay_bypass : 1; /** 1 = use rx clock delay bypass for AGL mode */\n+\tbool force_link_up : 1;\t\t /** Ignore PHY and always report link up */\n+\tbool disable_an : 1;\t\t /** true to disable autonegotiation */\n+\tbool link_down_pwr_dn : 1;\t /** Power PCS off when link is down */\n+\tbool phy_present : 1;\t\t /** true if PHY is present */\n+\tbool tx_clk_delay_bypass : 1;\t /** True to bypass the TX clock delay */\n+\tbool enable_fec : 1;\t\t /** True to enable FEC for 10/40G links */\n+\t/** Settings for short-run SRIO host */\n+\tstruct cvmx_srio_port_param srio_short;\n+\t/** Settings for long-run SRIO host */\n+\tstruct cvmx_srio_port_param srio_long;\n+\tu8 agl_refclk_sel; /** RGMII refclk select to use */\n+\t/** Set if local (non-PHY) LEDs are used */\n+\tstruct cvmx_phy_gpio_leds *gpio_leds;\n+\tstruct cvmx_fdt_sfp_info *sfp_info; /** SFP+/QSFP info for port */\n+\t/** Offset of SFP/SFP+/QSFP slot in device tree */\n+\tint sfp_of_offset;\n+\t/** Microsemi VSC7224 channel info data structure */\n+\tstruct cvmx_vsc7224_chan *vsc7224_chan;\n+\t/** Avago AVSP-5410 Phy */\n+\tstruct cvmx_avsp5410 *avsp5410;\n+\tstruct phy_device *phydev;\n+};\n+\n+/*\n+ * Per pko_port\n+ */\n+struct cvmx_cfg_pko_port_param {\n+\ts16 ccppp_queue_base;\n+\ts16 ccppp_num_queues;\n+};\n+\n+/*\n+ * A map from pko_port to\n+ * interface,\n+ * index, and\n+ * pko engine id\n+ */\n+struct cvmx_cfg_pko_port_map {\n+\ts16 ccppl_interface;\n+\ts16 ccppl_index;\n+\ts16 ccppl_eid;\n+};\n+\n+/*\n+ * This is for looking up pko_base_port and pko_nport for ipd_port\n+ */\n+struct cvmx_cfg_pko_port_pair {\n+\tint8_t ccppp_base_port;\n+\tint8_t ccppp_nports;\n+};\n+\n+typedef union cvmx_user_static_pko_queue_config {\n+\tstruct {\n+\t\tstruct pko_queues_cfg {\n+\t\t\tunsigned queues_per_port : 11, qos_enable : 1, pfc_enable : 1;\n+\t\t} pko_cfg_iface[6];\n+\t\tstruct pko_queues_cfg pko_cfg_loop;\n+\t\tstruct pko_queues_cfg pko_cfg_npi;\n+\t} pknd;\n+\tstruct {\n+\t\tu8 pko_ports_per_interface[5];\n+\t\tu8 pko_queues_per_port_interface[5];\n+\t\tu8 pko_queues_per_port_loop;\n+\t\tu8 pko_queues_per_port_pci;\n+\t\tu8 pko_queues_per_port_srio[4];\n+\t} non_pknd;\n+} cvmx_user_static_pko_queue_config_t;\n+\n+extern cvmx_user_static_pko_queue_config_t __cvmx_pko_queue_static_config[CVMX_MAX_NODES];\n+extern struct cvmx_cfg_pko_port_map cvmx_cfg_pko_port_map[CVMX_HELPER_CFG_MAX_PKO_PORT];\n+extern struct cvmx_cfg_port_param cvmx_cfg_port[CVMX_MAX_NODES][CVMX_HELPER_MAX_IFACE]\n+\t\t\t\t\t [CVMX_HELPER_CFG_MAX_PORT_PER_IFACE];\n+extern struct cvmx_cfg_pko_port_param cvmx_pko_queue_table[];\n+extern int cvmx_enable_helper_flag;\n+\n+/*\n+ * @INTERNAL\n+ * Return configured pknd for the port\n+ *\n+ * @param interface the interface number\n+ * @param index the port's index number\n+ * @return the pknd\n+ */\n+int __cvmx_helper_cfg_pknd(int interface, int index);\n+\n+/*\n+ * @INTERNAL\n+ * Return the configured bpid for the port\n+ *\n+ * @param interface the interface number\n+ * @param index the port's index number\n+ * @return the bpid\n+ */\n+int __cvmx_helper_cfg_bpid(int interface, int index);\n+\n+/**\n+ * @INTERNAL\n+ * Return the configured pko_port base for the port\n+ *\n+ * @param interface the interface number\n+ * @param index the port's index number\n+ * @return the pko_port base\n+ */\n+int __cvmx_helper_cfg_pko_port_base(int interface, int index);\n+\n+/*\n+ * @INTERNAL\n+ * Return the configured number of pko_ports for the port\n+ *\n+ * @param interface the interface number\n+ * @param index the port's index number\n+ * @return the number of pko_ports\n+ */\n+int __cvmx_helper_cfg_pko_port_num(int interface, int index);\n+\n+/*\n+ * @INTERNAL\n+ * Return the configured pko_queue base for the pko_port\n+ *\n+ * @param pko_port\n+ * @return the pko_queue base\n+ */\n+int __cvmx_helper_cfg_pko_queue_base(int pko_port);\n+\n+/*\n+ * @INTERNAL\n+ * Return the configured number of pko_queues for the pko_port\n+ *\n+ * @param pko_port\n+ * @return the number of pko_queues\n+ */\n+int __cvmx_helper_cfg_pko_queue_num(int pko_port);\n+\n+/*\n+ * @INTERNAL\n+ * Return the interface the pko_port is configured for\n+ *\n+ * @param pko_port\n+ * @return the interface for the pko_port\n+ */\n+int __cvmx_helper_cfg_pko_port_interface(int pko_port);\n+\n+/*\n+ * @INTERNAL\n+ * Return the index of the port the pko_port is configured for\n+ *\n+ * @param pko_port\n+ * @return the index of the port\n+ */\n+int __cvmx_helper_cfg_pko_port_index(int pko_port);\n+\n+/*\n+ * @INTERNAL\n+ * Return the pko_eid of the pko_port\n+ *\n+ * @param pko_port\n+ * @return the pko_eid\n+ */\n+int __cvmx_helper_cfg_pko_port_eid(int pko_port);\n+\n+/*\n+ * @INTERNAL\n+ * Return the max# of pko queues allocated.\n+ *\n+ * @return the max# of pko queues\n+ *\n+ * Note: there might be holes in the queue space depending on user\n+ * configuration. The function returns the highest queue's index in\n+ * use.\n+ */\n+int __cvmx_helper_cfg_pko_max_queue(void);\n+\n+/*\n+ * @INTERNAL\n+ * Return the max# of PKO DMA engines allocated.\n+ *\n+ * @return the max# of DMA engines\n+ *\n+ * NOTE: the DMA engines are allocated contiguously and starting from\n+ * 0.\n+ */\n+int __cvmx_helper_cfg_pko_max_engine(void);\n+\n+/*\n+ * Get the value set for the config option ``opt''.\n+ *\n+ * @param opt is the config option.\n+ * @return the value set for the option\n+ *\n+ * LR: only used for DWB in NPI, POW, PKO1\n+ */\n+u64 cvmx_helper_cfg_opt_get(cvmx_helper_cfg_option_t opt);\n+\n+/*\n+ * Set the value for a config option.\n+ *\n+ * @param opt is the config option.\n+ * @param val is the value to set for the opt.\n+ * @return 0 for success and -1 on error\n+ *\n+ * Note an option here is a config-time parameter and this means that\n+ * it has to be set before calling the corresponding setup functions\n+ * that actually sets the option in hw.\n+ *\n+ * LR: Not used.\n+ */\n+int cvmx_helper_cfg_opt_set(cvmx_helper_cfg_option_t opt, u64 val);\n+\n+/*\n+ * Retrieve the pko_port base given ipd_port.\n+ *\n+ * @param ipd_port is the IPD eport\n+ * @return the corresponding PKO port base for the physical port\n+ * represented by the IPD eport or CVMX_HELPER_CFG_INVALID_VALUE.\n+ */\n+int cvmx_helper_cfg_ipd2pko_port_base(int ipd_port);\n+\n+/*\n+ * Retrieve the number of pko_ports given ipd_port.\n+ *\n+ * @param ipd_port is the IPD eport\n+ * @return the corresponding number of PKO ports for the physical port\n+ * represented by IPD eport or CVMX_HELPER_CFG_INVALID_VALUE.\n+ */\n+int cvmx_helper_cfg_ipd2pko_port_num(int ipd_port);\n+\n+/*\n+ * @INTERNAL\n+ * The init function\n+ *\n+ * @param node\n+ * @return 0 for success.\n+ *\n+ * Note: this function is meant to be called to set the ``configured\n+ * parameters,'' e.g., pknd, bpid, etc. and therefore should be before\n+ * any of the corresponding cvmx_helper_cfg_xxxx() functions are\n+ * called.\n+ */\n+int __cvmx_helper_init_port_config_data(int node);\n+\n+/*\n+ * @INTERNAL\n+ * The local init function\n+ *\n+ * @param none\n+ * @return 0 for success.\n+ *\n+ * Note: this function is meant to be called to set the ``configured\n+ * parameters locally,'' e.g., pknd, bpid, etc. and therefore should be before\n+ * any of the corresponding cvmx_helper_cfg_xxxx() functions are\n+ * called.\n+ */\n+int __cvmx_helper_init_port_config_data_local(void);\n+\n+/*\n+ * Set the frame max size and jabber size to 65535.\n+ *\n+ */\n+void cvmx_helper_cfg_set_jabber_and_frame_max(void);\n+\n+/*\n+ * Enable storing short packets only in the WQE.\n+ */\n+void cvmx_helper_cfg_store_short_packets_in_wqe(void);\n+\n+/*\n+ * Allocated a block of internal ports and queues for the specified\n+ * interface/port\n+ *\n+ * @param interface the interface for which the internal ports and queues\n+ * are requested\n+ * @param port the index of the port within in the interface for which\n+\t\t the internal ports and queues are requested.\n+ * @param pot_count the number of internal ports requested\n+ * @param queue_cnt the number of queues requested for each of the internal\n+ * port. This call will allocate a total of\n+ *\t\t (port_cnt * queue_cnt) queues\n+ *\n+ * @return 0 on success\n+ * -1 on failure\n+ *\n+ * LR: Called ONLY from comfig-parse!\n+ */\n+int cvmx_pko_alloc_iport_and_queues(int interface, int port, int port_cnt, int queue_cnt);\n+\n+/*\n+ * Free the queues that are associated with the specified port\n+ *\n+ * @param port the internal port for which the queues are freed.\n+ *\n+ * @return 0 on success\n+ * -1 on failure\n+ */\n+int cvmx_pko_queue_free(u64 port);\n+\n+/*\n+ * Initializes the pko queue range data structure.\n+ * @return 0 on success\n+ * -1 on failure\n+ */\n+int init_cvmx_pko_que_range(void);\n+\n+/*\n+ * Frees up all the allocated ques.\n+ */\n+void cvmx_pko_queue_free_all(void);\n+\n+/**\n+ * Returns if port is valid for a given interface\n+ *\n+ * @param xiface interface to check\n+ * @param index port index in the interface\n+ *\n+ * @return status of the port present or not.\n+ */\n+int cvmx_helper_is_port_valid(int xiface, int index);\n+\n+/**\n+ * Set whether or not a port is valid\n+ *\n+ * @param interface interface to set\n+ * @param index port index to set\n+ * @param valid set 0 to make port invalid, 1 for valid\n+ */\n+void cvmx_helper_set_port_valid(int interface, int index, bool valid);\n+\n+/**\n+ * @INTERNAL\n+ * Return if port is in PHY mode\n+ *\n+ * @param interface the interface number\n+ * @param index the port's index number\n+ *\n+ * @return 1 if port is in PHY mode, 0 if port is in MAC mode\n+ */\n+bool cvmx_helper_get_mac_phy_mode(int interface, int index);\n+void cvmx_helper_set_mac_phy_mode(int interface, int index, bool valid);\n+\n+/**\n+ * @INTERNAL\n+ * Return if port is in 1000Base X mode\n+ *\n+ * @param interface the interface number\n+ * @param index the port's index number\n+ *\n+ * @return 1 if port is in 1000Base X mode, 0 if port is in SGMII mode\n+ */\n+bool cvmx_helper_get_1000x_mode(int interface, int index);\n+void cvmx_helper_set_1000x_mode(int interface, int index, bool valid);\n+\n+/**\n+ * @INTERNAL\n+ * Return if an AGL port should bypass the RX clock delay\n+ *\n+ * @param interface the interface number\n+ * @param index the port's index number\n+ */\n+bool cvmx_helper_get_agl_rx_clock_delay_bypass(int interface, int index);\n+void cvmx_helper_set_agl_rx_clock_delay_bypass(int interface, int index, bool valid);\n+\n+/**\n+ * @INTERNAL\n+ * Forces a link to always return that it is up ignoring the PHY (if present)\n+ *\n+ * @param interface the interface number\n+ * @param index the port's index\n+ */\n+bool cvmx_helper_get_port_force_link_up(int interface, int index);\n+void cvmx_helper_set_port_force_link_up(int interface, int index, bool value);\n+\n+/**\n+ * @INTERNAL\n+ * Return true if PHY is present to the passed xiface\n+ *\n+ * @param xiface the interface number\n+ * @param index the port's index\n+ */\n+bool cvmx_helper_get_port_phy_present(int xiface, int index);\n+void cvmx_helper_set_port_phy_present(int xiface, int index, bool value);\n+\n+/**\n+ * @INTERNAL\n+ * Return the AGL port rx clock skew, only used\n+ * if agl_rx_clock_delay_bypass is set.\n+ *\n+ * @param interface the interface number\n+ * @param index the port's index number\n+ */\n+u8 cvmx_helper_get_agl_rx_clock_skew(int interface, int index);\n+void cvmx_helper_set_agl_rx_clock_skew(int interface, int index, u8 value);\n+u8 cvmx_helper_get_agl_refclk_sel(int interface, int index);\n+void cvmx_helper_set_agl_refclk_sel(int interface, int index, u8 value);\n+\n+/**\n+ * @INTERNAL\n+ * Store the FDT node offset in the device tree of a port\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @param node_offset\tnode offset to store\n+ */\n+void cvmx_helper_set_port_fdt_node_offset(int xiface, int index, int node_offset);\n+\n+/**\n+ * @INTERNAL\n+ * Return the FDT node offset in the device tree of a port\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @return\t\tnode offset of port or -1 if invalid\n+ */\n+int cvmx_helper_get_port_fdt_node_offset(int xiface, int index);\n+\n+/**\n+ * @INTERNAL\n+ * Store the FDT node offset in the device tree of a phy\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @param node_offset\tnode offset to store\n+ */\n+void cvmx_helper_set_phy_fdt_node_offset(int xiface, int index, int node_offset);\n+\n+/**\n+ * @INTERNAL\n+ * Return the FDT node offset in the device tree of a phy\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @return\t\tnode offset of phy or -1 if invalid\n+ */\n+int cvmx_helper_get_phy_fdt_node_offset(int xiface, int index);\n+\n+/**\n+ * @INTERNAL\n+ * Override default autonegotiation for a port\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @param enable\ttrue to enable autonegotiation, false to force full\n+ *\t\t\tduplex, full speed.\n+ */\n+void cvmx_helper_set_port_autonegotiation(int xiface, int index, bool enable);\n+\n+/**\n+ * @INTERNAL\n+ * Returns if autonegotiation is enabled or not.\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ *\n+ * @return 0 if autonegotiation is disabled, 1 if enabled.\n+ */\n+bool cvmx_helper_get_port_autonegotiation(int xiface, int index);\n+\n+/**\n+ * @INTERNAL\n+ * Returns if forward error correction is enabled or not.\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ *\n+ * @return 0 if fec is disabled, 1 if enabled.\n+ */\n+bool cvmx_helper_get_port_fec(int xiface, int index);\n+\n+/**\n+ * @INTERNAL\n+ * Override default forward error correction for a port\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @param enable\ttrue to enable fec, false to disable.\n+ */\n+void cvmx_helper_set_port_fec(int xiface, int index, bool enable);\n+\n+/**\n+ * @INTERNAL\n+ * Configure the SRIO RX interface AGC settings in host mode\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tlane\n+ * @param long_run\ttrue for long run, false for short run\n+ * @param agc_override\ttrue to put AGC in manual mode\n+ * @param ctle_zero\tRX equalizer peaking control (default 0x6)\n+ * @param agc_pre_ctle\tAGC pre-CTLE gain (default 0x5)\n+ * @param agc_post_ctle\tAGC post-CTLE gain (default 0x4)\n+ *\n+ * NOTE: This must be called before SRIO is initialized to take effect\n+ */\n+void cvmx_helper_set_srio_rx(int xiface, int index, bool long_run, bool ctle_zero_override,\n+\t\t\t u8 ctle_zero, bool agc_override, u8 agc_pre_ctle, u8 agc_post_ctle);\n+\n+/**\n+ * @INTERNAL\n+ * Get the SRIO RX interface AGC settings for host mode\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tlane\n+ * @param long_run\ttrue for long run, false for short run\n+ * @param[out] ctle_zero_override true if overridden\n+ * @param[out] ctle_zero\tRX equalizer peaking control (default 0x6)\n+ * @param[out] agc_override\ttrue to put AGC in manual mode\n+ * @param[out] agc_pre_ctle\tAGC pre-CTLE gain (default 0x5)\n+ * @param[out] agc_post_ctle\tAGC post-CTLE gain (default 0x4)\n+ */\n+void cvmx_helper_get_srio_rx(int xiface, int index, bool long_run, bool *ctle_zero_override,\n+\t\t\t u8 *ctle_zero, bool *agc_override, u8 *agc_pre_ctle,\n+\t\t\t u8 *agc_post_ctle);\n+\n+/**\n+ * @INTERNAL\n+ * Configure the SRIO TX interface for host mode\n+ *\n+ * @param xiface\t\tnode and interface\n+ * @param index\t\t\tlane\n+ * @param long_run\ttrue for long run, false for short run\n+ * @param tx_swing\t\ttx swing value to use (default 0x7), -1 to not\n+ *\t\t\t\toverride.\n+ * @param tx_gain\t\tPCS SDS TX gain (default 0x3), -1 to not\n+ *\t\t\t\toverride\n+ * @param tx_premptap_override\ttrue to override preemphasis control\n+ * @param tx_premptap_pre\tpreemphasis pre tap value (default 0x0)\n+ * @param tx_premptap_post\tpreemphasis post tap value (default 0xF)\n+ * @param tx_vboost\t\tvboost enable (1 = enable, -1 = don't override)\n+ *\t\t\t\thardware default is 1.\n+ *\n+ * NOTE: This must be called before SRIO is initialized to take effect\n+ */\n+void cvmx_helper_set_srio_tx(int xiface, int index, bool long_run, int tx_swing, int tx_gain,\n+\t\t\t bool tx_premptap_override, u8 tx_premptap_pre, u8 tx_premptap_post,\n+\t\t\t int tx_vboost);\n+\n+/**\n+ * @INTERNAL\n+ * Get the SRIO TX interface settings for host mode\n+ *\n+ * @param xiface\t\t\tnode and interface\n+ * @param index\t\t\t\tlane\n+ * @param long_run\t\t\ttrue for long run, false for short run\n+ * @param[out] tx_swing_override\ttrue to override pcs_sds_txX_swing\n+ * @param[out] tx_swing\t\t\ttx swing value to use (default 0x7)\n+ * @param[out] tx_gain_override\t\ttrue to override default gain\n+ * @param[out] tx_gain\t\t\tPCS SDS TX gain (default 0x3)\n+ * @param[out] tx_premptap_override\ttrue to override preemphasis control\n+ * @param[out] tx_premptap_pre\t\tpreemphasis pre tap value (default 0x0)\n+ * @param[out] tx_premptap_post\t\tpreemphasis post tap value (default 0xF)\n+ * @param[out] tx_vboost_override\toverride vboost setting\n+ * @param[out] tx_vboost\t\tvboost enable (default true)\n+ */\n+void cvmx_helper_get_srio_tx(int xiface, int index, bool long_run, bool *tx_swing_override,\n+\t\t\t u8 *tx_swing, bool *tx_gain_override, u8 *tx_gain,\n+\t\t\t bool *tx_premptap_override, u8 *tx_premptap_pre, u8 *tx_premptap_post,\n+\t\t\t bool *tx_vboost_override, bool *tx_vboost);\n+\n+/**\n+ * @INTERNAL\n+ * Sets the PHY info data structure\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @param[in] phy_info\tphy information data structure pointer\n+ */\n+void cvmx_helper_set_port_phy_info(int xiface, int index, struct cvmx_phy_info *phy_info);\n+/**\n+ * @INTERNAL\n+ * Returns the PHY information data structure for a port\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ *\n+ * @return pointer to PHY information data structure or NULL if not set\n+ */\n+struct cvmx_phy_info *cvmx_helper_get_port_phy_info(int xiface, int index);\n+\n+/**\n+ * @INTERNAL\n+ * Returns a pointer to the PHY LED configuration (if local GPIOs drive them)\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tportindex\n+ *\n+ * @return pointer to the PHY LED information data structure or NULL if not\n+ *\t present\n+ */\n+struct cvmx_phy_gpio_leds *cvmx_helper_get_port_phy_leds(int xiface, int index);\n+\n+/**\n+ * @INTERNAL\n+ * Sets a pointer to the PHY LED configuration (if local GPIOs drive them)\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tportindex\n+ * @param leds\t\tpointer to led data structure\n+ */\n+void cvmx_helper_set_port_phy_leds(int xiface, int index, struct cvmx_phy_gpio_leds *leds);\n+\n+/**\n+ * @INTERNAL\n+ * Disables RGMII TX clock bypass and sets delay value\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tportindex\n+ * @param bypass\tSet true to enable the clock bypass and false\n+ *\t\t\tto sync clock and data synchronously.\n+ *\t\t\tDefault is false.\n+ * @param clk_delay\tDelay value to skew TXC from TXD\n+ */\n+void cvmx_helper_cfg_set_rgmii_tx_clk_delay(int xiface, int index, bool bypass, int clk_delay);\n+\n+/**\n+ * @INTERNAL\n+ * Gets RGMII TX clock bypass and delay value\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tportindex\n+ * @param bypass\tSet true to enable the clock bypass and false\n+ *\t\t\tto sync clock and data synchronously.\n+ *\t\t\tDefault is false.\n+ * @param clk_delay\tDelay value to skew TXC from TXD, default is 0.\n+ */\n+void cvmx_helper_cfg_get_rgmii_tx_clk_delay(int xiface, int index, bool *bypass, int *clk_delay);\n+\n+/**\n+ * @INTERNAL\n+ * Retrieve node-specific PKO Queue configuration.\n+ *\n+ * @param node\t\tOCTEON3 node.\n+ * @param pkocfg\tPKO Queue static configuration.\n+ */\n+int cvmx_helper_pko_queue_config_get(int node, cvmx_user_static_pko_queue_config_t *cfg);\n+\n+/**\n+ * @INTERNAL\n+ * Update node-specific PKO Queue configuration.\n+ *\n+ * @param node\t\tOCTEON3 node.\n+ * @param pkocfg\tPKO Queue static configuration.\n+ */\n+int cvmx_helper_pko_queue_config_set(int node, cvmx_user_static_pko_queue_config_t *cfg);\n+\n+/**\n+ * @INTERNAL\n+ * Retrieve the SFP node offset in the device tree\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ *\n+ * @return offset in device tree or -1 if error or not defined.\n+ */\n+int cvmx_helper_cfg_get_sfp_fdt_offset(int xiface, int index);\n+\n+/**\n+ * Search for a port based on its FDT node offset\n+ *\n+ * @param\tof_offset\tNode offset of port to search for\n+ *\n+ * @return\tipd_port or -1 if not found\n+ */\n+int cvmx_helper_cfg_get_ipd_port_by_fdt_node_offset(int of_offset);\n+\n+/**\n+ * @INTERNAL\n+ * Sets the SFP node offset\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @param sfp_of_offset\tOffset of SFP node in device tree\n+ */\n+void cvmx_helper_cfg_set_sfp_fdt_offset(int xiface, int index, int sfp_of_offset);\n+\n+/**\n+ * Search for a port based on its FDT node offset\n+ *\n+ * @param\tof_offset\tNode offset of port to search for\n+ * @param[out]\txiface\t\txinterface of match\n+ * @param[out]\tindex\t\tport index of match\n+ *\n+ * @return\t0 if found, -1 if not found\n+ */\n+int cvmx_helper_cfg_get_xiface_index_by_fdt_node_offset(int of_offset, int *xiface, int *index);\n+\n+/**\n+ * Get data structure defining the Microsemi VSC7224 channel info\n+ * or NULL if not present\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ *\n+ * @return pointer to vsc7224 data structure or NULL if not present\n+ */\n+struct cvmx_vsc7224_chan *cvmx_helper_cfg_get_vsc7224_chan_info(int xiface, int index);\n+\n+/**\n+ * Sets the Microsemi VSC7224 channel data structure\n+ *\n+ * @param\txiface\tnode and interface\n+ * @param\tindex\tport index\n+ * @param[in]\tvsc7224_info\tMicrosemi VSC7224 data structure\n+ */\n+void cvmx_helper_cfg_set_vsc7224_chan_info(int xiface, int index,\n+\t\t\t\t\t struct cvmx_vsc7224_chan *vsc7224_chan_info);\n+\n+/**\n+ * Get data structure defining the Avago AVSP5410 phy info\n+ * or NULL if not present\n+ *\n+ * @param xiface node and interface\n+ * @param index port index\n+ *\n+ * @return pointer to avsp5410 data structure or NULL if not present\n+ */\n+struct cvmx_avsp5410 *cvmx_helper_cfg_get_avsp5410_info(int xiface, int index);\n+\n+/**\n+ * Sets the Avago AVSP5410 phy info data structure\n+ *\n+ * @param xiface node and interface\n+ * @param index port index\n+ * @param[in] avsp5410_info Avago AVSP5410 data structure\n+ */\n+void cvmx_helper_cfg_set_avsp5410_info(int xiface, int index, struct cvmx_avsp5410 *avsp5410_info);\n+\n+/**\n+ * Gets the SFP data associated with a port\n+ *\n+ * @param\txiface\tnode and interface\n+ * @param\tindex\tport index\n+ *\n+ * @return\tpointer to SFP data structure or NULL if none\n+ */\n+struct cvmx_fdt_sfp_info *cvmx_helper_cfg_get_sfp_info(int xiface, int index);\n+\n+/**\n+ * Sets the SFP data associated with a port\n+ *\n+ * @param\txiface\t\tnode and interface\n+ * @param\tindex\t\tport index\n+ * @param[in]\tsfp_info\tport SFP data or NULL for none\n+ */\n+void cvmx_helper_cfg_set_sfp_info(int xiface, int index, struct cvmx_fdt_sfp_info *sfp_info);\n+\n+/*\n+ * Initializes cvmx with user specified config info.\n+ */\n+int cvmx_user_static_config(void);\n+void cvmx_pko_queue_show(void);\n+int cvmx_fpa_pool_init_from_cvmx_config(void);\n+int __cvmx_helper_init_port_valid(void);\n+\n+/**\n+ * Returns a pointer to the phy device associated with a port\n+ *\n+ * @param\txiface\t\tnode and interface\n+ * @param\tindex\t\tport index\n+ *\n+ * return\tpointer to phy device or NULL if none\n+ */\n+struct phy_device *cvmx_helper_cfg_get_phy_device(int xiface, int index);\n+\n+/**\n+ * Sets the phy device associated with a port\n+ *\n+ * @param\txiface\t\tnode and interface\n+ * @param\tindex\t\tport index\n+ * @param[in]\tphydev\t\tphy device to assiciate\n+ */\n+void cvmx_helper_cfg_set_phy_device(int xiface, int index, struct phy_device *phydev);\n+\n+#endif /* __CVMX_HELPER_CFG_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-errata.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-errata.h\nnew file mode 100644\nindex 0000000000..9ed13c1626\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-errata.h\n@@ -0,0 +1,50 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Fixes and workaround for Octeon chip errata. This file\n+ * contains functions called by cvmx-helper to workaround known\n+ * chip errata. For the most part, code doesn't need to call\n+ * these functions directly.\n+ */\n+\n+#ifndef __CVMX_HELPER_ERRATA_H__\n+#define __CVMX_HELPER_ERRATA_H__\n+\n+#include \"cvmx-wqe.h\"\n+\n+/**\n+ * @INTERNAL\n+ * Function to adjust internal IPD pointer alignments\n+ *\n+ * @return 0 on success\n+ * !0 on failure\n+ */\n+int __cvmx_helper_errata_fix_ipd_ptr_alignment(void);\n+\n+/**\n+ * This function needs to be called on all Octeon chips with\n+ * errata PKI-100.\n+ *\n+ * The Size field is 8 too large in WQE and next pointers\n+ *\n+ * The Size field generated by IPD is 8 larger than it should\n+ * be. The Size field is <55:40> of both:\n+ * - WORD3 in the work queue entry, and\n+ * - the next buffer pointer (which precedes the packet data\n+ * in each buffer).\n+ *\n+ * @param work Work queue entry to fix\n+ * @return Zero on success. Negative on failure\n+ */\n+int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work);\n+\n+/**\n+ * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass\n+ * 1 doesn't work properly. The following code disables 2nd order\n+ * CDR for the specified QLM.\n+ *\n+ * @param qlm QLM to disable 2nd order CDR for.\n+ */\n+void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);\n+#endif\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-fdt.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-fdt.h\nnew file mode 100644\nindex 0000000000..d3809aec29\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-fdt.h\n@@ -0,0 +1,568 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * FDT Helper functions similar to those provided to U-Boot.\n+ * If compiled for U-Boot, just provide wrappers to the equivalent U-Boot\n+ * functions.\n+ */\n+\n+#ifndef __CVMX_HELPER_FDT_H__\n+#define __CVMX_HELPER_FDT_H__\n+\n+#include <fdt_support.h>\n+#include <fdtdec.h>\n+#include <time.h>\n+#include <asm/global_data.h>\n+#include <linux/libfdt.h>\n+\n+#include <mach/cvmx-helper-sfp.h>\n+\n+enum cvmx_i2c_bus_type {\n+\tCVMX_I2C_BUS_OCTEON,\n+\tCVMX_I2C_MUX_PCA9540,\n+\tCVMX_I2C_MUX_PCA9542,\n+\tCVMX_I2C_MUX_PCA9543,\n+\tCVMX_I2C_MUX_PCA9544,\n+\tCVMX_I2C_MUX_PCA9545,\n+\tCVMX_I2C_MUX_PCA9546,\n+\tCVMX_I2C_MUX_PCA9547,\n+\tCVMX_I2C_MUX_PCA9548,\n+\tCVMX_I2C_MUX_OTHER\n+};\n+\n+struct cvmx_sfp_mod_info; /** Defined in cvmx-helper-sfp.h */\n+struct cvmx_phy_info;\t /** Defined in cvmx-helper-board.h */\n+\n+/**\n+ * This data structure holds information about various I2C muxes and switches\n+ * that may be between a device and the Octeon chip.\n+ */\n+struct cvmx_fdt_i2c_bus_info {\n+\t/** Parent I2C bus, NULL if root */\n+\tstruct cvmx_fdt_i2c_bus_info *parent;\n+\t/** Child I2C bus or NULL if last entry in the chain */\n+\tstruct cvmx_fdt_i2c_bus_info *child;\n+\t/** Offset in device tree */\n+\tint of_offset;\n+\t/** Type of i2c bus or mux */\n+\tenum cvmx_i2c_bus_type type;\n+\t/** I2C address of mux */\n+\tu8 i2c_addr;\n+\t/** Mux channel number */\n+\tu8 channel;\n+\t/** For muxes, the bit(s) to set to enable them */\n+\tu8 enable_bit;\n+\t/** True if mux, false if switch */\n+\tbool is_mux;\n+};\n+\n+/**\n+ * Data structure containing information about SFP/QSFP slots\n+ */\n+struct cvmx_fdt_sfp_info {\n+\t/** Used for a linked list of slots */\n+\tstruct cvmx_fdt_sfp_info *next, *prev;\n+\t/** Used when multiple SFP ports share the same IPD port */\n+\tstruct cvmx_fdt_sfp_info *next_iface_sfp;\n+\t/** Name from device tree of slot */\n+\tconst char *name;\n+\t/** I2C bus for slot EEPROM */\n+\tstruct cvmx_fdt_i2c_bus_info *i2c_bus;\n+\t/** Data from SFP or QSFP EEPROM */\n+\tstruct cvmx_sfp_mod_info sfp_info;\n+\t/** Data structure with PHY information */\n+\tstruct cvmx_phy_info *phy_info;\n+\t/** IPD port(s) slot is connected to */\n+\tint ipd_port[4];\n+\t/** Offset in device tree of slot */\n+\tint of_offset;\n+\t/** EEPROM address of SFP module (usually 0x50) */\n+\tu8 i2c_eeprom_addr;\n+\t/** Diagnostic address of SFP module (usually 0x51) */\n+\tu8 i2c_diag_addr;\n+\t/** True if QSFP module */\n+\tbool is_qsfp;\n+\t/** True if EEPROM data is valid */\n+\tbool valid;\n+\t/** SFP tx_disable GPIO descriptor */\n+\tstruct cvmx_fdt_gpio_info *tx_disable;\n+\t/** SFP mod_abs/QSFP mod_prs GPIO descriptor */\n+\tstruct cvmx_fdt_gpio_info *mod_abs;\n+\t/** SFP tx_error GPIO descriptor */\n+\tstruct cvmx_fdt_gpio_info *tx_error;\n+\t/** SFP rx_los GPIO discriptor */\n+\tstruct cvmx_fdt_gpio_info *rx_los;\n+\t/** QSFP select GPIO descriptor */\n+\tstruct cvmx_fdt_gpio_info *select;\n+\t/** QSFP reset GPIO descriptor */\n+\tstruct cvmx_fdt_gpio_info *reset;\n+\t/** QSFP interrupt GPIO descriptor */\n+\tstruct cvmx_fdt_gpio_info *interrupt;\n+\t/** QSFP lp_mode GPIO descriptor */\n+\tstruct cvmx_fdt_gpio_info *lp_mode;\n+\t/** Last mod_abs value */\n+\tint last_mod_abs;\n+\t/** Last rx_los value */\n+\tint last_rx_los;\n+\t/** Function to call to check mod_abs */\n+\tint (*check_mod_abs)(struct cvmx_fdt_sfp_info *sfp_info, void *data);\n+\t/** User-defined data to pass to check_mod_abs */\n+\tvoid *mod_abs_data;\n+\t/** Function to call when mod_abs changes */\n+\tint (*mod_abs_changed)(struct cvmx_fdt_sfp_info *sfp_info, int val, void *data);\n+\t/** User-defined data to pass to mod_abs_changed */\n+\tvoid *mod_abs_changed_data;\n+\t/** Function to call when rx_los changes */\n+\tint (*rx_los_changed)(struct cvmx_fdt_sfp_info *sfp_info, int val, void *data);\n+\t/** User-defined data to pass to rx_los_changed */\n+\tvoid *rx_los_changed_data;\n+\t/** True if we're connected to a Microsemi VSC7224 reclocking chip */\n+\tbool is_vsc7224;\n+\t/** Data structure for first vsc7224 channel we're attached to */\n+\tstruct cvmx_vsc7224_chan *vsc7224_chan;\n+\t/** True if we're connected to a Avago AVSP5410 phy */\n+\tbool is_avsp5410;\n+\t/** Data structure for avsp5410 phy we're attached to */\n+\tstruct cvmx_avsp5410 *avsp5410;\n+\t/** xinterface we're on */\n+\tint xiface;\n+\t/** port index */\n+\tint index;\n+};\n+\n+/**\n+ * Look up a phandle and follow it to its node then return the offset of that\n+ * node.\n+ *\n+ * @param[in]\tfdt_addr\tpointer to FDT blob\n+ * @param\tnode\t\tnode to read phandle from\n+ * @param[in]\tprop_name\tname of property to find\n+ * @param[in,out] lenp\t\tNumber of phandles, input max number\n+ * @param[out]\tnodes\t\tArray of phandle nodes\n+ *\n+ * @return\t-ve error code on error or 0 for success\n+ */\n+int cvmx_fdt_lookup_phandles(const void *fdt_addr, int node, const char *prop_name, int *lenp,\n+\t\t\t int *nodes);\n+\n+/**\n+ * Helper to return the address property\n+ *\n+ * @param[in] fdt_addr\tpointer to FDT blob\n+ * @param node\t\tnode to read address from\n+ * @param prop_name\tproperty name to read\n+ *\n+ * @return address of property or FDT_ADDR_T_NONE if not found\n+ */\n+static inline fdt_addr_t cvmx_fdt_get_addr(const void *fdt_addr, int node, const char *prop_name)\n+{\n+\treturn fdtdec_get_addr(fdt_addr, node, prop_name);\n+}\n+\n+/**\n+ * Helper function to return an integer property\n+ *\n+ * @param[in] fdt_addr\tpointer to FDT blob\n+ * @param node\t\tnode to read integer from\n+ * @param[in] prop_name\tproperty name to read\n+ * @param default_val\tdefault value to return if property doesn't exist\n+ *\n+ * @return\tinteger value of property or default_val if it doesn't exist.\n+ */\n+static inline int cvmx_fdt_get_int(const void *fdt_addr, int node, const char *prop_name,\n+\t\t\t\t int default_val)\n+{\n+\treturn fdtdec_get_int(fdt_addr, node, prop_name, default_val);\n+}\n+\n+static inline bool cvmx_fdt_get_bool(const void *fdt_addr, int node, const char *prop_name)\n+{\n+\treturn fdtdec_get_bool(fdt_addr, node, prop_name);\n+}\n+\n+static inline u64 cvmx_fdt_get_uint64(const void *fdt_addr, int node, const char *prop_name,\n+\t\t\t\t u64 default_val)\n+{\n+\treturn fdtdec_get_uint64(fdt_addr, node, prop_name, default_val);\n+}\n+\n+/**\n+ * Look up a phandle and follow it to its node then return the offset of that\n+ * node.\n+ *\n+ * @param[in] fdt_addr\tpointer to FDT blob\n+ * @param node\t\tnode to read phandle from\n+ * @param[in] prop_name\tname of property to find\n+ *\n+ * @return\tnode offset if found, -ve error code on error\n+ */\n+static inline int cvmx_fdt_lookup_phandle(const void *fdt_addr, int node, const char *prop_name)\n+{\n+\treturn fdtdec_lookup_phandle(fdt_addr, node, prop_name);\n+}\n+\n+/**\n+ * Translate an address from the device tree into a CPU physical address by\n+ * walking up the device tree and applying bus mappings along the way.\n+ *\n+ * This uses #size-cells and #address-cells.\n+ *\n+ * @param[in]\tfdt_addr\tAddress of flat device tree\n+ * @param\tnode\t\tnode to start translating from\n+ * @param[in]\tin_addr\t\tAddress to translate\n+ *\t\t\t\tNOTE: in_addr must be in the native ENDIAN\n+ *\t\t\t\tformat.\n+ *\n+ * @return\tTranslated address or FDT_ADDR_T_NONE if address cannot be\n+ *\t\ttranslated.\n+ */\n+static inline u64 cvmx_fdt_translate_address(const void *fdt_addr, int node, const u32 *in_addr)\n+{\n+\treturn fdt_translate_address((void *)fdt_addr, node, in_addr);\n+}\n+\n+/**\n+ * Compare compatibile strings in the flat device tree.\n+ *\n+ * @param[in] s1\tFirst string to compare\n+ * @param[in] sw\tSecond string to compare\n+ *\n+ * @return\t0 if no match\n+ *\t\t1 if only the part number matches and not the manufacturer\n+ *\t\t2 if both the part number and manufacturer match\n+ */\n+int cvmx_fdt_compat_match(const char *s1, const char *s2);\n+\n+/**\n+ * Returns whether a list of strings contains the specified string\n+ *\n+ * @param[in]\tslist\tString list\n+ * @param\tllen\tstring list total length\n+ * @param[in]\tstr\tstring to search for\n+ *\n+ * @return\t1 if string list contains string, 0 if it does not.\n+ */\n+int cvmx_fdt_compat_list_contains(const char *slist, int llen, const char *str);\n+\n+/**\n+ * Check if a node is compatible with the specified compat string\n+ *\n+ * @param[in]\tfdt_addr\tFDT address\n+ * @param\tnode\t\tnode offset to check\n+ * @param[in]\tcompat\t\tcompatible string to check\n+ *\n+ * @return\t0 if compatible, 1 if not compatible, error if negative\n+ */\n+int cvmx_fdt_node_check_compatible(const void *fdt_addr, int node, const char *compat);\n+\n+/**\n+ * @INTERNAL\n+ * Compares a string to a compatible field.\n+ *\n+ * @param[in]\tcompat\t\tcompatible string\n+ * @param[in]\tstr\t\tstring to check\n+ *\n+ * @return\t0 if not compatible, 1 if manufacturer compatible, 2 if\n+ *\t\tpart is compatible, 3 if both part and manufacturer are\n+ *\t\tcompatible.\n+ */\n+int __cvmx_fdt_compat_match(const char *compat, const char *str);\n+\n+/**\n+ * Given a phandle to a GPIO device return the type of GPIO device it is.\n+ *\n+ * @param[in]\tfdt_addr\tAddress of flat device tree\n+ * @param\tphandle\t\tphandle to GPIO\n+ * @param[out]\tsize\t\tNumber of pins (optional, may be NULL)\n+ *\n+ * @return\tType of GPIO device or PIN_ERROR if error\n+ */\n+enum cvmx_gpio_type cvmx_fdt_get_gpio_type(const void *fdt_addr, int phandle, int *size);\n+\n+/**\n+ * Given a phandle to a GPIO node output the i2c bus and address\n+ *\n+ * @param[in]\tfdt_addr\tAddress of FDT\n+ * @param\tphandle\t\tphandle of GPIO device\n+ * @param[out]\tbus\t\tTWSI bus number with node in bits 1-3, can be\n+ *\t\t\t\tNULL for none.\n+ * @param[out]\taddr\t\tTWSI address number, can be NULL for none\n+ *\n+ * @return\t0 for success, error otherwise\n+ */\n+int cvmx_fdt_get_twsi_gpio_bus_addr(const void *fdt_addr, int phandle, int *bus, int *addr);\n+\n+/**\n+ * Given a FDT node return the CPU node number\n+ *\n+ * @param[in]\tfdt_addr\tAddress of FDT\n+ * @param\tnode\t\tFDT node number\n+ *\n+ * @return\tCPU node number or error if negative\n+ */\n+int cvmx_fdt_get_cpu_node(const void *fdt_addr, int node);\n+\n+/**\n+ * Get the total size of the flat device tree\n+ *\n+ * @param[in]\tfdt_addr\tAddress of FDT\n+ *\n+ * @return\tSize of flat device tree in bytes or -1 if error.\n+ */\n+int cvmx_fdt_get_fdt_size(const void *fdt_addr);\n+\n+/**\n+ * Returns if a node is compatible with one of the items in the string list\n+ *\n+ * @param[in]\tfdt_addr\tPointer to flat device tree\n+ * @param\tnode\t\tNode offset to check\n+ * @param[in]\tstrlist\t\tArray of FDT device compatibility strings,\n+ *\t\t\t\tmust end with NULL or empty string.\n+ *\n+ * @return\t0 if at least one item matches, 1 if no matches\n+ */\n+int cvmx_fdt_node_check_compatible_list(const void *fdt_addr, int node, const char *const *strlist);\n+\n+/**\n+ * Given a FDT node, return the next compatible node.\n+ *\n+ * @param[in]\tfdt_addr\tPointer to flat device tree\n+ * @param\tstart_offset\tStarting node offset or -1 to find the first\n+ * @param\tstrlist\t\tArray of FDT device compatibility strings, must\n+ *\t\t\t\tend with NULL or empty string.\n+ *\n+ * @return\tnext matching node or -1 if no more matches.\n+ */\n+int cvmx_fdt_node_offset_by_compatible_list(const void *fdt_addr, int startoffset,\n+\t\t\t\t\t const char *const *strlist);\n+\n+/**\n+ * Given the parent offset of an i2c device build up a list describing the bus\n+ * which can contain i2c muxes and switches.\n+ *\n+ * @param[in]\tfdt_addr\taddress of device tree\n+ * @param\tof_offset\tOffset of the parent node of a GPIO device in\n+ *\t\t\t\tthe device tree.\n+ *\n+ * @return\tpointer to list of i2c devices starting from the root which\n+ *\t\tcan include i2c muxes and switches or NULL if error. Note that\n+ *\t\tall entries are allocated on the heap.\n+ *\n+ * @see cvmx_fdt_free_i2c_bus()\n+ */\n+struct cvmx_fdt_i2c_bus_info *cvmx_fdt_get_i2c_bus(const void *fdt_addr, int of_offset);\n+\n+/**\n+ * Return the Octeon bus number for a bus descriptor\n+ *\n+ * @param[in]\tbus\tbus descriptor\n+ *\n+ * @return\tOcteon twsi bus number or -1 on error\n+ */\n+int cvmx_fdt_i2c_get_root_bus(const struct cvmx_fdt_i2c_bus_info *bus);\n+\n+/**\n+ * Frees all entries for an i2c bus descriptor\n+ *\n+ * @param\tbus\tbus to free\n+ *\n+ * @return\t0\n+ */\n+int cvmx_fdt_free_i2c_bus(struct cvmx_fdt_i2c_bus_info *bus);\n+\n+/**\n+ * Given the bus to a device, enable it.\n+ *\n+ * @param[in]\tbus\ti2c bus descriptor to enable or disable\n+ * @param\tenable\tset to true to enable, false to disable\n+ *\n+ * @return\t0 for success or -1 for invalid bus\n+ *\n+ * This enables the entire bus including muxes and switches in the path.\n+ */\n+int cvmx_fdt_enable_i2c_bus(const struct cvmx_fdt_i2c_bus_info *bus, bool enable);\n+\n+/**\n+ * Return a GPIO handle given a GPIO phandle of the form <&gpio pin flags>\n+ *\n+ * @param[in]\tfdt_addr\tAddress of flat device tree\n+ * @param\tof_offset\tnode offset for property\n+ * @param\tprop_name\tname of property\n+ *\n+ * @return\tpointer to GPIO handle or NULL if error\n+ */\n+struct cvmx_fdt_gpio_info *cvmx_fdt_gpio_get_info_phandle(const void *fdt_addr, int of_offset,\n+\t\t\t\t\t\t\t const char *prop_name);\n+\n+/**\n+ * Sets a GPIO pin given the GPIO descriptor\n+ *\n+ * @param\tpin\tGPIO pin descriptor\n+ * @param\tvalue\tvalue to set it to, 0 or 1\n+ *\n+ * @return\t0 on success, -1 on error.\n+ *\n+ * NOTE: If the CVMX_GPIO_ACTIVE_LOW flag is set then the output value will be\n+ * inverted.\n+ */\n+int cvmx_fdt_gpio_set(struct cvmx_fdt_gpio_info *pin, int value);\n+\n+/**\n+ * Given a GPIO pin descriptor, input the value of that pin\n+ *\n+ * @param\tpin\tGPIO pin descriptor\n+ *\n+ * @return\t0 if low, 1 if high, -1 on error. Note that the input will be\n+ *\t\tinverted if the CVMX_GPIO_ACTIVE_LOW flag bit is set.\n+ */\n+int cvmx_fdt_gpio_get(struct cvmx_fdt_gpio_info *pin);\n+\n+/**\n+ * Assigns an IPD port to a SFP slot\n+ *\n+ * @param\tsfp\t\tHandle to SFP data structure\n+ * @param\tipd_port\tPort to assign it to\n+ *\n+ * @return\t0 for success, -1 on error\n+ */\n+int cvmx_sfp_set_ipd_port(struct cvmx_fdt_sfp_info *sfp, int ipd_port);\n+\n+/**\n+ * Get the IPD port of a SFP slot\n+ *\n+ * @param[in]\tsfp\t\tHandle to SFP data structure\n+ *\n+ * @return\tIPD port number for SFP slot\n+ */\n+static inline int cvmx_sfp_get_ipd_port(const struct cvmx_fdt_sfp_info *sfp)\n+{\n+\treturn sfp->ipd_port[0];\n+}\n+\n+/**\n+ * Get the IPD ports for a QSFP port\n+ *\n+ * @param[in]\tsfp\t\tHandle to SFP data structure\n+ * @param[out]\tipd_ports\tIPD ports for each lane, if running as 40G then\n+ *\t\t\t\tonly ipd_ports[0] is valid and the others will\n+ *\t\t\t\tbe set to -1.\n+ */\n+static inline void cvmx_qsfp_get_ipd_ports(const struct cvmx_fdt_sfp_info *sfp, int ipd_ports[4])\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < 4; i++)\n+\t\tipd_ports[i] = sfp->ipd_port[i];\n+}\n+\n+/**\n+ * Attaches a PHY to a SFP or QSFP.\n+ *\n+ * @param\tsfp\t\tsfp to attach PHY to\n+ * @param\tphy_info\tphy descriptor to attach or NULL to detach\n+ */\n+void cvmx_sfp_attach_phy(struct cvmx_fdt_sfp_info *sfp, struct cvmx_phy_info *phy_info);\n+\n+/**\n+ * Returns a phy descriptor for a SFP slot\n+ *\n+ * @param[in]\tsfp\tSFP to get phy info from\n+ *\n+ * @return\tphy descriptor or NULL if none.\n+ */\n+static inline struct cvmx_phy_info *cvmx_sfp_get_phy_info(const struct cvmx_fdt_sfp_info *sfp)\n+{\n+\treturn sfp->phy_info;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Parses all instances of the Vitesse VSC7224 reclocking chip\n+ *\n+ * @param[in]\tfdt_addr\tAddress of flat device tree\n+ *\n+ * @return\t0 for success, error otherwise\n+ */\n+int __cvmx_fdt_parse_vsc7224(const void *fdt_addr);\n+\n+/**\n+ * @INTERNAL\n+ * Parses all instances of the Avago AVSP5410 gearbox phy\n+ *\n+ * @param[in] fdt_addr Address of flat device tree\n+ *\n+ * @return 0 for success, error otherwise\n+ */\n+int __cvmx_fdt_parse_avsp5410(const void *fdt_addr);\n+\n+/**\n+ * Parse SFP information from device tree\n+ *\n+ * @param[in]\tfdt_addr\tAddress of flat device tree\n+ *\n+ * @return pointer to sfp info or NULL if error\n+ */\n+struct cvmx_fdt_sfp_info *cvmx_helper_fdt_parse_sfp_info(const void *fdt_addr, int of_offset);\n+\n+/**\n+ * @INTERNAL\n+ * Parses either a CS4343 phy or a slice of the phy from the device tree\n+ * @param[in]\tfdt_addr\tAddress of FDT\n+ * @param\tof_offset\toffset of slice or phy in device tree\n+ * @param\tphy_info\tphy_info data structure to fill in\n+ *\n+ * @return\t0 for success, -1 on error\n+ */\n+int cvmx_fdt_parse_cs4343(const void *fdt_addr, int of_offset, struct cvmx_phy_info *phy_info);\n+\n+/**\n+ * Given an i2c bus and device address, write an 8 bit value\n+ *\n+ * @param bus\ti2c bus number\n+ * @param addr\ti2c device address (7 bits)\n+ * @param val\t8-bit value to write\n+ *\n+ * This is just an abstraction to ease support in both U-Boot and SE.\n+ */\n+void cvmx_fdt_i2c_reg_write(int bus, int addr, u8 val);\n+\n+/**\n+ * Read an 8-bit value from an i2c bus and device address\n+ *\n+ * @param bus\ti2c bus number\n+ * @param addr\ti2c device address (7 bits)\n+ *\n+ * @return 8-bit value or error if negative\n+ */\n+int cvmx_fdt_i2c_reg_read(int bus, int addr);\n+\n+/**\n+ * Write an 8-bit value to a register indexed i2c device\n+ *\n+ * @param bus\ti2c bus number to write to\n+ * @param addr\ti2c device address (7 bits)\n+ * @param reg\ti2c 8-bit register address\n+ * @param val\t8-bit value to write\n+ *\n+ * @return 0 for success, otherwise error\n+ */\n+int cvmx_fdt_i2c_write8(int bus, int addr, int reg, u8 val);\n+\n+/**\n+ * Read an 8-bit value from a register indexed i2c device\n+ *\n+ * @param bus\ti2c bus number to write to\n+ * @param addr\ti2c device address (7 bits)\n+ * @param reg\ti2c 8-bit register address\n+ *\n+ * @return value or error if negative\n+ */\n+int cvmx_fdt_i2c_read8(int bus, int addr, int reg);\n+\n+int cvmx_sfp_vsc7224_mod_abs_changed(struct cvmx_fdt_sfp_info *sfp_info,\n+\t\t\t\t int val, void *data);\n+int cvmx_sfp_avsp5410_mod_abs_changed(struct cvmx_fdt_sfp_info *sfp_info,\n+\t\t\t\t int val, void *data);\n+\n+#endif /* CVMX_HELPER_FDT_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-fpa.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-fpa.h\nnew file mode 100644\nindex 0000000000..8b3a89bce4\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-fpa.h\n@@ -0,0 +1,43 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Helper functions for FPA setup.\n+ */\n+\n+#ifndef __CVMX_HELPER_H_FPA__\n+#define __CVMX_HELPER_H_FPA__\n+\n+/**\n+ * Allocate memory and initialize the FPA pools using memory\n+ * from cvmx-bootmem. Sizes of each element in the pools is\n+ * controlled by the cvmx-config.h header file. Specifying\n+ * zero for any parameter will cause that FPA pool to not be\n+ * setup. This is useful if you aren't using some of the\n+ * hardware and want to save memory.\n+ *\n+ * @param packet_buffers\n+ * Number of packet buffers to allocate\n+ * @param work_queue_entries\n+ * Number of work queue entries\n+ * @param pko_buffers\n+ * PKO Command buffers. You should at minimum have two per\n+ * each PKO queue.\n+ * @param tim_buffers\n+ * TIM ring buffer command queues. At least two per timer bucket\n+ * is recommended.\n+ * @param dfa_buffers\n+ * DFA command buffer. A relatively small (32 for example)\n+ * number should work.\n+ * @return Zero on success, non-zero if out of memory\n+ */\n+int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries, int pko_buffers,\n+\t\t\t int tim_buffers, int dfa_buffers);\n+\n+int __cvmx_helper_initialize_fpa_pool(int pool, u64 buffer_size, u64 buffers, const char *name);\n+\n+int cvmx_helper_shutdown_fpa_pools(int node);\n+\n+void cvmx_helper_fpa_dump(int node);\n+\n+#endif /* __CVMX_HELPER_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-gpio.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-gpio.h\nnew file mode 100644\nindex 0000000000..787eccf4aa\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-gpio.h\n@@ -0,0 +1,427 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Defines some GPIO information used in multiple places\n+ */\n+\n+#ifndef __CVMX_HELPER_GPIO_H__\n+#define __CVMX_HELPER_GPIO_H__\n+\n+#define CVMX_GPIO_NAME_LEN 32 /** Length of name */\n+\n+enum cvmx_gpio_type {\n+\tCVMX_GPIO_PIN_OCTEON, /** GPIO pin is directly connected to OCTEON */\n+\tCVMX_GPIO_PIN_PCA953X, /** GPIO pin is NXP PCA953X compat chip */\n+\tCVMX_GPIO_PIN_PCA957X,\n+\tCVMX_GPIO_PIN_PCF857X, /** GPIO pin is NXP PCF857X compat chip */\n+\tCVMX_GPIO_PIN_PCA9698, /** GPIO pin is NXP PCA9698 compat chip */\n+\tCVMX_GPIO_PIN_CS4343, /** Inphi/Cortina CS4343 GPIO pins */\n+\tCVMX_GPIO_PIN_OTHER, /** GPIO pin is something else */\n+};\n+\n+enum cvmx_gpio_operation {\n+\tCVMX_GPIO_OP_CONFIG,\t /** Initial configuration of the GPIO pin */\n+\tCVMX_GPIO_OP_SET,\t /** Set pin */\n+\tCVMX_GPIO_OP_CLEAR,\t /** Clear pin */\n+\tCVMX_GPIO_OP_READ,\t /** Read pin */\n+\tCVMX_GPIO_OP_TOGGLE,\t /** Toggle pin */\n+\tCVMX_GPIO_OP_BLINK_START, /** Put in blink mode (if supported) */\n+\tCVMX_GPIO_OP_BLINK_STOP, /** Takes the pin out of blink mode */\n+\tCVMX_GPIO_OP_SET_LINK,\t /** Put in link monitoring mode */\n+\tCVMX_GPIO_OP_SET_ACT,\t /** Put in RX activity mode */\n+};\n+\n+/**\n+ * Inphi CS4343 output source select values for the GPIO_GPIOX output_src_sel.\n+ */\n+enum cvmx_inphi_cs4343_gpio_gpio_output_src_sel {\n+\tGPIO_SEL_DRIVE = 0,\t/** Value of GPIOX_DRIVE */\n+\tGPIO_SEL_DELAY = 1,\t/** Drive delayed */\n+\tGPIO_SEL_TOGGLE = 2,\t/** Used for blinking */\n+\tGPIO_SEL_EXT = 3,\t/** External function */\n+\tGPIO_SEL_EXT_DELAY = 4, /** External function delayed */\n+};\n+\n+/** Inphi GPIO_GPIOX configuration register */\n+union cvmx_inphi_cs4343_gpio_cfg_reg {\n+\tu16 u;\n+\tstruct {\n+u16: 4;\n+\t\t/** Data source for the GPIO output */\n+\t\tu16 output_src_sel : 3;\n+\t\t/** 1 = GPIO output is inverted before being output */\n+\t\tu16 invert_output : 1;\n+\t\t/** 1 = GPIO input is inverted before being processed */\n+\t\tu16 invert_input : 1;\n+\t\t/** 0 = 2.5v/1.8v signalling, 1 = 1.2v signalling */\n+\t\tu16 iovddsel_1v2 : 1;\n+\t\t/**\n+\t\t * 0 = output selected by outen bit\n+\t\t * 1 = output controlled by selected GPIO output source\n+\t\t */\n+\t\tu16 outen_ovr : 1;\n+\t\t/** 0 = GPIO is input only, 1 = GPIO output driver enabled */\n+\t\tu16 outen : 1;\n+u16: 2;\n+\t\tu16 pullup_1k;\t/** 1 = enable 1K pad pullup */\n+\t\tu16 pullup_10k; /** 1 = enable 10K pad pullup */\n+\t} s;\n+};\n+\n+#define CVMX_INPHI_CS4343_GPIO_CFG_OFFSET 0x0\n+\n+/**\n+ * This selects which port the GPIO gets its signals from when configured\n+ * as an output.\n+ */\n+enum cvmx_inphi_cs4343_gpio_output_cfg_port {\n+\tPORT_0_HOST_RX = 0, /** Port pair 0 host RX */\n+\tPORT_0_LINE_RX = 1, /** Port pair 0 line RX */\n+\tPORT_1_HOST_RX = 2, /** Port pair 1 host RX */\n+\tPORT_1_LINE_RX = 3, /** Port pair 1 line RX */\n+\tPORT_3_HOST_RX = 4, /** Port pair 3 host RX */\n+\tPORT_3_LINE_RX = 5, /** Port pair 3 line RX */\n+\tPORT_2_HOST_RX = 6, /** Port pair 2 host RX */\n+\tPORT_2_LINE_RX = 7, /** Port pair 2 line RX */\n+\tCOMMON = 8,\t /** Common */\n+};\n+\n+enum cvmx_inphi_cs4343_gpio_output_cfg_function {\n+\tRX_LOS = 0,\t /** Port - 1 = Receive LOS (from DSP) */\n+\tRX_LOL = 1,\t /** Port - 1 = Receive LOL (inverted from MSEQ) */\n+\tEDC_CONVERGED = 2, /** Port - 1 = EDC converged (from DSP) */\n+\t/** Port - 1 = PRBS checker in sync (inverted from SDS) */\n+\tRX_PRBS_SYNC = 3,\n+\tCOMMON_LOGIC_0 = 0,\t /** Common - Logic 0 */\n+\tCOMMON_GPIO1_INPUT = 1,\t /** Common - GPIO 1 input */\n+\tCOMMON_GPIO2_INPUT = 2,\t /** Common - GPIO 2 input */\n+\tCOMMON_GPIO3_INPUT = 3,\t /** Common - GPIO 3 input */\n+\tCOMMON_GPIO4_INPUT = 4,\t /** Common - GPIO 4 input */\n+\tCOMMON_INTERR_INPUT = 5, /** Common - INTERR input */\n+\t/** Common - Interrupt output from GLOBAL_INT register */\n+\tCOMMON_GLOBAL_INT = 6,\n+\t/** Common - Interrupt output from GPIO_INT register */\n+\tCOMMON_GPIO_INT = 7,\n+\t/** Common - Temp/voltage monitor interrupt */\n+\tCOMMON_MONITOR_INT = 8,\n+\t/** Common - Selected clock output of global clock monitor */\n+\tCOMMON_GBL_CLKMON_CLK = 9,\n+};\n+\n+union cvmx_inphi_cs4343_gpio_output_cfg {\n+\tu16 u;\n+\tstruct {\n+u16: 8;\n+\t\tu16 port : 4;\t /** port */\n+\t\tu16 function : 4; /** function */\n+\t} s;\n+};\n+\n+#define CVMX_INPHI_CS4343_GPIO_OUTPUT_CFG_OFFSET 0x1\n+\n+union cvmx_inphi_cs4343_gpio_drive {\n+\tu16 u;\n+\tstruct {\n+u16: 15;\n+\t\tu16 value : 1; /** output value */\n+\t} s;\n+};\n+\n+#define CVMX_INPHI_CS4343_GPIO_DRIVE_OFFSET 0x2\n+\n+union cvmx_inphi_cs4343_gpio_value {\n+\tu16 u;\n+\tstruct {\n+u16: 15;\n+\t\tu16 value : 1; /** input value (read-only) */\n+\t} s;\n+};\n+\n+#define CVMX_INPHI_CS4343_GPIO_VALUE_OFFSET 0x3\n+\n+union cvmx_inphi_cs4343_gpio_toggle {\n+\tu16 u;\n+\tstruct {\n+\t\t/** Toggle rate in ms, multiply by 2 to get period in ms */\n+\t\tu16 rate : 16;\n+\t} s;\n+};\n+\n+#define CVMX_INPHI_CS4343_GPIO_TOGGLE_OFFSET 0x4\n+\n+union cvmx_inphi_cs4343_gpio_delay {\n+\tu16 u;\n+\tstruct {\n+\t\t/** On delay for GPIO output in ms when enabled */\n+\t\tu16 on_delay : 16;\n+\t} s;\n+};\n+\n+#define CVMX_INPHI_CS4343_GPIO_DELAY_OFFSET 0x5\n+\n+/**\n+ * GPIO flags associated with a GPIO pin (can be combined)\n+ */\n+enum cvmx_gpio_flags {\n+\tCVMX_GPIO_ACTIVE_HIGH = 0, /** Active high (default) */\n+\tCVMX_GPIO_ACTIVE_LOW = 1, /** Active low (inverted) */\n+\tCVMX_GPIO_OPEN_COLLECTOR = 2, /** Output is open-collector */\n+};\n+\n+/** Default timer number to use for outputting a frequency [0..3] */\n+#define CVMX_GPIO_DEFAULT_TIMER 3\n+\n+/** Configuration data for native Octeon GPIO pins */\n+struct cvmx_octeon_gpio_data {\n+\tint cpu_node; /** CPU node for GPIO pin */\n+\tint timer; /** Timer number used when in toggle mode, 0-3 */\n+};\n+\n+struct cvmx_pcf857x_gpio_data {\n+\tunsigned int latch_out;\n+};\n+\n+#define CVMX_INPHI_CS4343_EFUSE_PDF_SKU_REG 0x19f\n+#define CVMX_INPHI_CS4343_SKU_CS4223\t 0x10\n+#define CVMX_INPHI_CS4343_SKU_CS4224\t 0x11\n+#define CVMX_INPHI_CS4343_SKU_CS4343\t 0x12\n+#define CVMX_INPHI_CS4343_SKU_CS4221\t 0x13\n+#define CVMX_INPHI_CS4343_SKU_CS4227\t 0x14\n+#define CVMX_INPHI_CS4343_SKU_CS4341\t 0x16\n+\n+struct cvmx_cs4343_gpio_data {\n+\tint reg_offset; /** Base register address for GPIO */\n+\tenum cvmx_gpio_operation last_op;\n+\tu8 link_port; /** Link port number for link status */\n+\tu16 sku; /** Value from CS4224_EFUSE_PDF_SKU register */\n+\tu8 out_src_sel;\n+\tu8 field_func;\n+\tbool out_en;\n+\tbool is_cs4343; /** True if dual package */\n+\tstruct phy_device *phydev;\n+};\n+\n+struct cvmx_fdt_gpio_info;\n+\n+/** Function called for GPIO operations */\n+typedef int (*cvmx_fdt_gpio_op_func_t)(struct cvmx_fdt_gpio_info *, enum cvmx_gpio_operation);\n+\n+/**\n+ * GPIO descriptor\n+ */\n+struct cvmx_fdt_gpio_info {\n+\tstruct cvmx_fdt_gpio_info *next; /** For list of GPIOs */\n+\tchar name[CVMX_GPIO_NAME_LEN];\t /** Name of GPIO */\n+\tint pin;\t\t\t /** GPIO pin number */\n+\tenum cvmx_gpio_type gpio_type;\t /** Type of GPIO controller */\n+\tint of_offset;\t\t\t /** Offset in device tree */\n+\tint phandle;\n+\tstruct cvmx_fdt_i2c_bus_info *i2c_bus; /** I2C bus descriptor */\n+\tint i2c_addr;\t\t\t /** Address on i2c bus */\n+\tenum cvmx_gpio_flags flags;\t /** Flags associated with pin */\n+\tint num_pins;\t\t\t /** Total number of pins */\n+\tunsigned int latch_out;\t\t /** Latched output for 857x */\n+\t/** Rate in ms between toggle states */\n+\tint toggle_rate;\n+\t/** Pointer to user data for user-defined functions */\n+\tvoid *data;\n+\t/** Function to set, clear, toggle, etc. */\n+\tcvmx_fdt_gpio_op_func_t op_func;\n+\t/* Two values are used to detect the initial case where nothing has\n+\t * been configured. Initially, all of the following will be false\n+\t * which will force the initial state to be properly set.\n+\t */\n+\t/** True if the GPIO pin is currently set, useful for toggle */\n+\tbool is_set;\n+\t/** Set if configured to invert */\n+\tbool invert_set;\n+\t/** Set if input is to be inverted */\n+\tbool invert_input;\n+\t/** Set if direction is configured as output */\n+\tbool dir_out;\n+\t/** Set if direction is configured as input */\n+\tbool dir_in;\n+\t/** Pin is set to toggle periodically */\n+\tbool toggle;\n+\t/** True if LED is used to indicate link status */\n+\tbool link_led;\n+\t/** True if LED is used to indicate rx activity */\n+\tbool rx_act_led;\n+\t/** True if LED is used to indicate tx activity */\n+\tbool tx_act_led;\n+\t/** True if LED is used to indicate networking errors */\n+\tbool error_led;\n+\t/** True if LED can automatically show link */\n+\tbool hw_link;\n+};\n+\n+/** LED datastructure */\n+struct cvmx_fdt_gpio_led {\n+\tstruct cvmx_fdt_gpio_led *next, *prev; /** List of LEDs */\n+\tchar name[CVMX_GPIO_NAME_LEN];\t /** Name */\n+\tstruct cvmx_fdt_gpio_info *gpio; /** GPIO for LED */\n+\tint of_offset;\t\t\t /** Device tree node */\n+\t/** True if active low, note that GPIO contains this info */\n+\tbool active_low;\n+};\n+\n+/**\n+ * Returns the operation function for the GPIO phandle\n+ *\n+ * @param[in]\tfdt_addr\tPointer to FDT\n+ * @param\tphandle\t\tphandle of GPIO entry\n+ *\n+ * @return\tPointer to op function or NULL if not found.\n+ */\n+cvmx_fdt_gpio_op_func_t cvmx_fdt_gpio_get_op_func(const void *fdt_addr, int phandle);\n+\n+/**\n+ * Given a phandle to a GPIO device return the type of GPIO device it is.\n+ *\n+ * @param[in]\tfdt_addr\tAddress of flat device tree\n+ * @param\tphandle\t\tphandle to GPIO\n+ * @param[out]\tsize\t\tNumber of pins (optional, may be NULL)\n+ *\n+ * @return\tType of GPIO device or PIN_ERROR if error\n+ */\n+enum cvmx_gpio_type cvmx_fdt_get_gpio_type(const void *fdt_addr, int phandle, int *size);\n+\n+/**\n+ * Return a GPIO handle given a GPIO phandle of the form <&gpio pin flags>\n+ *\n+ * @param[in]\tfdt_addr\tAddress of flat device tree\n+ * @param\tof_offset\tnode offset of GPIO device\n+ * @param\tprop_name\tname of property\n+ *\n+ * @return\tpointer to GPIO handle or NULL if error\n+ */\n+struct cvmx_fdt_gpio_info *cvmx_fdt_gpio_get_info(const void *fdt_addr, int of_offset,\n+\t\t\t\t\t\t const char *prop_name);\n+\n+/**\n+ * Return a GPIO handle given a GPIO phandle of the form <&gpio pin flags>\n+ *\n+ * @param[in]\tfdt_addr\tAddress of flat device tree\n+ * @param\tof_offset\tnode offset for property\n+ * @param\tprop_name\tname of property\n+ *\n+ * @return\tpointer to GPIO handle or NULL if error\n+ */\n+struct cvmx_fdt_gpio_info *cvmx_fdt_gpio_get_info_phandle(const void *fdt_addr, int of_offset,\n+\t\t\t\t\t\t\t const char *prop_name);\n+\n+/**\n+ * Parses a GPIO entry and fills in the gpio info data structure\n+ *\n+ * @param[in]\tfdt_addr\tAddress of FDT\n+ * @param\tphandle\t\tphandle for GPIO\n+ * @param\tpin\t\tpin number\n+ * @param\tflags\t\tflags set (1 = invert)\n+ * @param[out]\tgpio\t\tGPIO info data structure\n+ *\n+ * @return\t0 for success, -1 on error\n+ */\n+int cvmx_fdt_parse_gpio(const void *fdt_addr, int phandle, int pin, u32 flags,\n+\t\t\tstruct cvmx_fdt_gpio_info *gpio);\n+\n+/**\n+ * @param\tgpio\tGPIO descriptor to assign timer to\n+ * @param\ttimer\tOcteon hardware timer number [0..3]\n+ */\n+void cvmx_fdt_gpio_set_timer(struct cvmx_fdt_gpio_info *gpio, int timer);\n+\n+/**\n+ * Given a GPIO pin descriptor, input the value of that pin\n+ *\n+ * @param\tpin\tGPIO pin descriptor\n+ *\n+ * @return\t0 if low, 1 if high, -1 on error. Note that the input will be\n+ *\t\tinverted if the CVMX_GPIO_ACTIVE_LOW flag bit is set.\n+ */\n+int cvmx_fdt_gpio_get(struct cvmx_fdt_gpio_info *pin);\n+\n+/**\n+ * Sets a GPIO pin given the GPIO descriptor\n+ *\n+ * @param\tgpio\tGPIO pin descriptor\n+ * @param\tvalue\tvalue to set it to, 0 or 1\n+ *\n+ * @return\t0 on success, -1 on error.\n+ *\n+ * NOTE: If the CVMX_GPIO_ACTIVE_LOW flag is set then the output value will be\n+ * inverted.\n+ */\n+int cvmx_fdt_gpio_set(struct cvmx_fdt_gpio_info *gpio, int value);\n+\n+/**\n+ * Sets the blink frequency for a GPIO pin\n+ *\n+ * @param gpio\tGPIO handle\n+ * @param freq\tFrequency in hz [0..500]\n+ */\n+void cvmx_fdt_gpio_set_freq(struct cvmx_fdt_gpio_info *gpio, int freq);\n+\n+/**\n+ * Enables or disables blinking a GPIO pin\n+ *\n+ * @param\tgpio\tGPIO handle\n+ * @param\tblink\tTrue to start blinking, false to stop\n+ *\n+ * @return\t0 for success, -1 on error\n+ * NOTE: Not all GPIO types support blinking.\n+ */\n+int cvmx_fdt_gpio_set_blink(struct cvmx_fdt_gpio_info *gpio, bool blink);\n+\n+/**\n+ * Alternates between link and blink mode\n+ *\n+ * @param\tgpio\tGPIO handle\n+ * @param\tblink\tTrue to start blinking, false to use link status\n+ *\n+ * @return\t0 for success, -1 on error\n+ * NOTE: Not all GPIO types support this.\n+ */\n+int cvmx_fdt_gpio_set_link_blink(struct cvmx_fdt_gpio_info *gpio, bool blink);\n+\n+static inline bool cvmx_fdt_gpio_hw_link_supported(const struct cvmx_fdt_gpio_info *gpio)\n+{\n+\treturn gpio->hw_link;\n+}\n+\n+/**\n+ * Configures a GPIO pin as input or output\n+ *\n+ * @param\tgpio\tGPIO pin to configure\n+ * @param\toutput\tSet to true to make output, false for input\n+ */\n+void cvmx_fdt_gpio_set_output(struct cvmx_fdt_gpio_info *gpio, bool output);\n+\n+/**\n+ * Allocates an LED data structure\n+ * @param[in]\tname\t\tname to assign LED\n+ * @param\tof_offset\tDevice tree offset\n+ * @param\tgpio\t\tGPIO assigned to LED (can be NULL)\n+ * @param\tlast\t\tPrevious LED to build a list\n+ *\n+ * @return\tpointer to LED data structure or NULL if out of memory\n+ */\n+struct cvmx_fdt_gpio_led *cvmx_alloc_led(const char *name, int of_offset,\n+\t\t\t\t\t struct cvmx_fdt_gpio_info *gpio,\n+\t\t\t\t\t struct cvmx_fdt_gpio_led *last);\n+\n+/**\n+ * Parses an LED in the device tree\n+ *\n+ * @param[in]\tfdt_addr\t\tPointer to flat device tree\n+ * @param\tled_of_offset\t\tDevice tree offset of LED\n+ * @param\tgpio\t\t\tGPIO data structure to use (can be NULL)\n+ * @param\tlast\t\t\tPrevious LED if this is a group of LEDs\n+ *\n+ * @return\tPointer to LED data structure or NULL if error\n+ */\n+struct cvmx_fdt_gpio_led *cvmx_fdt_parse_led(const void *fdt_addr, int led_of_offset,\n+\t\t\t\t\t struct cvmx_fdt_gpio_info *gpio,\n+\t\t\t\t\t struct cvmx_fdt_gpio_led *last);\n+\n+#endif /* __CVMX_HELPER_GPIO_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-ilk.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-ilk.h\nnew file mode 100644\nindex 0000000000..29af48e7a1\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-ilk.h\n@@ -0,0 +1,93 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Functions for ILK initialization, configuration,\n+ * and monitoring.\n+ */\n+\n+#ifndef __CVMX_HELPER_ILK_H__\n+#define __CVMX_HELPER_ILK_H__\n+\n+int __cvmx_helper_ilk_enumerate(int interface);\n+\n+/**\n+ * @INTERNAL\n+ * Clear all calendar entries to the xoff state. This\n+ * means no data is sent or received.\n+ *\n+ * @param interface Interface whose calendar are to be initialized.\n+ */\n+void __cvmx_ilk_clear_cal(int interface);\n+\n+/**\n+ * @INTERNAL\n+ * Setup the channel's tx calendar entry.\n+ *\n+ * @param interface Interface channel belongs to\n+ * @param channel Channel whose calendar entry is to be updated\n+ * @param bpid Bpid assigned to the channel\n+ */\n+void __cvmx_ilk_write_tx_cal_entry(int interface, int channel, unsigned char bpid);\n+\n+/**\n+ * @INTERNAL\n+ * Setup the channel's rx calendar entry.\n+ *\n+ * @param interface Interface channel belongs to\n+ * @param channel Channel whose calendar entry is to be updated\n+ * @param pipe PKO assigned to the channel\n+ */\n+void __cvmx_ilk_write_rx_cal_entry(int interface, int channel, unsigned char pipe);\n+\n+/**\n+ * @INTERNAL\n+ * Probe a ILK interface and determine the number of ports\n+ * connected to it. The ILK interface should still be down after\n+ * this call.\n+ *\n+ * @param xiface Interface to probe\n+ *\n+ * @return Number of ports on the interface. Zero to disable.\n+ */\n+int __cvmx_helper_ilk_probe(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Bringup and enable a ILK interface. After this call packet\n+ * I/O should be fully functional. This is called with IPD\n+ * enabled but PKO disabled.\n+ *\n+ * @param xiface Interface to bring up\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_ilk_enable(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Return the link state of an IPD/PKO port as returned by ILK link status.\n+ *\n+ * @param ipd_port IPD/PKO port to query\n+ *\n+ * @return Link state\n+ */\n+cvmx_helper_link_info_t __cvmx_helper_ilk_link_get(int ipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * Configure an IPD/PKO port for the specified link state. This\n+ * function does not influence auto negotiation at the PHY level.\n+ * The passed link state must always match the link state returned\n+ * by cvmx_helper_link_get(). It is normally best to use\n+ * cvmx_helper_link_autoconf() instead.\n+ *\n+ * @param ipd_port IPD/PKO port to configure\n+ * @param link_info The new link state\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_ilk_link_set(int ipd_port, cvmx_helper_link_info_t link_info);\n+\n+void __cvmx_helper_ilk_show_stats(void);\n+#endif\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-ipd.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-ipd.h\nnew file mode 100644\nindex 0000000000..025743d505\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-ipd.h\n@@ -0,0 +1,16 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Helper functions for IPD\n+ */\n+\n+#ifndef __CVMX_HELPER_IPD_H__\n+#define __CVMX_HELPER_IPD_H__\n+\n+void cvmx_helper_ipd_set_wqe_no_ptr_mode(bool mode);\n+void cvmx_helper_ipd_pkt_wqe_le_mode(bool mode);\n+int __cvmx_helper_ipd_global_setup(void);\n+int __cvmx_helper_ipd_setup_interface(int interface);\n+\n+#endif /* __CVMX_HELPER_PKI_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-jtag.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-jtag.h\nnew file mode 100644\nindex 0000000000..fa379eaf55\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-jtag.h\n@@ -0,0 +1,84 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Helper utilities for qlm_jtag.\n+ */\n+\n+#ifndef __CVMX_HELPER_JTAG_H__\n+#define __CVMX_HELPER_JTAG_H__\n+\n+/**\n+ * The JTAG chain for CN52XX and CN56XX is 4 * 268 bits long, or 1072.\n+ * CN5XXX full chain shift is:\n+ * new data => lane 3 => lane 2 => lane 1 => lane 0 => data out\n+ * The JTAG chain for CN63XX is 4 * 300 bits long, or 1200.\n+ * The JTAG chain for CN68XX is 4 * 304 bits long, or 1216.\n+ * The JTAG chain for CN66XX/CN61XX/CNF71XX is 4 * 304 bits long, or 1216.\n+ * CN6XXX full chain shift is:\n+ * new data => lane 0 => lane 1 => lane 2 => lane 3 => data out\n+ * Shift LSB first, get LSB out\n+ */\n+extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn63xx[];\n+extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn66xx[];\n+extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn68xx[];\n+\n+#define CVMX_QLM_JTAG_UINT32 40\n+\n+typedef u32 qlm_jtag_uint32_t[CVMX_QLM_JTAG_UINT32 * 8];\n+\n+/**\n+ * Initialize the internal QLM JTAG logic to allow programming\n+ * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.\n+ * These functions should only be used at the direction of Cavium\n+ * Networks. Programming incorrect values into the JTAG chain\n+ * can cause chip damage.\n+ */\n+void cvmx_helper_qlm_jtag_init(void);\n+\n+/**\n+ * Write up to 32bits into the QLM jtag chain. Bits are shifted\n+ * into the MSB and out the LSB, so you should shift in the low\n+ * order bits followed by the high order bits. The JTAG chain for\n+ * CN52XX and CN56XX is 4 * 268 bits long, or 1072. The JTAG chain\n+ * for CN63XX is 4 * 300 bits long, or 1200.\n+ *\n+ * @param qlm QLM to shift value into\n+ * @param bits Number of bits to shift in (1-32).\n+ * @param data Data to shift in. Bit 0 enters the chain first, followed by\n+ * bit 1, etc.\n+ *\n+ * @return The low order bits of the JTAG chain that shifted out of the\n+ * circle.\n+ */\n+u32 cvmx_helper_qlm_jtag_shift(int qlm, int bits, u32 data);\n+\n+/**\n+ * Shift long sequences of zeros into the QLM JTAG chain. It is\n+ * common to need to shift more than 32 bits of zeros into the\n+ * chain. This function is a convience wrapper around\n+ * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of\n+ * zeros at a time.\n+ *\n+ * @param qlm QLM to shift zeros into\n+ * @param bits\n+ */\n+void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits);\n+\n+/**\n+ * Program the QLM JTAG chain into all lanes of the QLM. You must\n+ * have already shifted in the proper number of bits into the\n+ * JTAG chain. Updating invalid values can possibly cause chip damage.\n+ *\n+ * @param qlm QLM to program\n+ */\n+void cvmx_helper_qlm_jtag_update(int qlm);\n+\n+/**\n+ * Load the QLM JTAG chain with data from all lanes of the QLM.\n+ *\n+ * @param qlm QLM to program\n+ */\n+void cvmx_helper_qlm_jtag_capture(int qlm);\n+\n+#endif /* __CVMX_HELPER_JTAG_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-loop.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-loop.h\nnew file mode 100644\nindex 0000000000..defd95551a\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-loop.h\n@@ -0,0 +1,37 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Functions for LOOP initialization, configuration,\n+ * and monitoring.\n+ */\n+\n+#ifndef __CVMX_HELPER_LOOP_H__\n+#define __CVMX_HELPER_LOOP_H__\n+\n+/**\n+ * @INTERNAL\n+ * Probe a LOOP interface and determine the number of ports\n+ * connected to it. The LOOP interface should still be down after\n+ * this call.\n+ *\n+ * @param xiface Interface to probe\n+ *\n+ * @return Number of ports on the interface. Zero to disable.\n+ */\n+int __cvmx_helper_loop_probe(int xiface);\n+int __cvmx_helper_loop_enumerate(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Bringup and enable a LOOP interface. After this call packet\n+ * I/O should be fully functional. This is called with IPD\n+ * enabled but PKO disabled.\n+ *\n+ * @param xiface Interface to bring up\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_loop_enable(int xiface);\n+\n+#endif\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-npi.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-npi.h\nnew file mode 100644\nindex 0000000000..6a600a017c\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-npi.h\n@@ -0,0 +1,42 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Functions for NPI initialization, configuration,\n+ * and monitoring.\n+ */\n+\n+#ifndef __CVMX_HELPER_NPI_H__\n+#define __CVMX_HELPER_NPI_H__\n+\n+/**\n+ * @INTERNAL\n+ * Probe a NPI interface and determine the number of ports\n+ * connected to it. The NPI interface should still be down after\n+ * this call.\n+ *\n+ * @param interface Interface to probe\n+ *\n+ * @return Number of ports on the interface. Zero to disable.\n+ */\n+int __cvmx_helper_npi_probe(int interface);\n+\n+/**\n+ * @INTERNAL\n+ * Bringup and enable a NPI interface. After this call packet\n+ * I/O should be fully functional. This is called with IPD\n+ * enabled but PKO disabled.\n+ *\n+ * @param xiface Interface to bring up\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_npi_enable(int xiface);\n+\n+/**\n+ * Sets the number of pipe used by SLI packet output in the variable,\n+ * which then later used for setting it up in HW\n+ */\n+void cvmx_npi_config_set_num_pipes(int num_pipes);\n+\n+#endif\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h\nnew file mode 100644\nindex 0000000000..f5933f24fa\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h\n@@ -0,0 +1,319 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Helper functions for PKI\n+ */\n+\n+#ifndef __CVMX_HELPER_PKI_H__\n+#define __CVMX_HELPER_PKI_H__\n+\n+#include \"cvmx-pki.h\"\n+\n+/* Modify this if more than 8 ilk channels need to be supported */\n+#define CVMX_MAX_PORT_PER_INTERFACE 64\n+#define CVMX_MAX_QOS_PRIORITY\t 64\n+#define CVMX_PKI_FIND_AVAILABLE_RSRC (-1)\n+\n+struct cvmx_pki_qos_schd {\n+\tcvmx_fpa3_gaura_t _aura;\n+\tcvmx_fpa3_pool_t _pool;\n+\tbool pool_per_qos;\n+\tint pool_num;\n+\tchar *pool_name;\n+\tu64 pool_buff_size;\n+\tu64 pool_max_buff;\n+\tbool aura_per_qos;\n+\tint aura_num;\n+\tchar *aura_name;\n+\tu64 aura_buff_cnt;\n+\tbool sso_grp_per_qos;\n+\tint sso_grp;\n+\tu16 port_add;\n+\tint qpg_base;\n+};\n+\n+struct cvmx_pki_prt_schd {\n+\tcvmx_fpa3_pool_t _pool;\n+\tcvmx_fpa3_gaura_t _aura;\n+\tbool cfg_port;\n+\tint style;\n+\tbool pool_per_prt;\n+\tint pool_num;\n+\tchar *pool_name;\n+\tu64 pool_buff_size;\n+\tu64 pool_max_buff;\n+\tbool aura_per_prt;\n+\tint aura_num;\n+\tchar *aura_name;\n+\tu64 aura_buff_cnt;\n+\tbool sso_grp_per_prt;\n+\tint sso_grp;\n+\tenum cvmx_pki_qpg_qos qpg_qos;\n+\tint qpg_base;\n+\tstruct cvmx_pki_qos_schd qos_s[CVMX_MAX_QOS_PRIORITY];\n+};\n+\n+struct cvmx_pki_intf_schd {\n+\tcvmx_fpa3_pool_t _pool;\n+\tcvmx_fpa3_gaura_t _aura;\n+\tbool style_per_intf;\n+\tint style;\n+\tbool pool_per_intf;\n+\tint pool_num;\n+\tchar *pool_name;\n+\tu64 pool_buff_size;\n+\tu64 pool_max_buff;\n+\tbool aura_per_intf;\n+\tint aura_num;\n+\tchar *aura_name;\n+\tu64 aura_buff_cnt;\n+\tbool sso_grp_per_intf;\n+\tint sso_grp;\n+\tbool qos_share_aura;\n+\tbool qos_share_grp;\n+\tint qpg_base;\n+\tstruct cvmx_pki_prt_schd prt_s[CVMX_MAX_PORT_PER_INTERFACE];\n+};\n+\n+struct cvmx_pki_global_schd {\n+\tbool setup_pool;\n+\tint pool_num;\n+\tchar *pool_name;\n+\tu64 pool_buff_size;\n+\tu64 pool_max_buff;\n+\tbool setup_aura;\n+\tint aura_num;\n+\tchar *aura_name;\n+\tu64 aura_buff_cnt;\n+\tbool setup_sso_grp;\n+\tint sso_grp;\n+\tcvmx_fpa3_pool_t _pool;\n+\tcvmx_fpa3_gaura_t _aura;\n+};\n+\n+struct cvmx_pki_legacy_qos_watcher {\n+\tbool configured;\n+\tenum cvmx_pki_term field;\n+\tu32 data;\n+\tu32 data_mask;\n+\tu8 advance;\n+\tu8 sso_grp;\n+};\n+\n+extern bool cvmx_pki_dflt_init[CVMX_MAX_NODES];\n+\n+extern struct cvmx_pki_pool_config pki_dflt_pool[CVMX_MAX_NODES];\n+extern struct cvmx_pki_aura_config pki_dflt_aura[CVMX_MAX_NODES];\n+extern struct cvmx_pki_style_config pki_dflt_style[CVMX_MAX_NODES];\n+extern struct cvmx_pki_pkind_config pki_dflt_pkind[CVMX_MAX_NODES];\n+extern u64 pkind_style_map[CVMX_MAX_NODES][CVMX_PKI_NUM_PKIND];\n+extern struct cvmx_pki_sso_grp_config pki_dflt_sso_grp[CVMX_MAX_NODES];\n+extern struct cvmx_pki_legacy_qos_watcher qos_watcher[8];\n+\n+/**\n+ * This function Enabled the PKI hardware to\n+ * start accepting/processing packets.\n+ * @param node node number\n+ */\n+void cvmx_helper_pki_enable(int node);\n+\n+/**\n+ * This function frees up PKI resources consumed by that port.\n+ * This function should only be called if port resources\n+ * (fpa pools aura, style qpg entry pcam entry etc.) are not shared\n+ * @param xipd_port ipd port number for which resources need to\n+ * be freed.\n+ */\n+int cvmx_helper_pki_port_shutdown(int xipd_port);\n+\n+/**\n+ * This function shuts down complete PKI hardware\n+ * and software resources.\n+ * @param node node number where PKI needs to shutdown.\n+ */\n+void cvmx_helper_pki_shutdown(int node);\n+\n+/**\n+ * This function calculates how mant qpf entries will be needed for\n+ * a particular QOS.\n+ * @param qpg_qos qos value for which entries need to be calculated.\n+ */\n+int cvmx_helper_pki_get_num_qpg_entry(enum cvmx_pki_qpg_qos qpg_qos);\n+\n+/**\n+ * This function setups the qos table by allocating qpg entry and writing\n+ * the provided parameters to that entry (offset).\n+ * @param node node number.\n+ * @param qpg_cfg pointer to struct containing qpg configuration\n+ */\n+int cvmx_helper_pki_set_qpg_entry(int node, struct cvmx_pki_qpg_config *qpg_cfg);\n+\n+/**\n+ * This function sets up aura QOS for RED, backpressure and tail-drop.\n+ *\n+ * @param node node number.\n+ * @param aura aura to configure.\n+ * @param ena_red enable RED based on [DROP] and [PASS] levels\n+ *\t\t\t1: enable 0:disable\n+ * @param pass_thresh pass threshold for RED.\n+ * @param drop_thresh drop threshold for RED\n+ * @param ena_bp enable backpressure based on [BP] level.\n+ *\t\t\t1:enable 0:disable\n+ * @param bp_thresh backpressure threshold.\n+ * @param ena_drop enable tail drop.\n+ *\t\t\t1:enable 0:disable\n+ * @return Zero on success. Negative on failure\n+ */\n+int cvmx_helper_setup_aura_qos(int node, int aura, bool ena_red, bool ena_drop, u64 pass_thresh,\n+\t\t\t u64 drop_thresh, bool ena_bp, u64 bp_thresh);\n+\n+/**\n+ * This function maps specified bpid to all the auras from which it can receive bp and\n+ * then maps that bpid to all the channels, that bpid can asserrt bp on.\n+ *\n+ * @param node node number.\n+ * @param aura aura number which will back pressure specified bpid.\n+ * @param bpid bpid to map.\n+ * @param chl_map array of channels to map to that bpid.\n+ * @param chl_cnt\tnumber of channel/ports to map to that bpid.\n+ * @return Zero on success. Negative on failure\n+ */\n+int cvmx_helper_pki_map_aura_chl_bpid(int node, u16 aura, u16 bpid, u16 chl_map[], u16 chl_cnt);\n+\n+/**\n+ * This function sets up the global pool, aura and sso group\n+ * resources which application can use between any interfaces\n+ * and ports.\n+ * @param node node number\n+ * @param gblsch pointer to struct containing global\n+ * scheduling parameters.\n+ */\n+int cvmx_helper_pki_set_gbl_schd(int node, struct cvmx_pki_global_schd *gblsch);\n+\n+/**\n+ * This function sets up scheduling parameters (pool, aura, sso group etc)\n+ * of an ipd port.\n+ * @param xipd_port ipd port number\n+ * @param prtsch pointer to struct containing port's\n+ * scheduling parameters.\n+ */\n+int cvmx_helper_pki_init_port(int xipd_port, struct cvmx_pki_prt_schd *prtsch);\n+\n+/**\n+ * This function sets up scheduling parameters (pool, aura, sso group etc)\n+ * of an interface (all ports/channels on that interface).\n+ * @param xiface interface number with node.\n+ * @param intfsch pointer to struct containing interface\n+ * scheduling parameters.\n+ * @param gblsch pointer to struct containing global scheduling parameters\n+ * (can be NULL if not used)\n+ */\n+int cvmx_helper_pki_init_interface(const int xiface, struct cvmx_pki_intf_schd *intfsch,\n+\t\t\t\t struct cvmx_pki_global_schd *gblsch);\n+/**\n+ * This function gets all the PKI parameters related to that\n+ * particular port from hardware.\n+ * @param xipd_port ipd port number to get parameter of\n+ * @param port_cfg pointer to structure where to store read parameters\n+ */\n+void cvmx_pki_get_port_config(int xipd_port, struct cvmx_pki_port_config *port_cfg);\n+\n+/**\n+ * This function sets all the PKI parameters related to that\n+ * particular port in hardware.\n+ * @param xipd_port ipd port number to get parameter of\n+ * @param port_cfg pointer to structure containing port parameters\n+ */\n+void cvmx_pki_set_port_config(int xipd_port, struct cvmx_pki_port_config *port_cfg);\n+\n+/**\n+ * This function displays all the PKI parameters related to that\n+ * particular port.\n+ * @param xipd_port ipd port number to display parameter of\n+ */\n+void cvmx_pki_show_port_config(int xipd_port);\n+\n+/**\n+ * Modifies maximum frame length to check.\n+ * It modifies the global frame length set used by this port, any other\n+ * port using the same set will get affected too.\n+ * @param xipd_port\tipd port for which to modify max len.\n+ * @param max_size\tmaximum frame length\n+ */\n+void cvmx_pki_set_max_frm_len(int xipd_port, u32 max_size);\n+\n+/**\n+ * This function sets up all the ports of particular interface\n+ * for chosen fcs mode. (only use for backward compatibility).\n+ * New application can control it via init_interface calls.\n+ * @param node node number.\n+ * @param interface interface number.\n+ * @param nports number of ports\n+ * @param has_fcs 1 -- enable fcs check and fcs strip.\n+ * 0 -- disable fcs check.\n+ */\n+void cvmx_helper_pki_set_fcs_op(int node, int interface, int nports, int has_fcs);\n+\n+/**\n+ * This function sets the wqe buffer mode of all ports. First packet data buffer can reside\n+ * either in same buffer as wqe OR it can go in separate buffer. If used the later mode,\n+ * make sure software allocate enough buffers to now have wqe separate from packet data.\n+ * @param node\t node number.\n+ * @param pkt_outside_wqe\t0 = The packet link pointer will be at word [FIRST_SKIP]\n+ *\t\t\t\t immediately followed by packet data, in the same buffer\n+ *\t\t\t\t as the work queue entry.\n+ *\t\t\t\t1 = The packet link pointer will be at word [FIRST_SKIP] in a new\n+ *\t\t\t\t buffer separate from the work queue entry. Words following the\n+ *\t\t\t\t WQE in the same cache line will be zeroed, other lines in the\n+ *\t\t\t\t buffer will not be modified and will retain stale data (from the\n+ *\t\t\t\t buffer’s previous use). This setting may decrease the peak PKI\n+ *\t\t\t\t performance by up to half on small packets.\n+ */\n+void cvmx_helper_pki_set_wqe_mode(int node, bool pkt_outside_wqe);\n+\n+/**\n+ * This function sets the Packet mode of all ports and styles to little-endian.\n+ * It Changes write operations of packet data to L2C to\n+ * be in little-endian. Does not change the WQE header format, which is\n+ * properly endian neutral.\n+ * @param node\t node number.\n+ */\n+void cvmx_helper_pki_set_little_endian(int node);\n+\n+void cvmx_helper_pki_set_dflt_pool(int node, int pool, int buffer_size, int buffer_count);\n+void cvmx_helper_pki_set_dflt_aura(int node, int aura, int pool, int buffer_count);\n+void cvmx_helper_pki_set_dflt_pool_buffer(int node, int buffer_count);\n+\n+void cvmx_helper_pki_set_dflt_aura_buffer(int node, int buffer_count);\n+\n+void cvmx_helper_pki_set_dflt_pkind_map(int node, int pkind, int style);\n+\n+void cvmx_helper_pki_get_dflt_style(int node, struct cvmx_pki_style_config *style_cfg);\n+void cvmx_helper_pki_set_dflt_style(int node, struct cvmx_pki_style_config *style_cfg);\n+\n+void cvmx_helper_pki_get_dflt_qpg(int node, struct cvmx_pki_qpg_config *qpg_cfg);\n+void cvmx_helper_pki_set_dflt_qpg(int node, struct cvmx_pki_qpg_config *qpg_cfg);\n+\n+void cvmx_helper_pki_no_dflt_init(int node);\n+\n+void cvmx_helper_pki_set_dflt_bp_en(int node, bool bp_en);\n+\n+void cvmx_pki_dump_wqe(const cvmx_wqe_78xx_t *wqp);\n+\n+int __cvmx_helper_pki_port_setup(int node, int xipd_port);\n+\n+int __cvmx_helper_pki_global_setup(int node);\n+void cvmx_helper_pki_show_port_config(int xipd_port);\n+\n+int __cvmx_helper_pki_install_dflt_vlan(int node);\n+void __cvmx_helper_pki_set_dflt_ltype_map(int node);\n+int cvmx_helper_pki_route_dmac(int node, int style, u64 mac_addr, u64 mac_addr_mask,\n+\t\t\t int final_style);\n+int cvmx_pki_clone_style(int node, int style, u64 cluster_mask);\n+void cvmx_helper_pki_modify_prtgrp(int xipd_port, int grp_ok, int grp_bad);\n+int cvmx_helper_pki_route_prt_dmac(int xipd_port, u64 mac_addr, u64 mac_addr_mask, int grp);\n+\n+void cvmx_helper_pki_errata(int node);\n+\n+#endif /* __CVMX_HELPER_PKI_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-pko.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-pko.h\nnew file mode 100644\nindex 0000000000..806102df22\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-pko.h\n@@ -0,0 +1,51 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * PKO helper, configuration API\n+ */\n+\n+#ifndef __CVMX_HELPER_PKO_H__\n+#define __CVMX_HELPER_PKO_H__\n+\n+/* CSR typedefs have been moved to cvmx-pko-defs.h */\n+\n+/**\n+ * cvmx_override_pko_queue_priority(int ipd_port, u64\n+ * priorities[16]) is a function pointer. It is meant to allow\n+ * customization of the PKO queue priorities based on the port\n+ * number. Users should set this pointer to a function before\n+ * calling any cvmx-helper operations.\n+ */\n+void (*cvmx_override_pko_queue_priority)(int ipd_port, u8 *priorities);\n+\n+/**\n+ * Gets the fpa pool number of pko pool\n+ */\n+s64 cvmx_fpa_get_pko_pool(void);\n+\n+/**\n+ * Gets the buffer size of pko pool\n+ */\n+u64 cvmx_fpa_get_pko_pool_block_size(void);\n+\n+/**\n+ * Gets the buffer size of pko pool\n+ */\n+u64 cvmx_fpa_get_pko_pool_buffer_count(void);\n+\n+int cvmx_helper_pko_init(void);\n+\n+/*\n+ * This function is a no-op\n+ * included here for backwards compatibility only.\n+ */\n+static inline int cvmx_pko_initialize_local(void)\n+{\n+\treturn 0;\n+}\n+\n+int __cvmx_helper_pko_drain(void);\n+int __cvmx_helper_interface_setup_pko(int interface);\n+\n+#endif /* __CVMX_HELPER_PKO_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-pko3.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-pko3.h\nnew file mode 100644\nindex 0000000000..ca8d848bd1\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-pko3.h\n@@ -0,0 +1,76 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#ifndef __CVMX_HELPER_PKO3_H__\n+#define __CVMX_HELPER_PKO3_H__\n+\n+/*\n+ * Initialize PKO3 unit on the current node.\n+ *\n+ * Covers the common hardware, memory and global configuration.\n+ * Per-interface initialization is performed separately.\n+ *\n+ * @return 0 on success.\n+ *\n+ */\n+int cvmx_helper_pko3_init_global(unsigned int node);\n+int __cvmx_helper_pko3_init_global(unsigned int node, u16 gaura);\n+\n+/**\n+ * Initialize a simple interface with a a given number of\n+ * fair or prioritized queues.\n+ * This function will assign one channel per sub-interface.\n+ */\n+int __cvmx_pko3_config_gen_interface(int xiface, u8 subif, u8 num_queues, bool prioritized);\n+\n+/*\n+ * Configure and initialize PKO3 for an interface\n+ *\n+ * @param interface is the interface number to configure\n+ * @return 0 on success.\n+ *\n+ */\n+int cvmx_helper_pko3_init_interface(int xiface);\n+int __cvmx_pko3_helper_dqs_activate(int xiface, int index, bool min_pad);\n+\n+/**\n+ * Uninitialize PKO3 interface\n+ *\n+ * Release all resources held by PKO for an interface.\n+ * The shutdown code is the same for all supported interfaces.\n+ */\n+int cvmx_helper_pko3_shut_interface(int xiface);\n+\n+/**\n+ * Shutdown PKO3\n+ *\n+ * Should be called after all interfaces have been shut down on the PKO3.\n+ *\n+ * Disables the PKO, frees all its buffers.\n+ */\n+int cvmx_helper_pko3_shutdown(unsigned int node);\n+\n+/**\n+ * Show integrated PKO configuration.\n+ *\n+ * @param node\t node number\n+ */\n+int cvmx_helper_pko3_config_dump(unsigned int node);\n+\n+/**\n+ * Show integrated PKO statistics.\n+ *\n+ * @param node\t node number\n+ */\n+int cvmx_helper_pko3_stats_dump(unsigned int node);\n+\n+/**\n+ * Clear PKO statistics.\n+ *\n+ * @param node\t node number\n+ */\n+void cvmx_helper_pko3_stats_clear(unsigned int node);\n+\n+#endif /* __CVMX_HELPER_PKO3_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-rgmii.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-rgmii.h\nnew file mode 100644\nindex 0000000000..2a206a8827\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-rgmii.h\n@@ -0,0 +1,99 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Functions for RGMII/GMII/MII initialization, configuration,\n+ * and monitoring.\n+ */\n+\n+#ifndef __CVMX_HELPER_RGMII_H__\n+#define __CVMX_HELPER_RGMII_H__\n+\n+/**\n+ * @INTERNAL\n+ * Probe RGMII ports and determine the number present\n+ *\n+ * @param xiface Interface to probe\n+ *\n+ * @return Number of RGMII/GMII/MII ports (0-4).\n+ */\n+int __cvmx_helper_rgmii_probe(int xiface);\n+\n+/**\n+ * Put an RGMII interface in loopback mode. Internal packets sent\n+ * out will be received back again on the same port. Externally\n+ * received packets will echo back out.\n+ *\n+ * @param port IPD port number to loop.\n+ */\n+void cvmx_helper_rgmii_internal_loopback(int port);\n+\n+/**\n+ * @INTERNAL\n+ * Configure all of the ASX, GMX, and PKO regsiters required\n+ * to get RGMII to function on the supplied interface.\n+ *\n+ * @param xiface PKO Interface to configure (0 or 1)\n+ *\n+ * @return Zero on success\n+ */\n+int __cvmx_helper_rgmii_enable(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Return the link state of an IPD/PKO port as returned by\n+ * auto negotiation. The result of this function may not match\n+ * Octeon's link config if auto negotiation has changed since\n+ * the last call to cvmx_helper_link_set().\n+ *\n+ * @param ipd_port IPD/PKO port to query\n+ *\n+ * @return Link state\n+ */\n+cvmx_helper_link_info_t __cvmx_helper_gmii_link_get(int ipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * Return the link state of an IPD/PKO port as returned by\n+ * auto negotiation. The result of this function may not match\n+ * Octeon's link config if auto negotiation has changed since\n+ * the last call to cvmx_helper_link_set().\n+ *\n+ * @param ipd_port IPD/PKO port to query\n+ *\n+ * @return Link state\n+ */\n+cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * Configure an IPD/PKO port for the specified link state. This\n+ * function does not influence auto negotiation at the PHY level.\n+ * The passed link state must always match the link state returned\n+ * by cvmx_helper_link_get(). It is normally best to use\n+ * cvmx_helper_link_autoconf() instead.\n+ *\n+ * @param ipd_port IPD/PKO port to configure\n+ * @param link_info The new link state\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_rgmii_link_set(int ipd_port, cvmx_helper_link_info_t link_info);\n+\n+/**\n+ * @INTERNAL\n+ * Configure a port for internal and/or external loopback. Internal loopback\n+ * causes packets sent by the port to be received by Octeon. External loopback\n+ * causes packets received from the wire to sent out again.\n+ *\n+ * @param ipd_port IPD/PKO port to loopback.\n+ * @param enable_internal\n+ * Non zero if you want internal loopback\n+ * @param enable_external\n+ * Non zero if you want external loopback\n+ *\n+ * @return Zero on success, negative on failure.\n+ */\n+int __cvmx_helper_rgmii_configure_loopback(int ipd_port, int enable_internal, int enable_external);\n+\n+#endif\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-sfp.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-sfp.h\nnew file mode 100644\nindex 0000000000..6fe55093b2\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-sfp.h\n@@ -0,0 +1,437 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Helper functions to abstract SFP and QSFP connectors\n+ */\n+\n+#ifndef __CVMX_HELPER_SFP_H__\n+#define __CVMX_HELPER_SFP_H__\n+\n+/**\n+ * Maximum size for the SFP EEPROM. Currently only 96 bytes are used.\n+ */\n+#define CVMX_SFP_MAX_EEPROM_SIZE 0x100\n+\n+/**\n+ * Default address of sfp EEPROM\n+ */\n+#define CVMX_SFP_DEFAULT_I2C_ADDR 0x50\n+\n+/**\n+ * Default address of SFP diagnostics chip\n+ */\n+#define CVMX_SFP_DEFAULT_DIAG_I2C_ADDR 0x51\n+\n+struct cvmx_fdt_sfp_info;\n+struct cvmx_fdt_gpio_info;\n+/**\n+ * Connector type for module, usually we only see SFP and QSFPP\n+ */\n+enum cvmx_phy_sfp_conn_type {\n+\tCVMX_SFP_CONN_GBIC = 0x01,\t /** GBIC */\n+\tCVMX_SFP_CONN_SFP = 0x03,\t /** SFP/SFP+/SFP28 */\n+\tCVMX_SFP_CONN_QSFP = 0x0C,\t /** 1G QSFP (obsolete) */\n+\tCVMX_SFP_CONN_QSFPP = 0x0D,\t /** QSFP+ or later */\n+\tCVMX_SFP_CONN_QSFP28 = 0x11,\t /** QSFP28 (100Gbps) */\n+\tCVMX_SFP_CONN_MICRO_QSFP = 0x17, /** Micro QSFP */\n+\tCVMX_SFP_CONN_QSFP_DD = 0x18,\t /** QSFP-DD Double Density 8X */\n+\tCVMX_SFP_CONN_SFP_DD = 0x1A,\t /** SFP-DD Double Density 2X */\n+};\n+\n+/**\n+ * module type plugged into a SFP/SFP+/QSFP+ port\n+ */\n+enum cvmx_phy_sfp_mod_type {\n+\tCVMX_SFP_MOD_UNKNOWN = 0, /** Unknown or unspecified */\n+\t/** Fiber optic module (LC connector) */\n+\tCVMX_SFP_MOD_OPTICAL_LC = 0x7,\n+\t/** Multiple optical */\n+\tCVMX_SFP_MOD_MULTIPLE_OPTICAL = 0x9,\n+\t/** Fiber optic module (pigtail, no connector) */\n+\tCVMX_SFP_MOD_OPTICAL_PIGTAIL = 0xB,\n+\tCVMX_SFP_MOD_COPPER_PIGTAIL = 0x21, /** copper module */\n+\tCVMX_SFP_MOD_RJ45 = 0x22,\t /** RJ45 (i.e. 10GBase-T) */\n+\t/** No separable connector (SFP28/copper) */\n+\tCVMX_SFP_MOD_NO_SEP_CONN = 0x23,\n+\t/** MXC 2X16 */\n+\tCVMX_SFP_MOD_MXC_2X16 = 0x24,\n+\t/** CS optical connector */\n+\tCVMX_SFP_MOD_CS_OPTICAL = 0x25,\n+\t/** Mini CS optical connector */\n+\tCVMX_SFP_MOD_MINI_CS_OPTICAL = 0x26,\n+\t/** Unknown/other module type */\n+\tCVMX_SFP_MOD_OTHER\n+};\n+\n+/** Peak rate supported by SFP cable */\n+enum cvmx_phy_sfp_rate {\n+\tCVMX_SFP_RATE_UNKNOWN, /** Unknown rate */\n+\tCVMX_SFP_RATE_1G, /** 1Gbps */\n+\tCVMX_SFP_RATE_10G, /** 10Gbps */\n+\tCVMX_SFP_RATE_25G, /** 25Gbps */\n+\tCVMX_SFP_RATE_40G, /** 40Gbps */\n+\tCVMX_SFP_RATE_100G /** 100Gbps */\n+};\n+\n+/**\n+ * Cable compliance specification\n+ * See table 4-4 from SFF-8024 for the extended specification compliance codes\n+ */\n+enum cvmx_phy_sfp_cable_ext_compliance {\n+\tCVMX_SFP_CABLE_UNSPEC = 0,\n+\tCVMX_SFP_CABLE_100G_25GAUI_C2M_AOC_HIGH_BER = 0x01, /** Active optical cable */\n+\tCVMX_SFP_CABLE_100G_SR4_25G_SR = 0x2,\n+\tCVMX_SFP_CABLE_100G_LR4_25G_LR = 0x3,\n+\tCVMX_SFP_CABLE_100G_ER4_25G_ER = 0x4,\n+\tCVMX_SFP_CABLE_100G_SR10 = 0x5,\n+\tCVMX_SFP_CABLE_100G_CWDM4_MSA = 0x6,\n+\tCVMX_SFP_CABLE_100G_PSM4 = 0x7,\n+\tCVMX_SFP_CABLE_100G_25GAUI_C2M_ACC_HIGH_BER = 0x8,\n+\tCVMX_SFP_CABLE_100G_CWDM4 = 0x9,\n+\tCVMX_SFP_CABLE_100G_CR4_25G_CR_CA_L = 0xB,\n+\tCVMX_SFP_CABLE_25G_CR_CA_S = 0xC,\n+\tCVMX_SFP_CABLE_25G_CR_CA_N = 0xD,\n+\tCVMX_SFP_CABLE_40G_ER4 = 0x10,\n+\tCVMX_SFP_CABLE_4X10G_SR = 0x11,\n+\tCVMX_SFP_CABLE_40G_PSM4 = 0x12,\n+\tCVMX_SFP_CABLE_G959_1_P1I1_2D1 = 0x13,\n+\tCVMX_SFP_CABLE_G959_1_P1S1_2D2 = 0x14,\n+\tCVMX_SFP_CABLE_G959_1_P1L1_2D2 = 0x15,\n+\tCVMX_SFP_CABLE_10GBASE_T = 0x16,\n+\tCVMX_SFP_CABLE_100G_CLR4 = 0x17,\n+\tCVMX_SFP_CABLE_100G_25GAUI_C2M_AOC_LOW_BER = 0x18,\n+\tCVMX_SFP_CABLE_100G_25GAUI_C2M_ACC_LOW_BER = 0x19,\n+\tCVMX_SFP_CABLE_100G_2_LAMBDA_DWDM = 0x1a,\n+\tCVMX_SFP_CABLE_100G_1550NM_WDM = 0x1b,\n+\tCVMX_SFP_CABLE_10GBASE_T_SR = 0x1c,\n+\tCVMX_SFP_CABLE_5GBASE_T = 0x1d,\n+\tCVMX_SFP_CABLE_2_5GBASE_T = 0x1e,\n+\tCVMX_SFP_CABLE_40G_SWDM4 = 0x1f,\n+\tCVMX_SFP_CABLE_100G_SWDM4 = 0x20,\n+\tCVMX_SFP_CABLE_100G_PAM4_BIDI = 0x21,\n+\tCVMX_SFP_CABLE_100G_4WDM_10_FEC_HOST = 0x22,\n+\tCVMX_SFP_CABLE_100G_4WDM_20_FEC_HOST = 0x23,\n+\tCVMX_SFP_CABLE_100G_4WDM_40_FEC_HOST = 0x24,\n+\tCVMX_SFP_CABLE_100GBASE_DR_CAUI4_NO_FEC = 0x25,\n+\tCVMX_SFP_CABLE_100G_FR_CAUI4_NO_FEC = 0x26,\n+\tCVMX_SFP_CABLE_100G_LR_CAUI4_NO_FEC = 0x27,\n+\tCVMX_SFP_CABLE_ACTIVE_COPPER_50_100_200GAUI_LOW_BER = 0x30,\n+\tCVMX_SFP_CABLE_ACTIVE_OPTICAL_50_100_200GAUI_LOW_BER = 0x31,\n+\tCVMX_SFP_CABLE_ACTIVE_COPPER_50_100_200GAUI_HI_BER = 0x32,\n+\tCVMX_SFP_CABLE_ACTIVE_OPTICAL_50_100_200GAUI_HI_BER = 0x33,\n+\tCVMX_SFP_CABLE_50_100_200G_CR = 0x40,\n+\tCVMX_SFP_CABLE_50_100_200G_SR = 0x41,\n+\tCVMX_SFP_CABLE_50GBASE_FR_200GBASE_DR4 = 0x42,\n+\tCVMX_SFP_CABLE_200GBASE_FR4 = 0x43,\n+\tCVMX_SFP_CABLE_200G_1550NM_PSM4 = 0x44,\n+\tCVMX_SFP_CABLE_50GBASE_LR = 0x45,\n+\tCVMX_SFP_CABLE_200GBASE_LR4 = 0x46,\n+\tCVMX_SFP_CABLE_64GFC_EA = 0x50,\n+\tCVMX_SFP_CABLE_64GFC_SW = 0x51,\n+\tCVMX_SFP_CABLE_64GFC_LW = 0x52,\n+\tCVMX_SFP_CABLE_128GFC_EA = 0x53,\n+\tCVMX_SFP_CABLE_128GFC_SW = 0x54,\n+\tCVMX_SFP_CABLE_128GFC_LW = 0x55,\n+\n+};\n+\n+/** Optical modes module is compliant with */\n+enum cvmx_phy_sfp_10g_eth_compliance {\n+\tCVMX_SFP_CABLE_10GBASE_ER = 0x80, /** 10G ER */\n+\tCVMX_SFP_CABLE_10GBASE_LRM = 0x40, /** 10G LRM */\n+\tCVMX_SFP_CABLE_10GBASE_LR = 0x20, /** 10G LR */\n+\tCVMX_SFP_CABLE_10GBASE_SR = 0x10 /** 10G SR */\n+};\n+\n+/** Diagnostic ASIC compatibility */\n+enum cvmx_phy_sfp_sff_8472_diag_rev {\n+\tCVMX_SFP_SFF_8472_NO_DIAG = 0x00,\n+\tCVMX_SFP_SFF_8472_REV_9_3 = 0x01,\n+\tCVMX_SFP_SFF_8472_REV_9_5 = 0x02,\n+\tCVMX_SFP_SFF_8472_REV_10_2 = 0x03,\n+\tCVMX_SFP_SFF_8472_REV_10_4 = 0x04,\n+\tCVMX_SFP_SFF_8472_REV_11_0 = 0x05,\n+\tCVMX_SFP_SFF_8472_REV_11_3 = 0x06,\n+\tCVMX_SFP_SFF_8472_REV_11_4 = 0x07,\n+\tCVMX_SFP_SFF_8472_REV_12_0 = 0x08,\n+\tCVMX_SFP_SFF_8472_REV_UNALLOCATED = 0xff\n+};\n+\n+/**\n+ * Data structure describing the current SFP or QSFP EEPROM\n+ */\n+struct cvmx_sfp_mod_info {\n+\tenum cvmx_phy_sfp_conn_type conn_type; /** Connector type */\n+\tenum cvmx_phy_sfp_mod_type mod_type; /** Module type */\n+\tenum cvmx_phy_sfp_rate rate;\t /** Rate of module */\n+\t/** 10G Ethernet Compliance codes (logical OR) */\n+\tenum cvmx_phy_sfp_10g_eth_compliance eth_comp;\n+\t/** Extended Cable compliance */\n+\tenum cvmx_phy_sfp_cable_ext_compliance cable_comp;\n+\tu8 vendor_name[17]; /** Module vendor name */\n+\tu8 vendor_oui[3]; /** vendor OUI */\n+\tu8 vendor_pn[17]; /** Vendor part number */\n+\tu8 vendor_rev[5]; /** Vendor revision */\n+\tu8 vendor_sn[17]; /** Vendor serial number */\n+\tu8 date_code[9]; /** Date code */\n+\tbool valid;\t /** True if module is valid */\n+\tbool active_cable; /** False for passive copper */\n+\tbool copper_cable; /** True if cable is copper */\n+\t/** True if module is limiting (i.e. not passive copper) */\n+\tbool limiting;\n+\t/** Maximum length of copper cable in meters */\n+\tint max_copper_cable_len;\n+\t/** Max single mode cable length in meters */\n+\tint max_single_mode_cable_length;\n+\t/** Max 50um OM2 cable length */\n+\tint max_50um_om2_cable_length;\n+\t/** Max 62.5um OM1 cable length */\n+\tint max_62_5um_om1_cable_length;\n+\t/** Max 50um OM4 cable length */\n+\tint max_50um_om4_cable_length;\n+\t/** Max 50um OM3 cable length */\n+\tint max_50um_om3_cable_length;\n+\t/** Minimum bitrate in Mbps */\n+\tint bitrate_min;\n+\t/** Maximum bitrate in Mbps */\n+\tint bitrate_max;\n+\t/**\n+\t * Set to true if forward error correction is required,\n+\t * for example, a 25GBase-CR CA-S cable.\n+\t *\n+\t * FEC should only be disabled at 25G with CA-N cables. FEC is required\n+\t * with 5M and longer cables.\n+\t */\n+\tbool fec_required;\n+\t/** True if RX output is linear */\n+\tbool linear_rx_output;\n+\t/** Power level, can be 1, 2 or 3 */\n+\tint power_level;\n+\t/** False if conventional cooling is used, true for active cooling */\n+\tbool cooled_laser;\n+\t/** True if internal retimer or clock and data recovery circuit */\n+\tbool internal_cdr;\n+\t/** True if LoS is implemented */\n+\tbool los_implemented;\n+\t/** True if LoS is inverted from the standard */\n+\tbool los_inverted;\n+\t/** True if TX_FAULT is implemented */\n+\tbool tx_fault_implemented;\n+\t/** True if TX_DISABLE is implemented */\n+\tbool tx_disable_implemented;\n+\t/** True if RATE_SELECT is implemented */\n+\tbool rate_select_implemented;\n+\t/** True if tuneable transmitter technology is used */\n+\tbool tuneable_transmitter;\n+\t/** True if receiver decision threshold is implemented */\n+\tbool rx_decision_threshold_implemented;\n+\t/** True if diagnostic monitoring present */\n+\tbool diag_monitoring;\n+\t/** True if diagnostic address 0x7f is used for selecting the page */\n+\tbool diag_paging;\n+\t/** Diagnostic feature revision */\n+\tenum cvmx_phy_sfp_sff_8472_diag_rev diag_rev;\n+\t/** True if an address change sequence is required for diagnostics */\n+\tbool diag_addr_change_required;\n+\t/** True if RX power is averaged, false if OMA */\n+\tbool diag_rx_power_averaged;\n+\t/** True if diagnostics are externally calibrated */\n+\tbool diag_externally_calibrated;\n+\t/** True if diagnostics are internally calibrated */\n+\tbool diag_internally_calibrated;\n+\t/** True of soft rate select control implemented per SFF-8431 */\n+\tbool diag_soft_rate_select_control;\n+\t/** True if application select control implemented per SFF-8079 */\n+\tbool diag_app_select_control;\n+\t/** True if soft RATE_SELECT control and moonitoring implemented */\n+\tbool diag_soft_rate_select_implemented;\n+\t/** True if soft RX_LOS monitoring implemented */\n+\tbool diag_soft_rx_los_implemented;\n+\t/** True if soft TX_FAULT monitoring implemented */\n+\tbool diag_soft_tx_fault_implemented;\n+\t/** True if soft TX_DISABLE control and monitoring implemented */\n+\tbool diag_soft_tx_disable_implemented;\n+\t/** True if alarm/warning flags implemented */\n+\tbool diag_alarm_warning_flags_implemented;\n+};\n+\n+/**\n+ * Reads the SFP EEPROM using the i2c bus\n+ *\n+ * @param[out]\tbuffer\t\tBuffer to store SFP EEPROM data in\n+ *\t\t\t\tThe buffer should be SFP_MAX_EEPROM_SIZE bytes.\n+ * @param\ti2c_bus\t\ti2c bus number to read from for SFP port\n+ * @param\ti2c_addr\ti2c address to use, 0 for default\n+ *\n+ * @return\t-1 if invalid bus or i2c read error, 0 for success\n+ */\n+int cvmx_phy_sfp_read_i2c_eeprom(u8 *buffer, int i2c_bus, int i2c_addr);\n+\n+/**\n+ * Reads the SFP/SFP+/QSFP EEPROM and outputs the type of module or cable\n+ * plugged in\n+ *\n+ * @param[out]\tsfp_info\tInfo about SFP module\n+ * @param[in]\tbuffer\t\tSFP EEPROM buffer to parse\n+ *\n+ * @return\t0 on success, -1 if error reading EEPROM or if EEPROM corrupt\n+ */\n+int cvmx_phy_sfp_parse_eeprom(struct cvmx_sfp_mod_info *sfp_info, const u8 *buffer);\n+\n+/**\n+ * Prints out information about a SFP/QSFP device\n+ *\n+ * @param[in]\tsfp_info\tdata structure to print\n+ */\n+void cvmx_phy_sfp_print_info(const struct cvmx_sfp_mod_info *sfp_info);\n+\n+/**\n+ * Reads and parses SFP/QSFP EEPROM\n+ *\n+ * @param\tsfp\tsfp handle to read\n+ *\n+ * @return\t0 for success, -1 on error.\n+ */\n+int cvmx_sfp_read_i2c_eeprom(struct cvmx_fdt_sfp_info *sfp);\n+\n+/**\n+ * Returns the information about a SFP/QSFP device\n+ *\n+ * @param sfp sfp handle\n+ *\n+ * @return sfp_info Pointer sfp mod info data structure\n+ */\n+const struct cvmx_sfp_mod_info *cvmx_phy_get_sfp_mod_info(const struct cvmx_fdt_sfp_info *sfp);\n+\n+/**\n+ * Function called to check and return the status of the mod_abs pin or\n+ * mod_pres pin for QSFPs.\n+ *\n+ * @param\tsfp\tHandle to SFP information.\n+ * @param\tdata\tUser-defined data passed to the function\n+ *\n+ * @return\t0 if absent, 1 if present, -1 on error\n+ */\n+int cvmx_sfp_check_mod_abs(struct cvmx_fdt_sfp_info *sfp, void *data);\n+\n+/**\n+ * Registers a function to be called to check mod_abs/mod_pres for a SFP/QSFP\n+ * slot.\n+ *\n+ * @param\tsfp\t\tHandle to SFP data structure\n+ * @param\tcheck_mod_abs\tFunction to be called or NULL to remove\n+ * @param\tmod_abs_data\tUser-defined data to be passed to check_mod_abs\n+ *\n+ * @return\t0 for success\n+ */\n+int cvmx_sfp_register_check_mod_abs(struct cvmx_fdt_sfp_info *sfp,\n+\t\t\t\t int (*check_mod_abs)(struct cvmx_fdt_sfp_info *sfp, void *data),\n+\t\t\t\t void *mod_abs_data);\n+\n+/**\n+ * Registers a function to be called whenever the mod_abs/mod_pres signal\n+ * changes.\n+ *\n+ * @param\tsfp\t\tHandle to SFP data structure\n+ * @param\tmod_abs_changed\tFunction called whenever mod_abs is changed\n+ *\t\t\t\tor NULL to remove.\n+ * @param\tmod_abs_changed_data\tUser-defined data passed to\n+ *\t\t\t\t\tmod_abs_changed\n+ *\n+ * @return\t0 for success\n+ */\n+int cvmx_sfp_register_mod_abs_changed(struct cvmx_fdt_sfp_info *sfp,\n+\t\t\t\t int (*mod_abs_changed)(struct cvmx_fdt_sfp_info *sfp, int val,\n+\t\t\t\t\t\t\t void *data),\n+\t\t\t\t void *mod_abs_changed_data);\n+\n+/**\n+ * Function called to check and return the status of the tx_fault pin\n+ *\n+ * @param\tsfp\tHandle to SFP information.\n+ * @param\tdata\tUser-defined data passed to the function\n+ *\n+ * @return\t0 if signal present, 1 if signal absent, -1 on error\n+ */\n+int cvmx_sfp_check_tx_fault(struct cvmx_fdt_sfp_info *sfp, void *data);\n+\n+/**\n+ * Function called to check and return the status of the rx_los pin\n+ *\n+ * @param\tsfp\tHandle to SFP information.\n+ * @param\tdata\tUser-defined data passed to the function\n+ *\n+ * @return\t0 if signal present, 1 if signal absent, -1 on error\n+ */\n+int cvmx_sfp_check_rx_los(struct cvmx_fdt_sfp_info *sfp, void *data);\n+\n+/**\n+ * Registers a function to be called whenever rx_los changes\n+ *\n+ * @param\tsfp\t\tHandle to SFP data structure\n+ * @param\trx_los_changed\tFunction to be called when rx_los changes\n+ *\t\t\t\tor NULL to remove the function\n+ * @param\trx_los_changed_data\tUser-defined data passed to\n+ *\t\t\t\t\trx_los_changed\n+ *\n+ * @return\t0 for success\n+ */\n+int cvmx_sfp_register_rx_los_changed(struct cvmx_fdt_sfp_info *sfp,\n+\t\t\t\t int (*rx_los_changed)(struct cvmx_fdt_sfp_info *sfp, int val,\n+\t\t\t\t\t\t\t void *data),\n+\t\t\t\t void *rx_los_changed_data);\n+\n+/**\n+ * Parses the device tree for SFP and QSFP slots\n+ *\n+ * @param\tfdt_addr\tAddress of flat device-tree\n+ *\n+ * @return\t0 for success, -1 on error\n+ */\n+int cvmx_sfp_parse_device_tree(const void *fdt_addr);\n+\n+/**\n+ * Given an IPD port number find the corresponding SFP or QSFP slot\n+ *\n+ * @param\tipd_port\tIPD port number to search for\n+ *\n+ * @return\tpointer to SFP data structure or NULL if not found\n+ */\n+struct cvmx_fdt_sfp_info *cvmx_sfp_find_slot_by_port(int ipd_port);\n+\n+/**\n+ * Given a fdt node offset find the corresponding SFP or QSFP slot\n+ *\n+ * @param\tof_offset\tflat device tree node offset\n+ *\n+ * @return\tpointer to SFP data structure or NULL if not found\n+ */\n+struct cvmx_fdt_sfp_info *cvmx_sfp_find_slot_by_fdt_node(int of_offset);\n+\n+/**\n+ * Reads the EEPROMs of all SFP modules.\n+ *\n+ * @return 0 for success\n+ */\n+int cvmx_sfp_read_all_modules(void);\n+\n+/**\n+ * Validates if the module is correct for the specified port\n+ *\n+ * @param[in]\tsfp\tSFP port to check\n+ * @param\tmode\tinterface mode\n+ *\n+ * @return\ttrue if module is valid, false if invalid\n+ * NOTE: This will also toggle the error LED, if present\n+ */\n+bool cvmx_sfp_validate_module(struct cvmx_fdt_sfp_info *sfp, int mode);\n+\n+/**\n+ * Prints information about the SFP module\n+ *\n+ * @param[in]\tsfp\tsfp data structure\n+ */\n+void cvmx_sfp_print_info(const struct cvmx_fdt_sfp_info *sfp);\n+\n+#endif /* __CVMX_HELPER_SFP_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-sgmii.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-sgmii.h\nnew file mode 100644\nindex 0000000000..c5110c9513\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-sgmii.h\n@@ -0,0 +1,81 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Functions for SGMII initialization, configuration,\n+ * and monitoring.\n+ */\n+\n+#ifndef __CVMX_HELPER_SGMII_H__\n+#define __CVMX_HELPER_SGMII_H__\n+\n+/**\n+ * @INTERNAL\n+ * Probe a SGMII interface and determine the number of ports\n+ * connected to it. The SGMII interface should still be down after\n+ * this call.\n+ *\n+ * @param xiface Interface to probe\n+ *\n+ * @return Number of ports on the interface. Zero to disable.\n+ */\n+int __cvmx_helper_sgmii_probe(int xiface);\n+int __cvmx_helper_sgmii_enumerate(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Bringup and enable a SGMII interface. After this call packet\n+ * I/O should be fully functional. This is called with IPD\n+ * enabled but PKO disabled.\n+ *\n+ * @param xiface Interface to bring up\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_sgmii_enable(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Return the link state of an IPD/PKO port as returned by\n+ * auto negotiation. The result of this function may not match\n+ * Octeon's link config if auto negotiation has changed since\n+ * the last call to cvmx_helper_link_set().\n+ *\n+ * @param ipd_port IPD/PKO port to query\n+ *\n+ * @return Link state\n+ */\n+cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * Configure an IPD/PKO port for the specified link state. This\n+ * function does not influence auto negotiation at the PHY level.\n+ * The passed link state must always match the link state returned\n+ * by cvmx_helper_link_get(). It is normally best to use\n+ * cvmx_helper_link_autoconf() instead.\n+ *\n+ * @param ipd_port IPD/PKO port to configure\n+ * @param link_info The new link state\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_sgmii_link_set(int ipd_port, cvmx_helper_link_info_t link_info);\n+\n+/**\n+ * @INTERNAL\n+ * Configure a port for internal and/or external loopback. Internal loopback\n+ * causes packets sent by the port to be received by Octeon. External loopback\n+ * causes packets received from the wire to sent out again.\n+ *\n+ * @param ipd_port IPD/PKO port to loopback.\n+ * @param enable_internal\n+ * Non zero if you want internal loopback\n+ * @param enable_external\n+ * Non zero if you want external loopback\n+ *\n+ * @return Zero on success, negative on failure.\n+ */\n+int __cvmx_helper_sgmii_configure_loopback(int ipd_port, int enable_internal, int enable_external);\n+\n+#endif\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-spi.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-spi.h\nnew file mode 100644\nindex 0000000000..cae72f2172\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-spi.h\n@@ -0,0 +1,73 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Functions for SPI initialization, configuration,\n+ * and monitoring.\n+ */\n+\n+#ifndef __CVMX_HELPER_SPI_H__\n+#define __CVMX_HELPER_SPI_H__\n+\n+#include \"cvmx-helper.h\"\n+\n+/**\n+ * @INTERNAL\n+ * Probe a SPI interface and determine the number of ports\n+ * connected to it. The SPI interface should still be down after\n+ * this call.\n+ *\n+ * @param interface Interface to probe\n+ *\n+ * @return Number of ports on the interface. Zero to disable.\n+ */\n+int __cvmx_helper_spi_probe(int interface);\n+int __cvmx_helper_spi_enumerate(int interface);\n+\n+/**\n+ * @INTERNAL\n+ * Bringup and enable a SPI interface. After this call packet I/O\n+ * should be fully functional. This is called with IPD enabled but\n+ * PKO disabled.\n+ *\n+ * @param interface Interface to bring up\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_spi_enable(int interface);\n+\n+/**\n+ * @INTERNAL\n+ * Return the link state of an IPD/PKO port as returned by\n+ * auto negotiation. The result of this function may not match\n+ * Octeon's link config if auto negotiation has changed since\n+ * the last call to cvmx_helper_link_set().\n+ *\n+ * @param ipd_port IPD/PKO port to query\n+ *\n+ * @return Link state\n+ */\n+cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * Configure an IPD/PKO port for the specified link state. This\n+ * function does not influence auto negotiation at the PHY level.\n+ * The passed link state must always match the link state returned\n+ * by cvmx_helper_link_get(). It is normally best to use\n+ * cvmx_helper_link_autoconf() instead.\n+ *\n+ * @param ipd_port IPD/PKO port to configure\n+ * @param link_info The new link state\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_spi_link_set(int ipd_port, cvmx_helper_link_info_t link_info);\n+\n+/**\n+ * Sets the spi timeout in config data\n+ * @param timeout value\n+ */\n+void cvmx_spi_config_set_timeout(int timeout);\n+\n+#endif\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-srio.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-srio.h\nnew file mode 100644\nindex 0000000000..2b7571dced\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-srio.h\n@@ -0,0 +1,72 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Functions for SRIO initialization, configuration,\n+ * and monitoring.\n+ */\n+\n+#ifndef __CVMX_HELPER_SRIO_H__\n+#define __CVMX_HELPER_SRIO_H__\n+\n+/**\n+ * @INTERNAL\n+ * Convert interface number to sRIO link number\n+ * per SoC model.\n+ *\n+ * @param xiface Interface to convert\n+ *\n+ * @return Srio link number\n+ */\n+int __cvmx_helper_srio_port(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Probe a SRIO interface and determine the number of ports\n+ * connected to it. The SRIO interface should still be down after\n+ * this call.\n+ *\n+ * @param xiface Interface to probe\n+ *\n+ * @return Number of ports on the interface. Zero to disable.\n+ */\n+int __cvmx_helper_srio_probe(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Bringup and enable a SRIO interface. After this call packet\n+ * I/O should be fully functional. This is called with IPD\n+ * enabled but PKO disabled.\n+ *\n+ * @param xiface Interface to bring up\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_srio_enable(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Return the link state of an IPD/PKO port as returned by SRIO link status.\n+ *\n+ * @param ipd_port IPD/PKO port to query\n+ *\n+ * @return Link state\n+ */\n+cvmx_helper_link_info_t __cvmx_helper_srio_link_get(int ipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * Configure an IPD/PKO port for the specified link state. This\n+ * function does not influence auto negotiation at the PHY level.\n+ * The passed link state must always match the link state returned\n+ * by cvmx_helper_link_get(). It is normally best to use\n+ * cvmx_helper_link_autoconf() instead.\n+ *\n+ * @param ipd_port IPD/PKO port to configure\n+ * @param link_info The new link state\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_srio_link_set(int ipd_port, cvmx_helper_link_info_t link_info);\n+\n+#endif\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-util.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-util.h\nnew file mode 100644\nindex 0000000000..cf98eaeba4\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-util.h\n@@ -0,0 +1,412 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#ifndef __CVMX_HELPER_UTIL_H__\n+#define __CVMX_HELPER_UTIL_H__\n+\n+#include \"cvmx-mio-defs.h\"\n+#include \"cvmx-helper.h\"\n+#include \"cvmx-fpa.h\"\n+\n+typedef char cvmx_pknd_t;\n+typedef char cvmx_bpid_t;\n+\n+#define CVMX_INVALID_PKND ((cvmx_pknd_t)-1)\n+#define CVMX_INVALID_BPID ((cvmx_bpid_t)-1)\n+#define CVMX_MAX_PKND\t ((cvmx_pknd_t)64)\n+#define CVMX_MAX_BPID\t ((cvmx_bpid_t)64)\n+\n+#define CVMX_HELPER_MAX_IFACE 11\n+#define CVMX_HELPER_MAX_PORTS 16\n+\n+/* Maximum range for normalized (a.k.a. IPD) port numbers (12-bit field) */\n+#define CVMX_PKO3_IPD_NUM_MAX 0x1000 //FIXME- take it from someplace else ?\n+#define CVMX_PKO3_DQ_NUM_MAX 0x400 // 78xx has 1024 queues\n+\n+#define CVMX_PKO3_IPD_PORT_NULL (CVMX_PKO3_IPD_NUM_MAX - 1)\n+#define CVMX_PKO3_IPD_PORT_LOOP 0\n+\n+struct cvmx_xport {\n+\tint node;\n+\tint port;\n+};\n+\n+typedef struct cvmx_xport cvmx_xport_t;\n+\n+static inline struct cvmx_xport cvmx_helper_ipd_port_to_xport(int ipd_port)\n+{\n+\tstruct cvmx_xport r;\n+\n+\tr.port = ipd_port & (CVMX_PKO3_IPD_NUM_MAX - 1);\n+\tr.node = (ipd_port >> 12) & CVMX_NODE_MASK;\n+\treturn r;\n+}\n+\n+static inline int cvmx_helper_node_to_ipd_port(int node, int index)\n+{\n+\treturn (node << 12) + index;\n+}\n+\n+struct cvmx_xdq {\n+\tint node;\n+\tint queue;\n+};\n+\n+typedef struct cvmx_xdq cvmx_xdq_t;\n+\n+static inline struct cvmx_xdq cvmx_helper_queue_to_xdq(int queue)\n+{\n+\tstruct cvmx_xdq r;\n+\n+\tr.queue = queue & (CVMX_PKO3_DQ_NUM_MAX - 1);\n+\tr.node = (queue >> 10) & CVMX_NODE_MASK;\n+\treturn r;\n+}\n+\n+static inline int cvmx_helper_node_to_dq(int node, int queue)\n+{\n+\treturn (node << 10) + queue;\n+}\n+\n+struct cvmx_xiface {\n+\tint node;\n+\tint interface;\n+};\n+\n+typedef struct cvmx_xiface cvmx_xiface_t;\n+\n+/**\n+ * Return node and interface number from XIFACE.\n+ *\n+ * @param xiface interface with node information\n+ *\n+ * @return struct that contains node and interface number.\n+ */\n+static inline struct cvmx_xiface cvmx_helper_xiface_to_node_interface(int xiface)\n+{\n+\tcvmx_xiface_t interface_node;\n+\n+\t/*\n+\t * If the majic number 0xde0000 is not present in the\n+\t * interface, then assume it is node 0.\n+\t */\n+\n+\tif (((xiface >> 0x8) & 0xff) == 0xde) {\n+\t\tinterface_node.node = (xiface >> 16) & CVMX_NODE_MASK;\n+\t\tinterface_node.interface = xiface & 0xff;\n+\t} else {\n+\t\tinterface_node.node = cvmx_get_node_num();\n+\t\tinterface_node.interface = xiface & 0xff;\n+\t}\n+\treturn interface_node;\n+}\n+\n+/* Used internally only*/\n+static inline bool __cvmx_helper_xiface_is_null(int xiface)\n+{\n+\treturn (xiface & 0xff) == 0xff;\n+}\n+\n+#define __CVMX_XIFACE_NULL 0xff\n+\n+/**\n+ * Return interface with majic number and node information (XIFACE)\n+ *\n+ * @param node node of the interface referred to\n+ * @param interface interface to use.\n+ *\n+ * @return\n+ */\n+static inline int cvmx_helper_node_interface_to_xiface(int node, int interface)\n+{\n+\treturn ((node & CVMX_NODE_MASK) << 16) | (0xde << 8) | (interface & 0xff);\n+}\n+\n+/**\n+ * Free the pip packet buffers contained in a work queue entry.\n+ * The work queue entry is not freed.\n+ *\n+ * @param work Work queue entry with packet to free\n+ */\n+static inline void cvmx_helper_free_pip_pkt_data(cvmx_wqe_t *work)\n+{\n+\tu64 number_buffers;\n+\tcvmx_buf_ptr_t buffer_ptr;\n+\tcvmx_buf_ptr_t next_buffer_ptr;\n+\tu64 start_of_buffer;\n+\n+\tnumber_buffers = work->word2.s.bufs;\n+\tif (number_buffers == 0)\n+\t\treturn;\n+\n+\tbuffer_ptr = work->packet_ptr;\n+\n+\t/* Since the number of buffers is not zero, we know this is not a dynamic\n+\t short packet. We need to check if it is a packet received with\n+\t IPD_CTL_STATUS[NO_WPTR]. If this is true, we need to free all buffers\n+\t except for the first one. The caller doesn't expect their WQE pointer\n+\t to be freed */\n+\tstart_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;\n+\tif (cvmx_ptr_to_phys(work) == start_of_buffer) {\n+\t\tnext_buffer_ptr = *(cvmx_buf_ptr_t *)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);\n+\t\tbuffer_ptr = next_buffer_ptr;\n+\t\tnumber_buffers--;\n+\t}\n+\n+\twhile (number_buffers--) {\n+\t\t/* Remember the back pointer is in cache lines, not 64bit words */\n+\t\tstart_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;\n+\t\t/* Read pointer to next buffer before we free the current buffer. */\n+\t\tnext_buffer_ptr = *(cvmx_buf_ptr_t *)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);\n+\t\tcvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer), buffer_ptr.s.pool, 0);\n+\t\tbuffer_ptr = next_buffer_ptr;\n+\t}\n+}\n+\n+/**\n+ * Free the pki packet buffers contained in a work queue entry.\n+ * If first packet buffer contains wqe, wqe gets freed too so do not access\n+ * wqe after calling this function.\n+ * This function asssumes that buffers to be freed are from\n+ * Naturally aligned pool/aura.\n+ * It does not use don't write back.\n+ * @param work Work queue entry with packet to free\n+ */\n+static inline void cvmx_helper_free_pki_pkt_data(cvmx_wqe_t *work)\n+{\n+\tu64 number_buffers;\n+\tu64 start_of_buffer;\n+\tcvmx_buf_ptr_pki_t next_buffer_ptr;\n+\tcvmx_buf_ptr_pki_t buffer_ptr;\n+\tcvmx_wqe_78xx_t *wqe = (cvmx_wqe_78xx_t *)work;\n+\n+\tif (!octeon_has_feature(OCTEON_FEATURE_CN78XX_WQE)) {\n+\t\treturn;\n+\t}\n+\t/* Make sure errata pki-20776 has been applied*/\n+\tcvmx_wqe_pki_errata_20776(work);\n+\tbuffer_ptr = wqe->packet_ptr;\n+\tnumber_buffers = cvmx_wqe_get_bufs(work);\n+\n+\twhile (number_buffers--) {\n+\t\t/* FIXME: change WQE function prototype */\n+\t\tunsigned int x = cvmx_wqe_get_aura(work);\n+\t\tcvmx_fpa3_gaura_t aura = __cvmx_fpa3_gaura(x >> 10, x & 0x3ff);\n+\t\t/* XXX- assumes the buffer is cache-line aligned and naturally aligned mode*/\n+\t\tstart_of_buffer = (buffer_ptr.addr >> 7) << 7;\n+\t\t/* Read pointer to next buffer before we free the current buffer. */\n+\t\tnext_buffer_ptr = *(cvmx_buf_ptr_pki_t *)cvmx_phys_to_ptr(buffer_ptr.addr - 8);\n+\t\t/* FPA AURA comes from WQE, includes node */\n+\t\tcvmx_fpa3_free(cvmx_phys_to_ptr(start_of_buffer), aura, 0);\n+\t\tbuffer_ptr = next_buffer_ptr;\n+\t}\n+}\n+\n+/**\n+ * Free the pki wqe entry buffer.\n+ * If wqe buffers contains first packet buffer, wqe does not get freed here.\n+ * This function asssumes that buffers to be freed are from\n+ * Naturally aligned pool/aura.\n+ * It does not use don't write back.\n+ * @param work Work queue entry to free\n+ */\n+static inline void cvmx_wqe_pki_free(cvmx_wqe_t *work)\n+{\n+\tcvmx_wqe_78xx_t *wqe = (cvmx_wqe_78xx_t *)work;\n+\tunsigned int x;\n+\tcvmx_fpa3_gaura_t aura;\n+\n+\tif (!octeon_has_feature(OCTEON_FEATURE_CN78XX_WQE)) {\n+\t\treturn;\n+\t}\n+\t/* Do nothing if the first packet buffer shares WQE buffer */\n+\tif (!wqe->packet_ptr.packet_outside_wqe)\n+\t\treturn;\n+\n+\t/* FIXME change WQE function prototype */\n+\tx = cvmx_wqe_get_aura(work);\n+\taura = __cvmx_fpa3_gaura(x >> 10, x & 0x3ff);\n+\n+\tcvmx_fpa3_free(work, aura, 0);\n+}\n+\n+/**\n+ * Convert a interface mode into a human readable string\n+ *\n+ * @param mode Mode to convert\n+ *\n+ * @return String\n+ */\n+const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode);\n+\n+/**\n+ * Debug routine to dump the packet structure to the console\n+ *\n+ * @param work Work queue entry containing the packet to dump\n+ * @return\n+ */\n+int cvmx_helper_dump_packet(cvmx_wqe_t *work);\n+\n+/**\n+ * Get the version of the CVMX libraries.\n+ *\n+ * @return Version string. Note this buffer is allocated statically\n+ * and will be shared by all callers.\n+ */\n+const char *cvmx_helper_get_version(void);\n+\n+/**\n+ * @INTERNAL\n+ * Setup the common GMX settings that determine the number of\n+ * ports. These setting apply to almost all configurations of all\n+ * chips.\n+ *\n+ * @param xiface Interface to configure\n+ * @param num_ports Number of ports on the interface\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_setup_gmx(int xiface, int num_ports);\n+\n+/**\n+ * @INTERNAL\n+ * Get the number of pko_ports on an interface.\n+ *\n+ * @param interface\n+ *\n+ * @return the number of pko_ports on the interface.\n+ */\n+int __cvmx_helper_get_num_pko_ports(int interface);\n+\n+/**\n+ * Returns the IPD port number for a port on the given\n+ * interface.\n+ *\n+ * @param interface Interface to use\n+ * @param port Port on the interface\n+ *\n+ * @return IPD port number\n+ */\n+int cvmx_helper_get_ipd_port(int interface, int port);\n+\n+/**\n+ * Returns the PKO port number for a port on the given interface,\n+ * This is the base pko_port for o68 and ipd_port for older models.\n+ *\n+ * @param interface Interface to use\n+ * @param port Port on the interface\n+ *\n+ * @return PKO port number and -1 on error.\n+ */\n+int cvmx_helper_get_pko_port(int interface, int port);\n+\n+/**\n+ * Returns the IPD/PKO port number for the first port on the given\n+ * interface.\n+ *\n+ * @param interface Interface to use\n+ *\n+ * @return IPD/PKO port number\n+ */\n+static inline int cvmx_helper_get_first_ipd_port(int interface)\n+{\n+\treturn cvmx_helper_get_ipd_port(interface, 0);\n+}\n+\n+int cvmx_helper_ports_on_interface(int interface);\n+\n+/**\n+ * Returns the IPD/PKO port number for the last port on the given\n+ * interface.\n+ *\n+ * @param interface Interface to use\n+ *\n+ * @return IPD/PKO port number\n+ *\n+ * Note: for o68, the last ipd port on an interface does not always equal to\n+ * the first plus the number of ports as the ipd ports are not contiguous in\n+ * some cases, e.g., SGMII.\n+ *\n+ * Note: code that makes the assumption of contiguous ipd port numbers needs to\n+ * be aware of this.\n+ */\n+static inline int cvmx_helper_get_last_ipd_port(int interface)\n+{\n+\treturn cvmx_helper_get_ipd_port(interface, cvmx_helper_ports_on_interface(interface) - 1);\n+}\n+\n+/**\n+ * Free the packet buffers contained in a work queue entry.\n+ * The work queue entry is not freed.\n+ * Note that this function will not free the work queue entry\n+ * even if it contains a non-redundant data packet, and hence\n+ * it is not really comparable to how the PKO would free a packet\n+ * buffers if requested.\n+ *\n+ * @param work Work queue entry with packet to free\n+ */\n+void cvmx_helper_free_packet_data(cvmx_wqe_t *work);\n+\n+/**\n+ * Returns the interface number for an IPD/PKO port number.\n+ *\n+ * @param ipd_port IPD/PKO port number\n+ *\n+ * @return Interface number\n+ */\n+int cvmx_helper_get_interface_num(int ipd_port);\n+\n+/**\n+ * Returns the interface index number for an IPD/PKO port\n+ * number.\n+ *\n+ * @param ipd_port IPD/PKO port number\n+ *\n+ * @return Interface index number\n+ */\n+int cvmx_helper_get_interface_index_num(int ipd_port);\n+\n+/**\n+ * Get port kind for a given port in an interface.\n+ *\n+ * @param xiface Interface\n+ * @param index index of the port in the interface\n+ *\n+ * @return port kind on sucicess and -1 on failure\n+ */\n+int cvmx_helper_get_pknd(int xiface, int index);\n+\n+/**\n+ * Get bpid for a given port in an interface.\n+ *\n+ * @param interface Interface\n+ * @param port index of the port in the interface\n+ *\n+ * @return port kind on sucicess and -1 on failure\n+ */\n+int cvmx_helper_get_bpid(int interface, int port);\n+\n+/**\n+ * Internal functions.\n+ */\n+int __cvmx_helper_post_init_interfaces(void);\n+int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);\n+void cvmx_helper_show_stats(int port);\n+\n+/*\n+ * Return number of array alements\n+ */\n+#define NUM_ELEMENTS(arr) (sizeof(arr) / sizeof((arr)[0]))\n+\n+/**\n+ * Prints out a buffer with the address, hex bytes, and ASCII\n+ *\n+ * @param\taddr\tStart address to print on the left\n+ * @param[in]\tbuffer\tarray of bytes to print\n+ * @param\tcount\tNumber of bytes to print\n+ */\n+void cvmx_print_buffer_u8(unsigned int addr, const u8 *buffer, size_t count);\n+\n+#endif /* __CVMX_HELPER_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-xaui.h b/arch/mips/mach-octeon/include/mach/cvmx-helper-xaui.h\nnew file mode 100644\nindex 0000000000..6ff4576f23\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-xaui.h\n@@ -0,0 +1,108 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Functions for XAUI initialization, configuration,\n+ * and monitoring.\n+ */\n+\n+#ifndef __CVMX_HELPER_XAUI_H__\n+#define __CVMX_HELPER_XAUI_H__\n+\n+/**\n+ * @INTERNAL\n+ * Probe a XAUI interface and determine the number of ports\n+ * connected to it. The XAUI interface should still be down\n+ * after this call.\n+ *\n+ * @param xiface Interface to probe\n+ *\n+ * @return Number of ports on the interface. Zero to disable.\n+ */\n+int __cvmx_helper_xaui_probe(int xiface);\n+int __cvmx_helper_xaui_enumerate(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ * Bringup and enable a XAUI interface. After this call packet\n+ * I/O should be fully functional. This is called with IPD\n+ * enabled but PKO disabled.\n+ *\n+ * @param xiface Interface to bring up\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_xaui_enable(int xiface);\n+\n+/**\n+ * Retrain XAUI interface.\n+ *\n+ * GMX is disabled as part of retraining.\n+ * While GMX is disabled, new received packets are dropped.\n+ * If GMX was in the middle of recieving a packet when disabled,\n+ * that packet will be received before GMX idles.\n+ * Transmitted packets are buffered normally, but not sent.\n+ * If GMX was in the middle of transmitting a packet when disabled,\n+ * that packet will be transmitted before GMX idles.\n+ *\n+ * @param interface Interface to retrain\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int cvmx_helper_xaui_link_retrain(int interface);\n+\n+/**\n+ * Reinitialize XAUI interface. Does a probe without changing the hardware\n+ * state.\n+ *\n+ * @param interface\tInterface to reinitialize\n+ *\n+ * @return\t0 on success, negative on failure\n+ */\n+int cvmx_helper_xaui_link_reinit(int interface);\n+\n+/**\n+ * @INTERNAL\n+ * Return the link state of an IPD/PKO port as returned by\n+ * auto negotiation. The result of this function may not match\n+ * Octeon's link config if auto negotiation has changed since\n+ * the last call to cvmx_helper_link_set().\n+ *\n+ * @param ipd_port IPD/PKO port to query\n+ *\n+ * @return Link state\n+ */\n+cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port);\n+\n+/**\n+ * @INTERNAL\n+ * Configure an IPD/PKO port for the specified link state. This\n+ * function does not influence auto negotiation at the PHY level.\n+ * The passed link state must always match the link state returned\n+ * by cvmx_helper_link_get(). It is normally best to use\n+ * cvmx_helper_link_autoconf() instead.\n+ *\n+ * @param ipd_port IPD/PKO port to configure\n+ * @param link_info The new link state\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info);\n+\n+/**\n+ * @INTERNAL\n+ * Configure a port for internal and/or external loopback. Internal loopback\n+ * causes packets sent by the port to be received by Octeon. External loopback\n+ * causes packets received from the wire to sent out again.\n+ *\n+ * @param ipd_port IPD/PKO port to loopback.\n+ * @param enable_internal\n+ * Non zero if you want internal loopback\n+ * @param enable_external\n+ * Non zero if you want external loopback\n+ *\n+ * @return Zero on success, negative on failure.\n+ */\n+int __cvmx_helper_xaui_configure_loopback(int ipd_port, int enable_internal, int enable_external);\n+\n+#endif\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper.h b/arch/mips/mach-octeon/include/mach/cvmx-helper.h\nnew file mode 100644\nindex 0000000000..b82e201269\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper.h\n@@ -0,0 +1,565 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Helper functions for common, but complicated tasks.\n+ */\n+\n+#ifndef __CVMX_HELPER_H__\n+#define __CVMX_HELPER_H__\n+\n+#include \"cvmx-wqe.h\"\n+\n+/* Max number of GMXX */\n+#define CVMX_HELPER_MAX_GMX \\\n+\t(OCTEON_IS_MODEL(OCTEON_CN78XX) ? \\\n+\t\t 6 : \\\n+\t\t (OCTEON_IS_MODEL(OCTEON_CN68XX) ? \\\n+\t\t\t\t5 : \\\n+\t\t\t\t(OCTEON_IS_MODEL(OCTEON_CN73XX) ? \\\n+\t\t\t\t\t 3 : \\\n+\t\t\t\t\t (OCTEON_IS_MODEL(OCTEON_CNF75XX) ? 1 : 2))))\n+\n+#define CVMX_HELPER_CSR_INIT0 \\\n+\t0 /* Do not change as\n+\t\t\t\t\t\t CVMX_HELPER_WRITE_CSR()\n+\t\t\t\t\t\t assumes it */\n+#define CVMX_HELPER_CSR_INIT_READ -1\n+\n+/*\n+ * CVMX_HELPER_WRITE_CSR--set a field in a CSR with a value.\n+ *\n+ * @param chcsr_init initial value of the csr (CVMX_HELPER_CSR_INIT_READ\n+ * means to use the existing csr value as the\n+ * initial value.)\n+ * @param chcsr_csr the name of the csr\n+ * @param chcsr_type the type of the csr (see the -defs.h)\n+ * @param chcsr_chip the chip for the csr/field\n+ * @param chcsr_fld the field in the csr\n+ * @param chcsr_val the value for field\n+ */\n+#define CVMX_HELPER_WRITE_CSR(chcsr_init, chcsr_csr, chcsr_type, chcsr_chip, chcsr_fld, chcsr_val) \\\n+\tdo { \\\n+\t\tchcsr_type csr; \\\n+\t\tif ((chcsr_init) == CVMX_HELPER_CSR_INIT_READ) \\\n+\t\t\tcsr.u64 = cvmx_read_csr(chcsr_csr); \\\n+\t\telse \\\n+\t\t\tcsr.u64 = (chcsr_init); \\\n+\t\tcsr.chcsr_chip.chcsr_fld = (chcsr_val); \\\n+\t\tcvmx_write_csr((chcsr_csr), csr.u64); \\\n+\t} while (0)\n+\n+/*\n+ * CVMX_HELPER_WRITE_CSR0--set a field in a CSR with the initial value of 0\n+ */\n+#define CVMX_HELPER_WRITE_CSR0(chcsr_csr, chcsr_type, chcsr_chip, chcsr_fld, chcsr_val) \\\n+\tCVMX_HELPER_WRITE_CSR(CVMX_HELPER_CSR_INIT0, chcsr_csr, chcsr_type, chcsr_chip, chcsr_fld, \\\n+\t\t\t chcsr_val)\n+\n+/*\n+ * CVMX_HELPER_WRITE_CSR1--set a field in a CSR with the initial value of\n+ * the CSR's current value.\n+ */\n+#define CVMX_HELPER_WRITE_CSR1(chcsr_csr, chcsr_type, chcsr_chip, chcsr_fld, chcsr_val) \\\n+\tCVMX_HELPER_WRITE_CSR(CVMX_HELPER_CSR_INIT_READ, chcsr_csr, chcsr_type, chcsr_chip, \\\n+\t\t\t chcsr_fld, chcsr_val)\n+\n+/* These flags are passed to __cvmx_helper_packet_hardware_enable */\n+\n+typedef enum {\n+\tCVMX_HELPER_INTERFACE_MODE_DISABLED,\n+\tCVMX_HELPER_INTERFACE_MODE_RGMII,\n+\tCVMX_HELPER_INTERFACE_MODE_GMII,\n+\tCVMX_HELPER_INTERFACE_MODE_SPI,\n+\tCVMX_HELPER_INTERFACE_MODE_PCIE,\n+\tCVMX_HELPER_INTERFACE_MODE_XAUI,\n+\tCVMX_HELPER_INTERFACE_MODE_SGMII,\n+\tCVMX_HELPER_INTERFACE_MODE_PICMG,\n+\tCVMX_HELPER_INTERFACE_MODE_NPI,\n+\tCVMX_HELPER_INTERFACE_MODE_LOOP,\n+\tCVMX_HELPER_INTERFACE_MODE_SRIO,\n+\tCVMX_HELPER_INTERFACE_MODE_ILK,\n+\tCVMX_HELPER_INTERFACE_MODE_RXAUI,\n+\tCVMX_HELPER_INTERFACE_MODE_QSGMII,\n+\tCVMX_HELPER_INTERFACE_MODE_AGL,\n+\tCVMX_HELPER_INTERFACE_MODE_XLAUI,\n+\tCVMX_HELPER_INTERFACE_MODE_XFI,\n+\tCVMX_HELPER_INTERFACE_MODE_10G_KR,\n+\tCVMX_HELPER_INTERFACE_MODE_40G_KR4,\n+\tCVMX_HELPER_INTERFACE_MODE_MIXED,\n+} cvmx_helper_interface_mode_t;\n+\n+typedef union cvmx_helper_link_info {\n+\tu64 u64;\n+\tstruct {\n+\t\tu64 reserved_20_63 : 43;\n+\t\tu64 init_success : 1;\n+\t\tu64 link_up : 1;\n+\t\tu64 full_duplex : 1;\n+\t\tu64 speed : 18;\n+\t} s;\n+} cvmx_helper_link_info_t;\n+\n+/**\n+ * Sets the back pressure configuration in internal data structure.\n+ * @param backpressure_dis disable/enable backpressure\n+ */\n+void cvmx_rgmii_set_back_pressure(u64 backpressure_dis);\n+\n+#include \"cvmx-helper-fpa.h\"\n+\n+#include \"cvmx-helper-agl.h\"\n+#include \"cvmx-helper-errata.h\"\n+#include \"cvmx-helper-ilk.h\"\n+#include \"cvmx-helper-loop.h\"\n+#include \"cvmx-helper-npi.h\"\n+#include \"cvmx-helper-rgmii.h\"\n+#include \"cvmx-helper-sgmii.h\"\n+#include \"cvmx-helper-spi.h\"\n+#include \"cvmx-helper-srio.h\"\n+#include \"cvmx-helper-util.h\"\n+#include \"cvmx-helper-xaui.h\"\n+\n+#include \"cvmx-fpa3.h\"\n+\n+enum cvmx_pko_padding {\n+\tCVMX_PKO_PADDING_NONE = 0,\n+\tCVMX_PKO_PADDING_60 = 1,\n+};\n+\n+/**\n+ * This function enables the IPD and also enables the packet interfaces.\n+ * The packet interfaces (RGMII and SPI) must be enabled after the\n+ * IPD. This should be called by the user program after any additional\n+ * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD\n+ * is not set in the executive-config.h file.\n+ *\n+ * @return 0 on success\n+ * -1 on failure\n+ */\n+int cvmx_helper_ipd_and_packet_input_enable_node(int node);\n+int cvmx_helper_ipd_and_packet_input_enable(void);\n+\n+/**\n+ * Initialize and allocate memory for the SSO.\n+ *\n+ * @param wqe_entries The maximum number of work queue entries to be\n+ * supported.\n+ *\n+ * @return Zero on success, non-zero on failure.\n+ */\n+int cvmx_helper_initialize_sso(int wqe_entries);\n+\n+/**\n+ * Initialize and allocate memory for the SSO on a specific node.\n+ *\n+ * @param node Node SSO to initialize\n+ * @param wqe_entries The maximum number of work queue entries to be\n+ * supported.\n+ *\n+ * @return Zero on success, non-zero on failure.\n+ */\n+int cvmx_helper_initialize_sso_node(unsigned int node, int wqe_entries);\n+\n+/**\n+ * Undo the effect of cvmx_helper_initialize_sso().\n+ *\n+ * @return Zero on success, non-zero on failure.\n+ */\n+int cvmx_helper_uninitialize_sso(void);\n+\n+/**\n+ * Undo the effect of cvmx_helper_initialize_sso_node().\n+ *\n+ * @param node Node SSO to initialize\n+ *\n+ * @return Zero on success, non-zero on failure.\n+ */\n+int cvmx_helper_uninitialize_sso_node(unsigned int node);\n+\n+/**\n+ * Initialize the PIP, IPD, and PKO hardware to support\n+ * simple priority based queues for the ethernet ports. Each\n+ * port is configured with a number of priority queues based\n+ * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower\n+ * priority than the previous.\n+ *\n+ * @return Zero on success, non-zero on failure\n+ */\n+int cvmx_helper_initialize_packet_io_global(void);\n+/**\n+ * Initialize the PIP, IPD, and PKO hardware to support\n+ * simple priority based queues for the ethernet ports. Each\n+ * port is configured with a number of priority queues based\n+ * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower\n+ * priority than the previous.\n+ *\n+ * @param node Node on which to initialize packet io hardware\n+ *\n+ * @return Zero on success, non-zero on failure\n+ */\n+int cvmx_helper_initialize_packet_io_node(unsigned int node);\n+\n+/**\n+ * Does core local initialization for packet io\n+ *\n+ * @return Zero on success, non-zero on failure\n+ */\n+int cvmx_helper_initialize_packet_io_local(void);\n+\n+/**\n+ * Undo the initialization performed in\n+ * cvmx_helper_initialize_packet_io_global(). After calling this routine and the\n+ * local version on each core, packet IO for Octeon will be disabled and placed\n+ * in the initial reset state. It will then be safe to call the initialize\n+ * later on. Note that this routine does not empty the FPA pools. It frees all\n+ * buffers used by the packet IO hardware to the FPA so a function emptying the\n+ * FPA after shutdown should find all packet buffers in the FPA.\n+ *\n+ * @return Zero on success, negative on failure.\n+ */\n+int cvmx_helper_shutdown_packet_io_global(void);\n+\n+/**\n+ * Helper function for 78xx global packet IO shutdown\n+ */\n+int cvmx_helper_shutdown_packet_io_global_cn78xx(int node);\n+\n+/**\n+ * Does core local shutdown of packet io\n+ *\n+ * @return Zero on success, non-zero on failure\n+ */\n+int cvmx_helper_shutdown_packet_io_local(void);\n+\n+/**\n+ * Returns the number of ports on the given interface.\n+ * The interface must be initialized before the port count\n+ * can be returned.\n+ *\n+ * @param interface Which interface to return port count for.\n+ *\n+ * @return Port count for interface\n+ * -1 for uninitialized interface\n+ */\n+int cvmx_helper_ports_on_interface(int interface);\n+\n+/**\n+ * Return the number of interfaces the chip has. Each interface\n+ * may have multiple ports. Most chips support two interfaces,\n+ * but the CNX0XX and CNX1XX are exceptions. These only support\n+ * one interface.\n+ *\n+ * @return Number of interfaces on chip\n+ */\n+int cvmx_helper_get_number_of_interfaces(void);\n+\n+/**\n+ * Get the operating mode of an interface. Depending on the Octeon\n+ * chip and configuration, this function returns an enumeration\n+ * of the type of packet I/O supported by an interface.\n+ *\n+ * @param xiface Interface to probe\n+ *\n+ * @return Mode of the interface. Unknown or unsupported interfaces return\n+ * DISABLED.\n+ */\n+cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int xiface);\n+\n+/**\n+ * Auto configure an IPD/PKO port link state and speed. This\n+ * function basically does the equivalent of:\n+ * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));\n+ *\n+ * @param ipd_port IPD/PKO port to auto configure\n+ *\n+ * @return Link state after configure\n+ */\n+cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port);\n+\n+/**\n+ * Return the link state of an IPD/PKO port as returned by\n+ * auto negotiation. The result of this function may not match\n+ * Octeon's link config if auto negotiation has changed since\n+ * the last call to cvmx_helper_link_set().\n+ *\n+ * @param ipd_port IPD/PKO port to query\n+ *\n+ * @return Link state\n+ */\n+cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port);\n+\n+/**\n+ * Configure an IPD/PKO port for the specified link state. This\n+ * function does not influence auto negotiation at the PHY level.\n+ * The passed link state must always match the link state returned\n+ * by cvmx_helper_link_get(). It is normally best to use\n+ * cvmx_helper_link_autoconf() instead.\n+ *\n+ * @param ipd_port IPD/PKO port to configure\n+ * @param link_info The new link state\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info);\n+\n+/**\n+ * This function probes an interface to determine the actual number of\n+ * hardware ports connected to it. It does some setup the ports but\n+ * doesn't enable them. The main goal here is to set the global\n+ * interface_port_count[interface] correctly. Final hardware setup of\n+ * the ports will be performed later.\n+ *\n+ * @param xiface Interface to probe\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int cvmx_helper_interface_probe(int xiface);\n+\n+/**\n+ * Determine the actual number of hardware ports connected to an\n+ * interface. It doesn't setup the ports or enable them.\n+ *\n+ * @param xiface Interface to enumerate\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int cvmx_helper_interface_enumerate(int xiface);\n+\n+/**\n+ * Configure a port for internal and/or external loopback. Internal loopback\n+ * causes packets sent by the port to be received by Octeon. External loopback\n+ * causes packets received from the wire to sent out again.\n+ *\n+ * @param ipd_port IPD/PKO port to loopback.\n+ * @param enable_internal\n+ * Non zero if you want internal loopback\n+ * @param enable_external\n+ * Non zero if you want external loopback\n+ *\n+ * @return Zero on success, negative on failure.\n+ */\n+int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, int enable_external);\n+\n+/**\n+ * Returns the number of ports on the given interface.\n+ *\n+ * @param interface Which interface to return port count for.\n+ *\n+ * @return Port count for interface\n+ * -1 for uninitialized interface\n+ */\n+int __cvmx_helper_early_ports_on_interface(int interface);\n+\n+void cvmx_helper_setup_simulator_io_buffer_counts(int node, int num_packet_buffers,\n+\t\t\t\t\t\t int pko_buffers);\n+\n+void cvmx_helper_set_wqe_no_ptr_mode(bool mode);\n+void cvmx_helper_set_pkt_wqe_le_mode(bool mode);\n+int cvmx_helper_shutdown_fpa_pools(int node);\n+\n+/**\n+ * Convert Ethernet QoS/PCP value to system-level priority\n+ *\n+ * In OCTEON, highest priority is 0, in Ethernet 802.1p PCP field\n+ * the highest priority is 7, lowest is 1. Here is the full conversion\n+ * table between QoS (PCP) and OCTEON priority values, per IEEE 802.1Q-2005:\n+ *\n+ * PCP\tPriority\tAcronym\tTraffic Types\n+ * 1\t7 (lowest)\tBK\tBackground\n+ * 0\t6\tBE\tBest Effort\n+ * 2\t5\tEE\tExcellent Effort\n+ * 3\t4\tCA\tCritical Applications\n+ * 4\t3\tVI\tVideo, < 100 ms latency and jitter\n+ * 5\t2\tVO\tVoice, < 10 ms latency and jitter\n+ * 6\t1\tIC\tInternetwork Control\n+ * 7\t0 (highest)\tNC\tNetwork Control\n+ */\n+static inline u8 cvmx_helper_qos2prio(u8 qos)\n+{\n+\tstatic const unsigned int pcp_map = 6 << (4 * 0) | 7 << (4 * 1) | 5 << (4 * 2) |\n+\t\t\t\t\t 4 << (4 * 3) | 3 << (4 * 4) | 2 << (4 * 5) |\n+\t\t\t\t\t 1 << (4 * 6) | 0 << (4 * 7);\n+\n+\treturn (pcp_map >> ((qos & 0x7) << 2)) & 0x7;\n+}\n+\n+/**\n+ * Convert system-level priority to Ethernet QoS/PCP value\n+ *\n+ * Calculate the reverse of cvmx_helper_qos2prio() per IEEE 802.1Q-2005.\n+ */\n+static inline u8 cvmx_helper_prio2qos(u8 prio)\n+{\n+\tstatic const unsigned int prio_map = 7 << (4 * 0) | 6 << (4 * 1) | 5 << (4 * 2) |\n+\t\t\t\t\t 4 << (4 * 3) | 3 << (4 * 4) | 2 << (4 * 5) |\n+\t\t\t\t\t 0 << (4 * 6) | 1 << (4 * 7);\n+\n+\treturn (prio_map >> ((prio & 0x7) << 2)) & 0x7;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Get the number of ipd_ports on an interface.\n+ *\n+ * @param xiface\n+ *\n+ * @return the number of ipd_ports on the interface and -1 for error.\n+ */\n+int __cvmx_helper_get_num_ipd_ports(int xiface);\n+\n+enum cvmx_pko_padding __cvmx_helper_get_pko_padding(int xiface);\n+\n+/**\n+ * @INTERNAL\n+ *\n+ * @param xiface\n+ * @param num_ipd_ports is the number of ipd_ports on the interface\n+ * @param has_fcs indicates if PKO does FCS for the ports on this\n+ * @param pad The padding that PKO should apply.\n+ * interface.\n+ *\n+ * @return 0 for success and -1 for failure\n+ */\n+int __cvmx_helper_init_interface(int xiface, int num_ipd_ports, int has_fcs,\n+\t\t\t\t enum cvmx_pko_padding pad);\n+\n+void __cvmx_helper_shutdown_interfaces(void);\n+\n+/*\n+ * @INTERNAL\n+ * Enable packet input/output from the hardware. This function is\n+ * called after all internal setup is complete and IPD is enabled.\n+ * After this function completes, packets will be accepted from the\n+ * hardware ports. PKO should still be disabled to make sure packets\n+ * aren't sent out partially setup hardware.\n+ *\n+ * @return Zero on success, negative on failure\n+ */\n+int __cvmx_helper_packet_hardware_enable(int xiface);\n+\n+/*\n+ * @INTERNAL\n+ *\n+ * @return 0 for success and -1 for failure\n+ */\n+int __cvmx_helper_set_link_info(int xiface, int index, cvmx_helper_link_info_t link_info);\n+\n+/**\n+ * @INTERNAL\n+ *\n+ * @param xiface\n+ * @param port\n+ *\n+ * @return valid link_info on success or -1 on failure\n+ */\n+cvmx_helper_link_info_t __cvmx_helper_get_link_info(int xiface, int port);\n+\n+/**\n+ * @INTERNAL\n+ *\n+ * @param xiface\n+ *\n+ * @return 0 if PKO does not do FCS and 1 otherwise.\n+ */\n+int __cvmx_helper_get_has_fcs(int xiface);\n+\n+void *cvmx_helper_mem_alloc(int node, u64 alloc_size, u64 align);\n+void cvmx_helper_mem_free(void *buffer, u64 size);\n+\n+#define CVMX_QOS_NUM 8 /* Number of QoS priority classes */\n+\n+typedef enum {\n+\tCVMX_QOS_PROTO_NONE, /* Disable QOS */\n+\tCVMX_QOS_PROTO_PAUSE, /* IEEE 802.3 PAUSE */\n+\tCVMX_QOS_PROTO_PFC /* IEEE 802.1Qbb-2011 PFC/CBFC */\n+} cvmx_qos_proto_t;\n+\n+typedef enum {\n+\tCVMX_QOS_PKT_MODE_HWONLY, /* PAUSE packets processed in Hardware only. */\n+\tCVMX_QOS_PKT_MODE_SWONLY, /* PAUSE packets processed in Software only. */\n+\tCVMX_QOS_PKT_MODE_HWSW,\t /* PAUSE packets processed in both HW and SW. */\n+\tCVMX_QOS_PKT_MODE_DROP\t /* Ignore PAUSE packets. */\n+} cvmx_qos_pkt_mode_t;\n+\n+typedef enum {\n+\tCVMX_QOS_POOL_PER_PORT, /* Pool per Physical Port */\n+\tCVMX_QOS_POOL_PER_CLASS /* Pool per Priority Class */\n+} cvmx_qos_pool_mode_t;\n+\n+typedef struct cvmx_qos_config {\n+\tcvmx_qos_proto_t qos_proto;\t/* QoS protocol.*/\n+\tcvmx_qos_pkt_mode_t pkt_mode;\t/* PAUSE processing mode.*/\n+\tcvmx_qos_pool_mode_t pool_mode; /* FPA Pool mode.*/\n+\tint pktbuf_size;\t\t/* Packet buffer size */\n+\tint aura_size;\t\t\t/* Number of buffers */\n+\tint drop_thresh[CVMX_QOS_NUM];\t/* DROP threashold in % */\n+\tint red_thresh[CVMX_QOS_NUM];\t/* RED threashold in % */\n+\tint bp_thresh[CVMX_QOS_NUM];\t/* BP threashold in % */\n+\tint groups[CVMX_QOS_NUM];\t/* Base SSO group for QOS group set. */\n+\tint group_prio[CVMX_QOS_NUM];\t/* SSO group priorities.*/\n+\tint pko_pfc_en;\t\t\t/* Enable PKO PFC layout. */\n+\tint vlan_num;\t\t\t/* VLAN number: 0 = 1st or 1 = 2nd. */\n+\tint p_time;\t\t\t/* PAUSE packets send time (in number of 512 bit-times).*/\n+\tint p_interval; /* PAUSE packet send interval (in number of 512 bit-times).*/\n+\t/* Internal parameters (should not be used by application developer): */\n+\tcvmx_fpa3_pool_t gpools[CVMX_QOS_NUM];\t/* Pool to use.*/\n+\tcvmx_fpa3_gaura_t gauras[CVMX_QOS_NUM]; /* Global auras -- one per priority class. */\n+\tint bpids[CVMX_QOS_NUM];\t\t/* PKI BPID.*/\n+\tint qpg_base;\t\t\t\t/* QPG Table base index.*/\n+} cvmx_qos_config_t;\n+\n+/**\n+ * Initialize QoS configuraiton with the SDK defaults.\n+ *\n+ * @param qos_cfg User QOS configuration parameters.\n+ * @return Zero on success, negative number otherwise.\n+ */\n+int cvmx_helper_qos_config_init(cvmx_qos_proto_t qos_proto, cvmx_qos_config_t *qos_cfg);\n+\n+/**\n+ * Update the user static processor configuration.\n+ * It should be done before any initialization of the DP units is performed.\n+ *\n+ * @param xipdport Global IPD port\n+ * @param qos_cfg User QOS configuration parameters.\n+ * @return Zero on success, negative number otherwise.\n+ */\n+int cvmx_helper_qos_port_config_update(int xipdport, cvmx_qos_config_t *qos_cfg);\n+\n+/**\n+ * Configure the Data Path components for QOS function.\n+ * This function is called after the global processor initialization is\n+ * performed.\n+ *\n+ * @param xipdport Global IPD port\n+ * @param qos_cfg User QOS configuration parameters.\n+ * @return Zero on success, negative number otherwise.\n+ */\n+int cvmx_helper_qos_port_setup(int xipdport, cvmx_qos_config_t *qos_cfg);\n+\n+/**\n+ * Configure the SSO for QOS function.\n+ * This function is called after the global processor initialization is\n+ * performed.\n+ *\n+ * @param node OCTEON3 node number.\n+ * @param qos_cfg User QOS configuration parameters.\n+ * @return Zero on success, negative number otherwise.\n+ */\n+int cvmx_helper_qos_sso_setup(int node, cvmx_qos_config_t *qos_cfg);\n+\n+/**\n+ * Return PKI_CHAN_E channel name based on the provided index.\n+ * @param chan Channel index.\n+ * @param namebuf Name buffer (output).\n+ * @param buflen Name maximum length.\n+ * @return Length of name (in bytes) on success, negative number otherwise.\n+ */\n+int cvmx_helper_get_chan_e_name(int chan, char *namebuf, int buflen);\n+\n+#ifdef CVMX_DUMP_DIAGNOSTICS\n+void cvmx_helper_dump_for_diagnostics(int node);\n+#endif\n+\n+#endif /* __CVMX_HELPER_H__ */\n", "prefixes": [ "v1", "02/50" ] }