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{
    "id": 1415038,
    "url": "http://patchwork.ozlabs.org/api/patches/1415038/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-6-sr@denx.de/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20201211160612.1498780-6-sr@denx.de>",
    "list_archive_url": null,
    "date": "2020-12-11T16:05:27",
    "name": "[v1,05/50] mips: octeon: Add cvmx-bgxx-defs.h header file",
    "commit_ref": "e6ce36344d167c629d71686cdd8e5665fe7ea028",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "0c4305a787ce7bfb07ce7ba01e795c45ad86877e",
    "submitter": {
        "id": 13,
        "url": "http://patchwork.ozlabs.org/api/people/13/?format=api",
        "name": "Stefan Roese",
        "email": "sr@denx.de"
    },
    "delegate": {
        "id": 4307,
        "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api",
        "username": "danielschwierzeck",
        "first_name": "Daniel",
        "last_name": "Schwierzeck",
        "email": "daniel.schwierzeck@googlemail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-6-sr@denx.de/mbox/",
    "series": [
        {
            "id": 220054,
            "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054",
            "date": "2020-12-11T16:05:23",
            "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1415038/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1415038/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<u-boot-bounces@lists.denx.de>",
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        "From": "Stefan Roese <sr@denx.de>",
        "To": "u-boot@lists.denx.de",
        "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com",
        "Subject": "[PATCH v1 05/50] mips: octeon: Add cvmx-bgxx-defs.h header file",
        "Date": "Fri, 11 Dec 2020 17:05:27 +0100",
        "Message-Id": "<20201211160612.1498780-6-sr@denx.de>",
        "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>",
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    },
    "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-bgxx-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-bgxx-defs.h | 4106 +++++++++++++++++\n 1 file changed, 4106 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-bgxx-defs.h",
    "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-bgxx-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-bgxx-defs.h\nnew file mode 100644\nindex 0000000000..7bcf805827\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-bgxx-defs.h\n@@ -0,0 +1,4106 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon bgxx.\n+ */\n+\n+#ifndef __CVMX_BGXX_DEFS_H__\n+#define __CVMX_BGXX_DEFS_H__\n+\n+#define CVMX_BGXX_CMRX_CONFIG(offset, block_id)                                                    \\\n+\t(0x00011800E0000000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_INT(offset, block_id)                                                       \\\n+\t(0x00011800E0000020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_PRT_CBFC_CTL(offset, block_id)                                              \\\n+\t(0x00011800E0000408ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_ADR_CTL(offset, block_id)                                                \\\n+\t(0x00011800E00000A0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_BP_DROP(offset, block_id)                                                \\\n+\t(0x00011800E0000080ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_BP_OFF(offset, block_id)                                                 \\\n+\t(0x00011800E0000090ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_BP_ON(offset, block_id)                                                  \\\n+\t(0x00011800E0000088ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_BP_STATUS(offset, block_id)                                              \\\n+\t(0x00011800E00000A8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_FIFO_LEN(offset, block_id)                                               \\\n+\t(0x00011800E00000C0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_ID_MAP(offset, block_id)                                                 \\\n+\t(0x00011800E0000028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_LOGL_XOFF(offset, block_id)                                              \\\n+\t(0x00011800E00000B0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_LOGL_XON(offset, block_id)                                               \\\n+\t(0x00011800E00000B8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_PAUSE_DROP_TIME(offset, block_id)                                        \\\n+\t(0x00011800E0000030ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_STAT0(offset, block_id)                                                  \\\n+\t(0x00011800E0000038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_STAT1(offset, block_id)                                                  \\\n+\t(0x00011800E0000040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_STAT2(offset, block_id)                                                  \\\n+\t(0x00011800E0000048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_STAT3(offset, block_id)                                                  \\\n+\t(0x00011800E0000050ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_STAT4(offset, block_id)                                                  \\\n+\t(0x00011800E0000058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_STAT5(offset, block_id)                                                  \\\n+\t(0x00011800E0000060ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_STAT6(offset, block_id)                                                  \\\n+\t(0x00011800E0000068ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_STAT7(offset, block_id)                                                  \\\n+\t(0x00011800E0000070ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_STAT8(offset, block_id)                                                  \\\n+\t(0x00011800E0000078ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_RX_WEIGHT(offset, block_id)                                                 \\\n+\t(0x00011800E0000098ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_CHANNEL(offset, block_id)                                                \\\n+\t(0x00011800E0000400ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_FIFO_LEN(offset, block_id)                                               \\\n+\t(0x00011800E0000418ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_HG2_STATUS(offset, block_id)                                             \\\n+\t(0x00011800E0000410ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_OVR_BP(offset, block_id)                                                 \\\n+\t(0x00011800E0000420ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT0(offset, block_id)                                                  \\\n+\t(0x00011800E0000508ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT1(offset, block_id)                                                  \\\n+\t(0x00011800E0000510ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT10(offset, block_id)                                                 \\\n+\t(0x00011800E0000558ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT11(offset, block_id)                                                 \\\n+\t(0x00011800E0000560ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT12(offset, block_id)                                                 \\\n+\t(0x00011800E0000568ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT13(offset, block_id)                                                 \\\n+\t(0x00011800E0000570ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT14(offset, block_id)                                                 \\\n+\t(0x00011800E0000578ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT15(offset, block_id)                                                 \\\n+\t(0x00011800E0000580ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT16(offset, block_id)                                                 \\\n+\t(0x00011800E0000588ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT17(offset, block_id)                                                 \\\n+\t(0x00011800E0000590ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT2(offset, block_id)                                                  \\\n+\t(0x00011800E0000518ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT3(offset, block_id)                                                  \\\n+\t(0x00011800E0000520ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT4(offset, block_id)                                                  \\\n+\t(0x00011800E0000528ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT5(offset, block_id)                                                  \\\n+\t(0x00011800E0000530ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT6(offset, block_id)                                                  \\\n+\t(0x00011800E0000538ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT7(offset, block_id)                                                  \\\n+\t(0x00011800E0000540ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT8(offset, block_id)                                                  \\\n+\t(0x00011800E0000548ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMRX_TX_STAT9(offset, block_id)                                                  \\\n+\t(0x00011800E0000550ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_CMR_BAD(offset)\t    (0x00011800E0001020ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_CMR_BIST_STATUS(offset)   (0x00011800E0000300ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_CMR_CHAN_MSK_AND(offset)  (0x00011800E0000200ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_CMR_CHAN_MSK_OR(offset)   (0x00011800E0000208ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_CMR_ECO(offset)\t    (0x00011800E0001028ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_CMR_GLOBAL_CONFIG(offset) (0x00011800E0000008ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_CMR_MEM_CTRL(offset)\t    (0x00011800E0000018ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_CMR_MEM_INT(offset)\t    (0x00011800E0000010ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_CMR_NXC_ADR(offset)\t    (0x00011800E0001018ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_CMR_RX_ADRX_CAM(offset, block_id)                                                \\\n+\t(0x00011800E0000100ull + (((offset) & 31) + ((block_id) & 7) * 0x200000ull) * 8)\n+#define CVMX_BGXX_CMR_RX_LMACS(offset)\t(0x00011800E0000308ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_CMR_RX_OVR_BP(offset) (0x00011800E0000318ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_CMR_TX_LMACS(offset)\t(0x00011800E0001000ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_GMP_GMI_PRTX_CFG(offset, block_id)                                               \\\n+\t(0x00011800E0038010ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_RXX_DECISION(offset, block_id)                                           \\\n+\t(0x00011800E0038040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_RXX_FRM_CHK(offset, block_id)                                            \\\n+\t(0x00011800E0038020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_RXX_FRM_CTL(offset, block_id)                                            \\\n+\t(0x00011800E0038018ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_RXX_IFG(offset, block_id)                                                \\\n+\t(0x00011800E0038058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_RXX_INT(offset, block_id)                                                \\\n+\t(0x00011800E0038000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_RXX_JABBER(offset, block_id)                                             \\\n+\t(0x00011800E0038038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_RXX_UDD_SKP(offset, block_id)                                            \\\n+\t(0x00011800E0038048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_SMACX(offset, block_id)                                                  \\\n+\t(0x00011800E0038230ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_APPEND(offset, block_id)                                             \\\n+\t(0x00011800E0038218ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_BURST(offset, block_id)                                              \\\n+\t(0x00011800E0038228ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_CTL(offset, block_id)                                                \\\n+\t(0x00011800E0038270ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_INT(offset, block_id)                                                \\\n+\t(0x00011800E0038500ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_MIN_PKT(offset, block_id)                                            \\\n+\t(0x00011800E0038240ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(offset, block_id)                                 \\\n+\t(0x00011800E0038248ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(offset, block_id)                                     \\\n+\t(0x00011800E0038238ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_PAUSE_TOGO(offset, block_id)                                         \\\n+\t(0x00011800E0038258ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_PAUSE_ZERO(offset, block_id)                                         \\\n+\t(0x00011800E0038260ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_SGMII_CTL(offset, block_id)                                          \\\n+\t(0x00011800E0038300ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_SLOT(offset, block_id)                                               \\\n+\t(0x00011800E0038220ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_SOFT_PAUSE(offset, block_id)                                         \\\n+\t(0x00011800E0038250ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TXX_THRESH(offset, block_id)                                             \\\n+\t(0x00011800E0038210ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_GMI_TX_COL_ATTEMPT(offset)                                                   \\\n+\t(0x00011800E0039010ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_GMP_GMI_TX_IFG(offset)  (0x00011800E0039000ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_GMP_GMI_TX_JAM(offset)  (0x00011800E0039008ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_GMP_GMI_TX_LFSR(offset) (0x00011800E0039028ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(offset)                                                \\\n+\t(0x00011800E0039018ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(offset)                                                \\\n+\t(0x00011800E0039020ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_GMP_PCS_ANX_ADV(offset, block_id)                                                \\\n+\t(0x00011800E0030010ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_ANX_EXT_ST(offset, block_id)                                             \\\n+\t(0x00011800E0030028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_ANX_LP_ABIL(offset, block_id)                                            \\\n+\t(0x00011800E0030018ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_ANX_RESULTS(offset, block_id)                                            \\\n+\t(0x00011800E0030020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_INTX(offset, block_id)                                                   \\\n+\t(0x00011800E0030080ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_LINKX_TIMER(offset, block_id)                                            \\\n+\t(0x00011800E0030040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_MISCX_CTL(offset, block_id)                                              \\\n+\t(0x00011800E0030078ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_MRX_CONTROL(offset, block_id)                                            \\\n+\t(0x00011800E0030000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_MRX_STATUS(offset, block_id)                                             \\\n+\t(0x00011800E0030008ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_RXX_STATES(offset, block_id)                                             \\\n+\t(0x00011800E0030058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_RXX_SYNC(offset, block_id)                                               \\\n+\t(0x00011800E0030050ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_SGMX_AN_ADV(offset, block_id)                                            \\\n+\t(0x00011800E0030068ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_SGMX_LP_ADV(offset, block_id)                                            \\\n+\t(0x00011800E0030070ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_TXX_STATES(offset, block_id)                                             \\\n+\t(0x00011800E0030060ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_GMP_PCS_TX_RXX_POLARITY(offset, block_id)                                        \\\n+\t(0x00011800E0030048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_CBFC_CTL(offset, block_id)                                                  \\\n+\t(0x00011800E0020218ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_CTRL(offset, block_id)                                                      \\\n+\t(0x00011800E0020200ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_EXT_LOOPBACK(offset, block_id)                                              \\\n+\t(0x00011800E0020208ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_HG2_CONTROL(offset, block_id)                                               \\\n+\t(0x00011800E0020210ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_RX_BAD_COL_HI(offset, block_id)                                             \\\n+\t(0x00011800E0020040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_RX_BAD_COL_LO(offset, block_id)                                             \\\n+\t(0x00011800E0020038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_RX_CTL(offset, block_id)                                                    \\\n+\t(0x00011800E0020030ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_RX_DECISION(offset, block_id)                                               \\\n+\t(0x00011800E0020020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_RX_FRM_CHK(offset, block_id)                                                \\\n+\t(0x00011800E0020010ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_RX_FRM_CTL(offset, block_id)                                                \\\n+\t(0x00011800E0020008ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_RX_INT(offset, block_id)                                                    \\\n+\t(0x00011800E0020000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_RX_JABBER(offset, block_id)                                                 \\\n+\t(0x00011800E0020018ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_RX_UDD_SKP(offset, block_id)                                                \\\n+\t(0x00011800E0020028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_SMAC(offset, block_id)                                                      \\\n+\t(0x00011800E0020108ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_APPEND(offset, block_id)                                                 \\\n+\t(0x00011800E0020100ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_CTL(offset, block_id)                                                    \\\n+\t(0x00011800E0020160ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_IFG(offset, block_id)                                                    \\\n+\t(0x00011800E0020148ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_INT(offset, block_id)                                                    \\\n+\t(0x00011800E0020140ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_MIN_PKT(offset, block_id)                                                \\\n+\t(0x00011800E0020118ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_PAUSE_PKT_DMAC(offset, block_id)                                         \\\n+\t(0x00011800E0020150ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_PAUSE_PKT_INTERVAL(offset, block_id)                                     \\\n+\t(0x00011800E0020120ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_PAUSE_PKT_TIME(offset, block_id)                                         \\\n+\t(0x00011800E0020110ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_PAUSE_PKT_TYPE(offset, block_id)                                         \\\n+\t(0x00011800E0020158ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_PAUSE_TOGO(offset, block_id)                                             \\\n+\t(0x00011800E0020130ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_PAUSE_ZERO(offset, block_id)                                             \\\n+\t(0x00011800E0020138ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_SOFT_PAUSE(offset, block_id)                                             \\\n+\t(0x00011800E0020128ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SMUX_TX_THRESH(offset, block_id)                                                 \\\n+\t(0x00011800E0020168ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_AN_ADV(offset, block_id)                                                    \\\n+\t(0x00011800E00100D8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_AN_BP_STATUS(offset, block_id)                                              \\\n+\t(0x00011800E00100F8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_AN_CONTROL(offset, block_id)                                                \\\n+\t(0x00011800E00100C8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_AN_LP_BASE(offset, block_id)                                                \\\n+\t(0x00011800E00100E0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_AN_LP_XNP(offset, block_id)                                                 \\\n+\t(0x00011800E00100F0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_AN_STATUS(offset, block_id)                                                 \\\n+\t(0x00011800E00100D0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_AN_XNP_TX(offset, block_id)                                                 \\\n+\t(0x00011800E00100E8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_ALGN_STATUS(offset, block_id)                                            \\\n+\t(0x00011800E0010050ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_BIP_ERR_CNT(offset, block_id)                                            \\\n+\t(0x00011800E0010058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_LANE_MAP(offset, block_id)                                               \\\n+\t(0x00011800E0010060ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_PMD_CONTROL(offset, block_id)                                            \\\n+\t(0x00011800E0010068ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_PMD_LD_CUP(offset, block_id)                                             \\\n+\t(0x00011800E0010088ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_PMD_LD_REP(offset, block_id)                                             \\\n+\t(0x00011800E0010090ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_PMD_LP_CUP(offset, block_id)                                             \\\n+\t(0x00011800E0010078ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_PMD_LP_REP(offset, block_id)                                             \\\n+\t(0x00011800E0010080ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_PMD_STATUS(offset, block_id)                                             \\\n+\t(0x00011800E0010070ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_STATUS1(offset, block_id)                                                \\\n+\t(0x00011800E0010030ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_STATUS2(offset, block_id)                                                \\\n+\t(0x00011800E0010038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_TP_CONTROL(offset, block_id)                                             \\\n+\t(0x00011800E0010040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BR_TP_ERR_CNT(offset, block_id)                                             \\\n+\t(0x00011800E0010048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_BX_STATUS(offset, block_id)                                                 \\\n+\t(0x00011800E0010028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_CONTROL1(offset, block_id)                                                  \\\n+\t(0x00011800E0010000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_CONTROL2(offset, block_id)                                                  \\\n+\t(0x00011800E0010018ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_FEC_ABIL(offset, block_id)                                                  \\\n+\t(0x00011800E0010098ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_FEC_CONTROL(offset, block_id)                                               \\\n+\t(0x00011800E00100A0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_FEC_CORR_BLKS01(offset, block_id)                                           \\\n+\t(0x00011800E00100A8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_FEC_CORR_BLKS23(offset, block_id)                                           \\\n+\t(0x00011800E00100B0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_FEC_UNCORR_BLKS01(offset, block_id)                                         \\\n+\t(0x00011800E00100B8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_FEC_UNCORR_BLKS23(offset, block_id)                                         \\\n+\t(0x00011800E00100C0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_INT(offset, block_id)                                                       \\\n+\t(0x00011800E0010220ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_LPCS_STATES(offset, block_id)                                               \\\n+\t(0x00011800E0010208ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_MISC_CONTROL(offset, block_id)                                              \\\n+\t(0x00011800E0010218ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_SPD_ABIL(offset, block_id)                                                  \\\n+\t(0x00011800E0010010ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_STATUS1(offset, block_id)                                                   \\\n+\t(0x00011800E0010008ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPUX_STATUS2(offset, block_id)                                                   \\\n+\t(0x00011800E0010020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)\n+#define CVMX_BGXX_SPU_BIST_STATUS(offset) (0x00011800E0010318ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_SPU_DBG_CONTROL(offset) (0x00011800E0010300ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_SPU_MEM_INT(offset)\t  (0x00011800E0010310ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_SPU_MEM_STATUS(offset)  (0x00011800E0010308ull + ((offset) & 7) * 0x1000000ull)\n+#define CVMX_BGXX_SPU_SDSX_SKEW_STATUS(offset, block_id)                                           \\\n+\t(0x00011800E0010320ull + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8)\n+#define CVMX_BGXX_SPU_SDSX_STATES(offset, block_id)                                                \\\n+\t(0x00011800E0010340ull + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8)\n+\n+/**\n+ * cvmx_bgx#_cmr#_config\n+ *\n+ * Logical MAC/PCS configuration registers; one per LMAC. The maximum number of LMACs (and\n+ * maximum LMAC ID) that can be enabled by these registers is limited by\n+ * BGX()_CMR_RX_LMACS[LMACS] and BGX()_CMR_TX_LMACS[LMACS]. When multiple LMACs are\n+ * enabled, they must be configured with the same [LMAC_TYPE] value.\n+ */\n+union cvmx_bgxx_cmrx_config {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_config_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 enable : 1;\n+\t\tu64 data_pkt_rx_en : 1;\n+\t\tu64 data_pkt_tx_en : 1;\n+\t\tu64 int_beat_gen : 1;\n+\t\tu64 mix_en : 1;\n+\t\tu64 lmac_type : 3;\n+\t\tu64 lane_to_sds : 8;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_config_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_config_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_config_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_config_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_config cvmx_bgxx_cmrx_config_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_int\n+ */\n+union cvmx_bgxx_cmrx_int {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_int_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 pko_nxc : 1;\n+\t\tu64 overflw : 1;\n+\t\tu64 pause_drp : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_int_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_int_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_int_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_int cvmx_bgxx_cmrx_int_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_prt_cbfc_ctl\n+ *\n+ * See XOFF definition listed under BGX()_SMU()_CBFC_CTL.\n+ *\n+ */\n+union cvmx_bgxx_cmrx_prt_cbfc_ctl {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_prt_cbfc_ctl_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 phys_bp : 16;\n+\t\tu64 reserved_0_15 : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_prt_cbfc_ctl_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_prt_cbfc_ctl_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_prt_cbfc_ctl_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_prt_cbfc_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_prt_cbfc_ctl cvmx_bgxx_cmrx_prt_cbfc_ctl_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_adr_ctl\n+ */\n+union cvmx_bgxx_cmrx_rx_adr_ctl {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_adr_ctl_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 cam_accept : 1;\n+\t\tu64 mcst_mode : 2;\n+\t\tu64 bcst_accept : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_adr_ctl_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_adr_ctl_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_adr_ctl_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_adr_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_adr_ctl cvmx_bgxx_cmrx_rx_adr_ctl_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_bp_drop\n+ */\n+union cvmx_bgxx_cmrx_rx_bp_drop {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_drop_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 mark : 7;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_drop_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_drop_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_drop_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_drop_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_bp_drop cvmx_bgxx_cmrx_rx_bp_drop_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_bp_off\n+ */\n+union cvmx_bgxx_cmrx_rx_bp_off {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_off_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 mark : 7;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_off_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_off_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_off_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_off_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_bp_off cvmx_bgxx_cmrx_rx_bp_off_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_bp_on\n+ */\n+union cvmx_bgxx_cmrx_rx_bp_on {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_on_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 mark : 12;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_on_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_on_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_on_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_on_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_bp_on cvmx_bgxx_cmrx_rx_bp_on_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_bp_status\n+ */\n+union cvmx_bgxx_cmrx_rx_bp_status {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_status_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 bp : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_status_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_status_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_status_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_bp_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_bp_status cvmx_bgxx_cmrx_rx_bp_status_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_fifo_len\n+ */\n+union cvmx_bgxx_cmrx_rx_fifo_len {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_fifo_len_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 fifo_len : 13;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_fifo_len_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_fifo_len_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_fifo_len_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_fifo_len_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_fifo_len cvmx_bgxx_cmrx_rx_fifo_len_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_id_map\n+ *\n+ * These registers set the RX LMAC ID mapping for X2P/PKI.\n+ *\n+ */\n+union cvmx_bgxx_cmrx_rx_id_map {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_id_map_s {\n+\t\tu64 reserved_15_63 : 49;\n+\t\tu64 rid : 7;\n+\t\tu64 pknd : 8;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_id_map_cn73xx {\n+\t\tu64 reserved_15_63 : 49;\n+\t\tu64 rid : 7;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 pknd : 6;\n+\t} cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_id_map_cn73xx cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_id_map_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_id_map_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_id_map cvmx_bgxx_cmrx_rx_id_map_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_logl_xoff\n+ */\n+union cvmx_bgxx_cmrx_rx_logl_xoff {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_logl_xoff_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 xoff : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_logl_xoff_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_logl_xoff_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_logl_xoff_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_logl_xoff_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_logl_xoff cvmx_bgxx_cmrx_rx_logl_xoff_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_logl_xon\n+ */\n+union cvmx_bgxx_cmrx_rx_logl_xon {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_logl_xon_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 xon : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_logl_xon_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_logl_xon_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_logl_xon_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_logl_xon_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_logl_xon cvmx_bgxx_cmrx_rx_logl_xon_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_pause_drop_time\n+ */\n+union cvmx_bgxx_cmrx_rx_pause_drop_time {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_pause_drop_time_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 pause_time : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_pause_drop_time_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_pause_drop_time_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_pause_drop_time_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_pause_drop_time_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_pause_drop_time cvmx_bgxx_cmrx_rx_pause_drop_time_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_stat0\n+ *\n+ * These registers provide a count of received packets that meet the following conditions:\n+ * * are not recognized as PAUSE packets.\n+ * * are not dropped due DMAC filtering.\n+ * * are not dropped due FIFO full status.\n+ * * do not have any other OPCODE (FCS, Length, etc).\n+ */\n+union cvmx_bgxx_cmrx_rx_stat0 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_stat0_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_stat0_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat0_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat0_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_stat0_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_stat0 cvmx_bgxx_cmrx_rx_stat0_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_stat1\n+ *\n+ * These registers provide a count of octets of received packets.\n+ *\n+ */\n+union cvmx_bgxx_cmrx_rx_stat1 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_stat1_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_stat1_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat1_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat1_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_stat1_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_stat1 cvmx_bgxx_cmrx_rx_stat1_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_stat2\n+ *\n+ * These registers provide a count of all packets received that were recognized as flow-control\n+ * or PAUSE packets. PAUSE packets with any kind of error are counted in\n+ * BGX()_CMR()_RX_STAT8 (error stats register). Pause packets can be optionally dropped\n+ * or forwarded based on BGX()_SMU()_RX_FRM_CTL[CTL_DRP]. This count increments\n+ * regardless of whether the packet is dropped. PAUSE packets are never counted in\n+ * BGX()_CMR()_RX_STAT0.\n+ */\n+union cvmx_bgxx_cmrx_rx_stat2 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_stat2_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_stat2_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat2_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat2_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_stat2_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_stat2 cvmx_bgxx_cmrx_rx_stat2_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_stat3\n+ *\n+ * These registers provide a count of octets of received PAUSE and control packets.\n+ *\n+ */\n+union cvmx_bgxx_cmrx_rx_stat3 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_stat3_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_stat3_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat3_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat3_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_stat3_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_stat3 cvmx_bgxx_cmrx_rx_stat3_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_stat4\n+ *\n+ * These registers provide a count of all packets received that were dropped by the DMAC filter.\n+ * Packets that match the DMAC are dropped and counted here regardless of whether they were ERR\n+ * packets, but does not include those reported in BGX()_CMR()_RX_STAT6. These packets\n+ * are never counted in BGX()_CMR()_RX_STAT0. Eight-byte packets as the result of\n+ * truncation or other means are not dropped by CNXXXX and will never appear in this count.\n+ */\n+union cvmx_bgxx_cmrx_rx_stat4 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_stat4_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_stat4_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat4_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat4_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_stat4_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_stat4 cvmx_bgxx_cmrx_rx_stat4_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_stat5\n+ *\n+ * These registers provide a count of octets of filtered DMAC packets.\n+ *\n+ */\n+union cvmx_bgxx_cmrx_rx_stat5 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_stat5_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_stat5_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat5_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat5_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_stat5_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_stat5 cvmx_bgxx_cmrx_rx_stat5_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_stat6\n+ *\n+ * These registers provide a count of all packets received that were dropped due to a full\n+ * receive FIFO. They do not count any packet that is truncated at the point of overflow and sent\n+ * on to the PKI. These registers count all entire packets dropped by the FIFO for a given LMAC\n+ * regardless of DMAC or PAUSE type.\n+ */\n+union cvmx_bgxx_cmrx_rx_stat6 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_stat6_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_stat6_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat6_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat6_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_stat6_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_stat6 cvmx_bgxx_cmrx_rx_stat6_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_stat7\n+ *\n+ * These registers provide a count of octets of received packets that were dropped due to a full\n+ * receive FIFO.\n+ */\n+union cvmx_bgxx_cmrx_rx_stat7 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_stat7_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_stat7_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat7_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat7_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_stat7_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_stat7 cvmx_bgxx_cmrx_rx_stat7_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_stat8\n+ *\n+ * These registers provide a count of all packets received with some error that were not dropped\n+ * either due to the DMAC filter or lack of room in the receive FIFO.\n+ * This does not include packets which were counted in\n+ * BGX()_CMR()_RX_STAT2, BGX()_CMR()_RX_STAT4 nor\n+ * BGX()_CMR()_RX_STAT6.\n+ *\n+ * Which statistics are updated on control packet errors and drops are shown below:\n+ *\n+ * <pre>\n+ * if dropped [\n+ *   if !errored STAT8\n+ *   if overflow STAT6\n+ *   else if dmac drop STAT4\n+ *   else if filter drop STAT2\n+ * ] else [\n+ *   if errored STAT2\n+ *   else STAT8\n+ * ]\n+ * </pre>\n+ */\n+union cvmx_bgxx_cmrx_rx_stat8 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_stat8_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_stat8_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat8_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_stat8_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_stat8_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_stat8 cvmx_bgxx_cmrx_rx_stat8_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_rx_weight\n+ */\n+union cvmx_bgxx_cmrx_rx_weight {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_rx_weight_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 weight : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_rx_weight_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_rx_weight_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_rx_weight_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_rx_weight_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_rx_weight cvmx_bgxx_cmrx_rx_weight_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_channel\n+ */\n+union cvmx_bgxx_cmrx_tx_channel {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_channel_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 msk : 16;\n+\t\tu64 dis : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_channel_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_channel_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_channel_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_channel_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_channel cvmx_bgxx_cmrx_tx_channel_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_fifo_len\n+ */\n+union cvmx_bgxx_cmrx_tx_fifo_len {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_fifo_len_s {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 lmac_idle : 1;\n+\t\tu64 fifo_len : 13;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_fifo_len_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_fifo_len_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_fifo_len_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_fifo_len_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_fifo_len cvmx_bgxx_cmrx_tx_fifo_len_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_hg2_status\n+ */\n+union cvmx_bgxx_cmrx_tx_hg2_status {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_hg2_status_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 xof : 16;\n+\t\tu64 lgtim2go : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_hg2_status_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_hg2_status_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_hg2_status_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_hg2_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_hg2_status cvmx_bgxx_cmrx_tx_hg2_status_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_ovr_bp\n+ */\n+union cvmx_bgxx_cmrx_tx_ovr_bp {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_ovr_bp_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 tx_chan_bp : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_ovr_bp_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_ovr_bp_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_ovr_bp_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_ovr_bp_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_ovr_bp cvmx_bgxx_cmrx_tx_ovr_bp_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat0\n+ */\n+union cvmx_bgxx_cmrx_tx_stat0 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat0_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 xscol : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat0_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat0_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat0_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat0_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat0 cvmx_bgxx_cmrx_tx_stat0_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat1\n+ */\n+union cvmx_bgxx_cmrx_tx_stat1 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat1_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 xsdef : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat1_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat1_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat1_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat1_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat1 cvmx_bgxx_cmrx_tx_stat1_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat10\n+ */\n+union cvmx_bgxx_cmrx_tx_stat10 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat10_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 hist4 : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat10_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat10_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat10_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat10_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat10 cvmx_bgxx_cmrx_tx_stat10_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat11\n+ */\n+union cvmx_bgxx_cmrx_tx_stat11 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat11_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 hist5 : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat11_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat11_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat11_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat11_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat11 cvmx_bgxx_cmrx_tx_stat11_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat12\n+ */\n+union cvmx_bgxx_cmrx_tx_stat12 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat12_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 hist6 : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat12_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat12_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat12_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat12_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat12 cvmx_bgxx_cmrx_tx_stat12_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat13\n+ */\n+union cvmx_bgxx_cmrx_tx_stat13 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat13_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 hist7 : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat13_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat13_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat13_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat13_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat13 cvmx_bgxx_cmrx_tx_stat13_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat14\n+ */\n+union cvmx_bgxx_cmrx_tx_stat14 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat14_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 bcst : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat14_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat14_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat14_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat14_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat14 cvmx_bgxx_cmrx_tx_stat14_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat15\n+ */\n+union cvmx_bgxx_cmrx_tx_stat15 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat15_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 mcst : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat15_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat15_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat15_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat15_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat15 cvmx_bgxx_cmrx_tx_stat15_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat16\n+ */\n+union cvmx_bgxx_cmrx_tx_stat16 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat16_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 undflw : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat16_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat16_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat16_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat16_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat16 cvmx_bgxx_cmrx_tx_stat16_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat17\n+ */\n+union cvmx_bgxx_cmrx_tx_stat17 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat17_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 ctl : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat17_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat17_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat17_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat17_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat17 cvmx_bgxx_cmrx_tx_stat17_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat2\n+ */\n+union cvmx_bgxx_cmrx_tx_stat2 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat2_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 mcol : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat2_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat2_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat2_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat2_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat2 cvmx_bgxx_cmrx_tx_stat2_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat3\n+ */\n+union cvmx_bgxx_cmrx_tx_stat3 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat3_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 scol : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat3_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat3_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat3_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat3_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat3 cvmx_bgxx_cmrx_tx_stat3_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat4\n+ */\n+union cvmx_bgxx_cmrx_tx_stat4 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat4_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 octs : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat4_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat4_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat4_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat4_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat4 cvmx_bgxx_cmrx_tx_stat4_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat5\n+ */\n+union cvmx_bgxx_cmrx_tx_stat5 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat5_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 pkts : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat5_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat5_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat5_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat5_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat5 cvmx_bgxx_cmrx_tx_stat5_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat6\n+ */\n+union cvmx_bgxx_cmrx_tx_stat6 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat6_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 hist0 : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat6_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat6_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat6_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat6_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat6 cvmx_bgxx_cmrx_tx_stat6_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat7\n+ */\n+union cvmx_bgxx_cmrx_tx_stat7 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat7_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 hist1 : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat7_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat7_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat7_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat7_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat7 cvmx_bgxx_cmrx_tx_stat7_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat8\n+ */\n+union cvmx_bgxx_cmrx_tx_stat8 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat8_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 hist2 : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat8_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat8_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat8_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat8_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat8 cvmx_bgxx_cmrx_tx_stat8_t;\n+\n+/**\n+ * cvmx_bgx#_cmr#_tx_stat9\n+ */\n+union cvmx_bgxx_cmrx_tx_stat9 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmrx_tx_stat9_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 hist3 : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmrx_tx_stat9_s cn73xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat9_s cn78xx;\n+\tstruct cvmx_bgxx_cmrx_tx_stat9_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmrx_tx_stat9_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmrx_tx_stat9 cvmx_bgxx_cmrx_tx_stat9_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_bad\n+ */\n+union cvmx_bgxx_cmr_bad {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_bad_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 rxb_nxl : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_bad_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_bad_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_bad_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmr_bad_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_bad cvmx_bgxx_cmr_bad_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_bist_status\n+ */\n+union cvmx_bgxx_cmr_bist_status {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_bist_status_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 status : 25;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_bist_status_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_bist_status_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_bist_status_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmr_bist_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_bist_status cvmx_bgxx_cmr_bist_status_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_chan_msk_and\n+ */\n+union cvmx_bgxx_cmr_chan_msk_and {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_chan_msk_and_s {\n+\t\tu64 msk_and : 64;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_chan_msk_and_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_chan_msk_and_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_chan_msk_and_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmr_chan_msk_and_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_chan_msk_and cvmx_bgxx_cmr_chan_msk_and_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_chan_msk_or\n+ */\n+union cvmx_bgxx_cmr_chan_msk_or {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_chan_msk_or_s {\n+\t\tu64 msk_or : 64;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_chan_msk_or_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_chan_msk_or_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_chan_msk_or_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmr_chan_msk_or_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_chan_msk_or cvmx_bgxx_cmr_chan_msk_or_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_eco\n+ */\n+union cvmx_bgxx_cmr_eco {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_eco_s {\n+\t\tu64 eco_ro : 32;\n+\t\tu64 eco_rw : 32;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_eco_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_eco_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_eco_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_eco cvmx_bgxx_cmr_eco_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_global_config\n+ *\n+ * These registers configure the global CMR, PCS, and MAC.\n+ *\n+ */\n+union cvmx_bgxx_cmr_global_config {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_global_config_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 cmr_mix1_reset : 1;\n+\t\tu64 cmr_mix0_reset : 1;\n+\t\tu64 cmr_x2p_reset : 1;\n+\t\tu64 bgx_clk_enable : 1;\n+\t\tu64 pmux_sds_sel : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_global_config_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_global_config_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_global_config_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmr_global_config_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_global_config cvmx_bgxx_cmr_global_config_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_mem_ctrl\n+ */\n+union cvmx_bgxx_cmr_mem_ctrl {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_mem_ctrl_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 txb_skid_synd : 2;\n+\t\tu64 txb_skid_cor_dis : 1;\n+\t\tu64 txb_fif_bk1_syn : 2;\n+\t\tu64 txb_fif_bk1_cdis : 1;\n+\t\tu64 txb_fif_bk0_syn : 2;\n+\t\tu64 txb_fif_bk0_cdis : 1;\n+\t\tu64 rxb_skid_synd : 2;\n+\t\tu64 rxb_skid_cor_dis : 1;\n+\t\tu64 rxb_fif_bk1_syn1 : 2;\n+\t\tu64 rxb_fif_bk1_cdis1 : 1;\n+\t\tu64 rxb_fif_bk1_syn0 : 2;\n+\t\tu64 rxb_fif_bk1_cdis0 : 1;\n+\t\tu64 rxb_fif_bk0_syn1 : 2;\n+\t\tu64 rxb_fif_bk0_cdis1 : 1;\n+\t\tu64 rxb_fif_bk0_syn0 : 2;\n+\t\tu64 rxb_fif_bk0_cdis0 : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_mem_ctrl_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_mem_ctrl_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_mem_ctrl_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmr_mem_ctrl_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_mem_ctrl cvmx_bgxx_cmr_mem_ctrl_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_mem_int\n+ */\n+union cvmx_bgxx_cmr_mem_int {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_mem_int_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 smu_in_overfl : 1;\n+\t\tu64 gmp_in_overfl : 1;\n+\t\tu64 txb_skid_sbe : 1;\n+\t\tu64 txb_skid_dbe : 1;\n+\t\tu64 txb_fif_bk1_sbe : 1;\n+\t\tu64 txb_fif_bk1_dbe : 1;\n+\t\tu64 txb_fif_bk0_sbe : 1;\n+\t\tu64 txb_fif_bk0_dbe : 1;\n+\t\tu64 rxb_skid_sbe : 1;\n+\t\tu64 rxb_skid_dbe : 1;\n+\t\tu64 rxb_fif_bk1_sbe1 : 1;\n+\t\tu64 rxb_fif_bk1_dbe1 : 1;\n+\t\tu64 rxb_fif_bk1_sbe0 : 1;\n+\t\tu64 rxb_fif_bk1_dbe0 : 1;\n+\t\tu64 rxb_fif_bk0_sbe1 : 1;\n+\t\tu64 rxb_fif_bk0_dbe1 : 1;\n+\t\tu64 rxb_fif_bk0_sbe0 : 1;\n+\t\tu64 rxb_fif_bk0_dbe0 : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_mem_int_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_mem_int_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_mem_int_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmr_mem_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_mem_int cvmx_bgxx_cmr_mem_int_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_nxc_adr\n+ */\n+union cvmx_bgxx_cmr_nxc_adr {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_nxc_adr_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 lmac_id : 4;\n+\t\tu64 channel : 12;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_nxc_adr_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_nxc_adr_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_nxc_adr_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmr_nxc_adr_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_nxc_adr cvmx_bgxx_cmr_nxc_adr_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_rx_adr#_cam\n+ *\n+ * These registers provide access to the 32 DMAC CAM entries in BGX.\n+ *\n+ */\n+union cvmx_bgxx_cmr_rx_adrx_cam {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_rx_adrx_cam_s {\n+\t\tu64 reserved_54_63 : 10;\n+\t\tu64 id : 2;\n+\t\tu64 reserved_49_51 : 3;\n+\t\tu64 en : 1;\n+\t\tu64 adr : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_rx_adrx_cam_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_rx_adrx_cam_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_rx_adrx_cam_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmr_rx_adrx_cam_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_rx_adrx_cam cvmx_bgxx_cmr_rx_adrx_cam_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_rx_lmacs\n+ */\n+union cvmx_bgxx_cmr_rx_lmacs {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_rx_lmacs_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 lmacs : 3;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_rx_lmacs_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_rx_lmacs_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_rx_lmacs_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmr_rx_lmacs_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_rx_lmacs cvmx_bgxx_cmr_rx_lmacs_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_rx_ovr_bp\n+ *\n+ * BGX()_CMR_RX_OVR_BP[EN<0>] must be set to one and BGX()_CMR_RX_OVR_BP[BP<0>] must be\n+ * cleared to zero (to forcibly disable hardware-automatic 802.3 PAUSE packet generation) with\n+ * the HiGig2 Protocol when BGX()_SMU()_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is\n+ * indicated by BGX()_SMU()_TX_CTL[HG_EN]=1 and BGX()_SMU()_RX_UDD_SKP[LEN]=16).\n+ * Hardware can only auto-generate backpressure through HiGig2 messages (optionally, when\n+ * BGX()_SMU()_HG2_CONTROL[HG2TX_EN]=1) with the HiGig2 protocol.\n+ */\n+union cvmx_bgxx_cmr_rx_ovr_bp {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_rx_ovr_bp_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 en : 4;\n+\t\tu64 bp : 4;\n+\t\tu64 ign_fifo_bp : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_rx_ovr_bp_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_rx_ovr_bp_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_rx_ovr_bp_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmr_rx_ovr_bp_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_rx_ovr_bp cvmx_bgxx_cmr_rx_ovr_bp_t;\n+\n+/**\n+ * cvmx_bgx#_cmr_tx_lmacs\n+ *\n+ * This register sets the number of LMACs allowed on the TX interface. The value is important for\n+ * defining the partitioning of the transmit FIFO.\n+ */\n+union cvmx_bgxx_cmr_tx_lmacs {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_cmr_tx_lmacs_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 lmacs : 3;\n+\t} s;\n+\tstruct cvmx_bgxx_cmr_tx_lmacs_s cn73xx;\n+\tstruct cvmx_bgxx_cmr_tx_lmacs_s cn78xx;\n+\tstruct cvmx_bgxx_cmr_tx_lmacs_s cn78xxp1;\n+\tstruct cvmx_bgxx_cmr_tx_lmacs_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_cmr_tx_lmacs cvmx_bgxx_cmr_tx_lmacs_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_prt#_cfg\n+ *\n+ * This register controls the configuration of the LMAC.\n+ *\n+ */\n+union cvmx_bgxx_gmp_gmi_prtx_cfg {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_prtx_cfg_s {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 tx_idle : 1;\n+\t\tu64 rx_idle : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 speed_msb : 1;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 slottime : 1;\n+\t\tu64 duplex : 1;\n+\t\tu64 speed : 1;\n+\t\tu64 reserved_0_0 : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_prtx_cfg_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_prtx_cfg_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_prtx_cfg_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_prtx_cfg_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_prtx_cfg cvmx_bgxx_gmp_gmi_prtx_cfg_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_rx#_decision\n+ *\n+ * This register specifies the byte count used to determine when to accept or to filter a packet.\n+ * As each byte in a packet is received by GMI, the L2 byte count is compared against\n+ * [CNT]. In normal operation, the L2 header begins after the\n+ * PREAMBLE + SFD (BGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK] = 1) and any optional UDD skip\n+ * data (BGX()_GMP_GMI_RX()_UDD_SKP[LEN]).\n+ */\n+union cvmx_bgxx_gmp_gmi_rxx_decision {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_decision_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 cnt : 5;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_decision_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_decision_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_decision_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_decision_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_rxx_decision cvmx_bgxx_gmp_gmi_rxx_decision_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_rx#_frm_chk\n+ */\n+union cvmx_bgxx_gmp_gmi_rxx_frm_chk {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_frm_chk_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_frm_chk_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_frm_chk_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_frm_chk_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_frm_chk_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_rxx_frm_chk cvmx_bgxx_gmp_gmi_rxx_frm_chk_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_rx#_frm_ctl\n+ *\n+ * This register controls the handling of the frames.\n+ * The [CTL_BCK] and [CTL_DRP] bits control how the hardware handles incoming PAUSE packets. The\n+ * most\n+ * common modes of operation:\n+ * _ [CTL_BCK] = 1, [CTL_DRP] = 1: hardware handles everything.\n+ * _ [CTL_BCK] = 0, [CTL_DRP] = 0: software sees all PAUSE frames.\n+ * _ [CTL_BCK] = 0, [CTL_DRP] = 1: all PAUSE frames are completely ignored.\n+ *\n+ * These control bits should be set to [CTL_BCK] = 0, [CTL_DRP] = 0 in half-duplex mode. Since\n+ * PAUSE\n+ * packets only apply to full duplex operation, any PAUSE packet would constitute an exception\n+ * which should be handled by the processing cores. PAUSE packets should not be forwarded.\n+ */\n+union cvmx_bgxx_gmp_gmi_rxx_frm_ctl {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_frm_ctl_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 ptp_mode : 1;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 null_dis : 1;\n+\t\tu64 pre_align : 1;\n+\t\tu64 reserved_7_8 : 2;\n+\t\tu64 pre_free : 1;\n+\t\tu64 ctl_smac : 1;\n+\t\tu64 ctl_mcst : 1;\n+\t\tu64 ctl_bck : 1;\n+\t\tu64 ctl_drp : 1;\n+\t\tu64 pre_strp : 1;\n+\t\tu64 pre_chk : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_frm_ctl_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_frm_ctl_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_frm_ctl_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_frm_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_rxx_frm_ctl cvmx_bgxx_gmp_gmi_rxx_frm_ctl_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_rx#_ifg\n+ *\n+ * This register specifies the minimum number of interframe-gap (IFG) cycles between packets.\n+ *\n+ */\n+union cvmx_bgxx_gmp_gmi_rxx_ifg {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_ifg_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 ifg : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_ifg_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_ifg_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_ifg_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_ifg_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_rxx_ifg cvmx_bgxx_gmp_gmi_rxx_ifg_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_rx#_int\n+ *\n+ * '\"These registers allow interrupts to be sent to the control processor.\n+ * * Exception conditions <10:0> can also set the rcv/opcode in the received packet's work-queue\n+ * entry. BGX()_GMP_GMI_RX()_FRM_CHK provides a bit mask for configuring which conditions\n+ * set the error.\n+ * In half duplex operation, the expectation is that collisions will appear as either MINERR or\n+ * CAREXT errors.'\n+ */\n+union cvmx_bgxx_gmp_gmi_rxx_int {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_int_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_int_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_int_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_int_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_rxx_int cvmx_bgxx_gmp_gmi_rxx_int_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_rx#_jabber\n+ *\n+ * This register specifies the maximum size for packets, beyond which the GMI truncates.\n+ *\n+ */\n+union cvmx_bgxx_gmp_gmi_rxx_jabber {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_jabber_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 cnt : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_jabber_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_jabber_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_jabber_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_jabber_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_rxx_jabber cvmx_bgxx_gmp_gmi_rxx_jabber_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_rx#_udd_skp\n+ *\n+ * This register specifies the amount of user-defined data (UDD) added before the start of the\n+ * L2C data.\n+ */\n+union cvmx_bgxx_gmp_gmi_rxx_udd_skp {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_udd_skp_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 fcssel : 1;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 len : 7;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_udd_skp_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_udd_skp_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_udd_skp_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_rxx_udd_skp_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_rxx_udd_skp cvmx_bgxx_gmp_gmi_rxx_udd_skp_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_smac#\n+ */\n+union cvmx_bgxx_gmp_gmi_smacx {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_smacx_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 smac : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_smacx_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_smacx_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_smacx_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_smacx_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_smacx cvmx_bgxx_gmp_gmi_smacx_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_append\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_append {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_append_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 force_fcs : 1;\n+\t\tu64 fcs : 1;\n+\t\tu64 pad : 1;\n+\t\tu64 preamble : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_append_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_append_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_append_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_append_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_append cvmx_bgxx_gmp_gmi_txx_append_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_burst\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_burst {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_burst_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 burst : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_burst_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_burst_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_burst_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_burst_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_burst cvmx_bgxx_gmp_gmi_txx_burst_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_ctl\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_ctl_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 xsdef_en : 1;\n+\t\tu64 xscol_en : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_ctl_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_ctl_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_ctl_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_ctl cvmx_bgxx_gmp_gmi_txx_ctl_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_int\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_int {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_int_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 ptp_lost : 1;\n+\t\tu64 late_col : 1;\n+\t\tu64 xsdef : 1;\n+\t\tu64 xscol : 1;\n+\t\tu64 undflw : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_int_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_int_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_int_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_int cvmx_bgxx_gmp_gmi_txx_int_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_min_pkt\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_min_pkt {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_min_pkt_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 min_size : 8;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_min_pkt_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_min_pkt_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_min_pkt_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_min_pkt_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_min_pkt cvmx_bgxx_gmp_gmi_txx_min_pkt_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_pause_pkt_interval\n+ *\n+ * This register specifies how often PAUSE packets are sent.\n+ *\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 interval : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval cvmx_bgxx_gmp_gmi_txx_pause_pkt_interval_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_pause_pkt_time\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_pause_pkt_time {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_pkt_time_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 ptime : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_pkt_time_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_pkt_time_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_pkt_time_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_pkt_time_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_pause_pkt_time cvmx_bgxx_gmp_gmi_txx_pause_pkt_time_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_pause_togo\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_pause_togo {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_togo_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 ptime : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_togo_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_togo_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_togo_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_togo_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_pause_togo cvmx_bgxx_gmp_gmi_txx_pause_togo_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_pause_zero\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_pause_zero {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_zero_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 send : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_zero_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_zero_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_zero_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_pause_zero_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_pause_zero cvmx_bgxx_gmp_gmi_txx_pause_zero_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_sgmii_ctl\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_sgmii_ctl {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_sgmii_ctl_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 align : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_sgmii_ctl_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_sgmii_ctl_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_sgmii_ctl_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_sgmii_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_sgmii_ctl cvmx_bgxx_gmp_gmi_txx_sgmii_ctl_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_slot\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_slot {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_slot_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 slot : 10;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_slot_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_slot_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_slot_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_slot_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_slot cvmx_bgxx_gmp_gmi_txx_slot_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_soft_pause\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_soft_pause {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_soft_pause_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 ptime : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_soft_pause_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_soft_pause_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_soft_pause_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_soft_pause_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_soft_pause cvmx_bgxx_gmp_gmi_txx_soft_pause_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx#_thresh\n+ */\n+union cvmx_bgxx_gmp_gmi_txx_thresh {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_thresh_s {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 cnt : 11;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_thresh_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_thresh_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_thresh_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_txx_thresh_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_txx_thresh cvmx_bgxx_gmp_gmi_txx_thresh_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx_col_attempt\n+ */\n+union cvmx_bgxx_gmp_gmi_tx_col_attempt {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_col_attempt_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 limit : 5;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_col_attempt_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_col_attempt_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_col_attempt_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_col_attempt_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_tx_col_attempt cvmx_bgxx_gmp_gmi_tx_col_attempt_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx_ifg\n+ *\n+ * Consider the following when programming IFG1 and IFG2:\n+ * * For 10/100/1000 Mb/s half-duplex systems that require IEEE 802.3 compatibility, IFG1 must be\n+ * in the range of 1-8, IFG2 must be in the range of 4-12, and the IFG1 + IFG2 sum must be 12.\n+ * * For 10/100/1000 Mb/s full-duplex systems that require IEEE 802.3 compatibility, IFG1 must be\n+ * in the range of 1-11, IFG2 must be in the range of 1-11, and the IFG1 + IFG2 sum must be 12.\n+ * For all other systems, IFG1 and IFG2 can be any value in the range of 1-15, allowing for a\n+ * total possible IFG sum of 2-30.\n+ */\n+union cvmx_bgxx_gmp_gmi_tx_ifg {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_ifg_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 ifg2 : 4;\n+\t\tu64 ifg1 : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_ifg_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_ifg_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_ifg_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_ifg_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_tx_ifg cvmx_bgxx_gmp_gmi_tx_ifg_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx_jam\n+ *\n+ * This register provides the pattern used in JAM bytes.\n+ *\n+ */\n+union cvmx_bgxx_gmp_gmi_tx_jam {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_jam_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 jam : 8;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_jam_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_jam_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_jam_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_jam_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_tx_jam cvmx_bgxx_gmp_gmi_tx_jam_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx_lfsr\n+ *\n+ * This register shows the contents of the linear feedback shift register (LFSR), which is used\n+ * to implement truncated binary exponential backoff.\n+ */\n+union cvmx_bgxx_gmp_gmi_tx_lfsr {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_lfsr_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 lfsr : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_lfsr_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_lfsr_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_lfsr_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_lfsr_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_tx_lfsr cvmx_bgxx_gmp_gmi_tx_lfsr_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx_pause_pkt_dmac\n+ */\n+union cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 dmac : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac cvmx_bgxx_gmp_gmi_tx_pause_pkt_dmac_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_gmi_tx_pause_pkt_type\n+ *\n+ * This register provides the PTYPE field that is placed in outbound PAUSE packets.\n+ *\n+ */\n+union cvmx_bgxx_gmp_gmi_tx_pause_pkt_type {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_pause_pkt_type_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 ptype : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_pause_pkt_type_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_pause_pkt_type_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_pause_pkt_type_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_gmi_tx_pause_pkt_type_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_gmi_tx_pause_pkt_type cvmx_bgxx_gmp_gmi_tx_pause_pkt_type_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_an#_adv\n+ */\n+union cvmx_bgxx_gmp_pcs_anx_adv {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_adv_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 np : 1;\n+\t\tu64 reserved_14_14 : 1;\n+\t\tu64 rem_flt : 2;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 pause : 2;\n+\t\tu64 hfd : 1;\n+\t\tu64 fd : 1;\n+\t\tu64 reserved_0_4 : 5;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_adv_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_adv_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_adv_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_adv_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_anx_adv cvmx_bgxx_gmp_pcs_anx_adv_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_an#_ext_st\n+ */\n+union cvmx_bgxx_gmp_pcs_anx_ext_st {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_ext_st_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 thou_xfd : 1;\n+\t\tu64 thou_xhd : 1;\n+\t\tu64 thou_tfd : 1;\n+\t\tu64 thou_thd : 1;\n+\t\tu64 reserved_0_11 : 12;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_ext_st_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_ext_st_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_ext_st_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_ext_st_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_anx_ext_st cvmx_bgxx_gmp_pcs_anx_ext_st_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_an#_lp_abil\n+ *\n+ * This is the autonegotiation link partner ability register 5 as per IEEE 802.3, Clause 37.\n+ *\n+ */\n+union cvmx_bgxx_gmp_pcs_anx_lp_abil {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_lp_abil_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 np : 1;\n+\t\tu64 ack : 1;\n+\t\tu64 rem_flt : 2;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 pause : 2;\n+\t\tu64 hfd : 1;\n+\t\tu64 fd : 1;\n+\t\tu64 reserved_0_4 : 5;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_lp_abil_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_lp_abil_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_lp_abil_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_lp_abil_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_anx_lp_abil cvmx_bgxx_gmp_pcs_anx_lp_abil_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_an#_results\n+ *\n+ * This register is not valid when BGX()_GMP_PCS_MISC()_CTL[AN_OVRD] is set to 1. If\n+ * BGX()_GMP_PCS_MISC()_CTL[AN_OVRD] is set to 0 and\n+ * BGX()_GMP_PCS_AN()_RESULTS[AN_CPT] is set to 1, this register is valid.\n+ */\n+union cvmx_bgxx_gmp_pcs_anx_results {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_results_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 pause : 2;\n+\t\tu64 spd : 2;\n+\t\tu64 an_cpt : 1;\n+\t\tu64 dup : 1;\n+\t\tu64 link_ok : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_results_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_results_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_results_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_anx_results_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_anx_results cvmx_bgxx_gmp_pcs_anx_results_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_int#\n+ */\n+union cvmx_bgxx_gmp_pcs_intx {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_intx_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 dbg_sync : 1;\n+\t\tu64 dup : 1;\n+\t\tu64 sync_bad : 1;\n+\t\tu64 an_bad : 1;\n+\t\tu64 rxlock : 1;\n+\t\tu64 rxbad : 1;\n+\t\tu64 rxerr : 1;\n+\t\tu64 txbad : 1;\n+\t\tu64 txfifo : 1;\n+\t\tu64 txfifu : 1;\n+\t\tu64 an_err : 1;\n+\t\tu64 xmit : 1;\n+\t\tu64 lnkspd : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_intx_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_intx_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_intx_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_intx_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_intx cvmx_bgxx_gmp_pcs_intx_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_link#_timer\n+ *\n+ * This is the 1.6 ms nominal link timer register.\n+ *\n+ */\n+union cvmx_bgxx_gmp_pcs_linkx_timer {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_linkx_timer_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 count : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_linkx_timer_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_linkx_timer_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_linkx_timer_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_linkx_timer_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_linkx_timer cvmx_bgxx_gmp_pcs_linkx_timer_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_misc#_ctl\n+ */\n+union cvmx_bgxx_gmp_pcs_miscx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_miscx_ctl_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 sgmii : 1;\n+\t\tu64 gmxeno : 1;\n+\t\tu64 loopbck2 : 1;\n+\t\tu64 mac_phy : 1;\n+\t\tu64 mode : 1;\n+\t\tu64 an_ovrd : 1;\n+\t\tu64 samp_pt : 7;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_miscx_ctl_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_miscx_ctl_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_miscx_ctl_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_miscx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_miscx_ctl cvmx_bgxx_gmp_pcs_miscx_ctl_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_mr#_control\n+ */\n+union cvmx_bgxx_gmp_pcs_mrx_control {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_mrx_control_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 reset : 1;\n+\t\tu64 loopbck1 : 1;\n+\t\tu64 spdlsb : 1;\n+\t\tu64 an_en : 1;\n+\t\tu64 pwr_dn : 1;\n+\t\tu64 reserved_10_10 : 1;\n+\t\tu64 rst_an : 1;\n+\t\tu64 dup : 1;\n+\t\tu64 coltst : 1;\n+\t\tu64 spdmsb : 1;\n+\t\tu64 uni : 1;\n+\t\tu64 reserved_0_4 : 5;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_mrx_control_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_mrx_control_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_mrx_control_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_mrx_control_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_mrx_control cvmx_bgxx_gmp_pcs_mrx_control_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_mr#_status\n+ *\n+ * Bits <15:9> in this register indicate the ability to operate when\n+ * BGX()_GMP_PCS_MISC()_CTL[MAC_PHY] is set to MAC mode. Bits <15:9> are always read as\n+ * 0, indicating that the chip cannot operate in the corresponding modes. The field [RM_FLT] is a\n+ * 'don't care' when the selected mode is SGMII.\n+ */\n+union cvmx_bgxx_gmp_pcs_mrx_status {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_mrx_status_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 hun_t4 : 1;\n+\t\tu64 hun_xfd : 1;\n+\t\tu64 hun_xhd : 1;\n+\t\tu64 ten_fd : 1;\n+\t\tu64 ten_hd : 1;\n+\t\tu64 hun_t2fd : 1;\n+\t\tu64 hun_t2hd : 1;\n+\t\tu64 ext_st : 1;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 prb_sup : 1;\n+\t\tu64 an_cpt : 1;\n+\t\tu64 rm_flt : 1;\n+\t\tu64 an_abil : 1;\n+\t\tu64 lnk_st : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 extnd : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_mrx_status_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_mrx_status_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_mrx_status_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_mrx_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_mrx_status cvmx_bgxx_gmp_pcs_mrx_status_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_rx#_states\n+ */\n+union cvmx_bgxx_gmp_pcs_rxx_states {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_rxx_states_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 rx_bad : 1;\n+\t\tu64 rx_st : 5;\n+\t\tu64 sync_bad : 1;\n+\t\tu64 sync : 4;\n+\t\tu64 an_bad : 1;\n+\t\tu64 an_st : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_rxx_states_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_rxx_states_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_rxx_states_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_rxx_states_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_rxx_states cvmx_bgxx_gmp_pcs_rxx_states_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_rx#_sync\n+ */\n+union cvmx_bgxx_gmp_pcs_rxx_sync {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_rxx_sync_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 sync : 1;\n+\t\tu64 bit_lock : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_rxx_sync_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_rxx_sync_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_rxx_sync_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_rxx_sync_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_rxx_sync cvmx_bgxx_gmp_pcs_rxx_sync_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_sgm#_an_adv\n+ *\n+ * This is the SGMII autonegotiation advertisement register (sent out as tx_Config_Reg<15:0> as\n+ * defined in IEEE 802.3 clause 37). This register is sent during autonegotiation if\n+ * BGX()_GMP_PCS_MISC()_CTL[MAC_PHY] is set (1 = PHY mode). If the bit is not set (0 =\n+ * MAC mode), then tx_Config_Reg<14> becomes ACK bit and tx_Config_Reg<0> is always 1. All other\n+ * bits in tx_Config_Reg sent will be 0. The PHY dictates the autonegotiation results.\n+ */\n+union cvmx_bgxx_gmp_pcs_sgmx_an_adv {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_sgmx_an_adv_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 link : 1;\n+\t\tu64 ack : 1;\n+\t\tu64 reserved_13_13 : 1;\n+\t\tu64 dup : 1;\n+\t\tu64 speed : 2;\n+\t\tu64 reserved_1_9 : 9;\n+\t\tu64 one : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_sgmx_an_adv_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_sgmx_an_adv_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_sgmx_an_adv_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_sgmx_an_adv_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_sgmx_an_adv cvmx_bgxx_gmp_pcs_sgmx_an_adv_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_sgm#_lp_adv\n+ *\n+ * This is the SGMII link partner advertisement register (received as rx_Config_Reg<15:0> as\n+ * defined in IEEE 802.3 clause 37).\n+ */\n+union cvmx_bgxx_gmp_pcs_sgmx_lp_adv {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_sgmx_lp_adv_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 link : 1;\n+\t\tu64 reserved_13_14 : 2;\n+\t\tu64 dup : 1;\n+\t\tu64 speed : 2;\n+\t\tu64 reserved_1_9 : 9;\n+\t\tu64 one : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_sgmx_lp_adv_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_sgmx_lp_adv_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_sgmx_lp_adv_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_sgmx_lp_adv_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_sgmx_lp_adv cvmx_bgxx_gmp_pcs_sgmx_lp_adv_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_tx#_states\n+ */\n+union cvmx_bgxx_gmp_pcs_txx_states {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_txx_states_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 xmit : 2;\n+\t\tu64 tx_bad : 1;\n+\t\tu64 ord_st : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_txx_states_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_txx_states_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_txx_states_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_txx_states_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_txx_states cvmx_bgxx_gmp_pcs_txx_states_t;\n+\n+/**\n+ * cvmx_bgx#_gmp_pcs_tx_rx#_polarity\n+ *\n+ * BGX()_GMP_PCS_TX_RX()_POLARITY[AUTORXPL] shows correct polarity needed on the link\n+ * receive path after code group synchronization is achieved.\n+ */\n+union cvmx_bgxx_gmp_pcs_tx_rxx_polarity {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_gmp_pcs_tx_rxx_polarity_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 rxovrd : 1;\n+\t\tu64 autorxpl : 1;\n+\t\tu64 rxplrt : 1;\n+\t\tu64 txplrt : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_gmp_pcs_tx_rxx_polarity_s cn73xx;\n+\tstruct cvmx_bgxx_gmp_pcs_tx_rxx_polarity_s cn78xx;\n+\tstruct cvmx_bgxx_gmp_pcs_tx_rxx_polarity_s cn78xxp1;\n+\tstruct cvmx_bgxx_gmp_pcs_tx_rxx_polarity_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_gmp_pcs_tx_rxx_polarity cvmx_bgxx_gmp_pcs_tx_rxx_polarity_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_cbfc_ctl\n+ */\n+union cvmx_bgxx_smux_cbfc_ctl {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_cbfc_ctl_s {\n+\t\tu64 phys_en : 16;\n+\t\tu64 logl_en : 16;\n+\t\tu64 reserved_4_31 : 28;\n+\t\tu64 bck_en : 1;\n+\t\tu64 drp_en : 1;\n+\t\tu64 tx_en : 1;\n+\t\tu64 rx_en : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_cbfc_ctl_s cn73xx;\n+\tstruct cvmx_bgxx_smux_cbfc_ctl_s cn78xx;\n+\tstruct cvmx_bgxx_smux_cbfc_ctl_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_cbfc_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_cbfc_ctl cvmx_bgxx_smux_cbfc_ctl_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_ctrl\n+ */\n+union cvmx_bgxx_smux_ctrl {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_ctrl_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 tx_idle : 1;\n+\t\tu64 rx_idle : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_ctrl_s cn73xx;\n+\tstruct cvmx_bgxx_smux_ctrl_s cn78xx;\n+\tstruct cvmx_bgxx_smux_ctrl_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_ctrl_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_ctrl cvmx_bgxx_smux_ctrl_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_ext_loopback\n+ *\n+ * In loopback mode, the IFG1+IFG2 of local and remote parties must match exactly; otherwise one\n+ * of the two sides' loopback FIFO will overrun: BGX()_SMU()_TX_INT[LB_OVRFLW].\n+ */\n+union cvmx_bgxx_smux_ext_loopback {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_ext_loopback_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 en : 1;\n+\t\tu64 thresh : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_ext_loopback_s cn73xx;\n+\tstruct cvmx_bgxx_smux_ext_loopback_s cn78xx;\n+\tstruct cvmx_bgxx_smux_ext_loopback_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_ext_loopback_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_ext_loopback cvmx_bgxx_smux_ext_loopback_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_hg2_control\n+ *\n+ * HiGig2 TX- and RX-enable are normally set together for HiGig2 messaging. Setting just the TX\n+ * or RX bit results in only the HG2 message transmit or receive capability.\n+ *\n+ * Setting [PHYS_EN] and [LOGL_EN] to 1 allows link PAUSE or backpressure to PKO as per the\n+ * received HiGig2 message. Setting these fields to 0 disables link PAUSE and backpressure to PKO\n+ * in response to received messages.\n+ *\n+ * BGX()_SMU()_TX_CTL[HG_EN] must be set (to enable HiGig) whenever either [HG2TX_EN] or\n+ * [HG2RX_EN] are set. BGX()_SMU()_RX_UDD_SKP[LEN] must be set to 16 (to select HiGig2)\n+ * whenever either [HG2TX_EN] or [HG2RX_EN] are set.\n+ *\n+ * BGX()_CMR_RX_OVR_BP[EN]<0> must be set and BGX()_CMR_RX_OVR_BP[BP]<0> must be cleared\n+ * to 0 (to forcibly disable hardware-automatic 802.3 PAUSE packet generation) with the HiGig2\n+ * Protocol when [HG2TX_EN] = 0. (The HiGig2 protocol is indicated\n+ * by BGX()_SMU()_TX_CTL[HG_EN] = 1 and BGX()_SMU()_RX_UDD_SKP[LEN]=16.) Hardware\n+ * can only autogenerate backpressure via HiGig2 messages (optionally, when [HG2TX_EN] = 1) with\n+ * the HiGig2 protocol.\n+ */\n+union cvmx_bgxx_smux_hg2_control {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_hg2_control_s {\n+\t\tu64 reserved_19_63 : 45;\n+\t\tu64 hg2tx_en : 1;\n+\t\tu64 hg2rx_en : 1;\n+\t\tu64 phys_en : 1;\n+\t\tu64 logl_en : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_hg2_control_s cn73xx;\n+\tstruct cvmx_bgxx_smux_hg2_control_s cn78xx;\n+\tstruct cvmx_bgxx_smux_hg2_control_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_hg2_control_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_hg2_control cvmx_bgxx_smux_hg2_control_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_rx_bad_col_hi\n+ */\n+union cvmx_bgxx_smux_rx_bad_col_hi {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_rx_bad_col_hi_s {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 val : 1;\n+\t\tu64 state : 8;\n+\t\tu64 lane_rxc : 8;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_rx_bad_col_hi_s cn73xx;\n+\tstruct cvmx_bgxx_smux_rx_bad_col_hi_s cn78xx;\n+\tstruct cvmx_bgxx_smux_rx_bad_col_hi_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_rx_bad_col_hi_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_rx_bad_col_hi cvmx_bgxx_smux_rx_bad_col_hi_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_rx_bad_col_lo\n+ */\n+union cvmx_bgxx_smux_rx_bad_col_lo {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_rx_bad_col_lo_s {\n+\t\tu64 lane_rxd : 64;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_rx_bad_col_lo_s cn73xx;\n+\tstruct cvmx_bgxx_smux_rx_bad_col_lo_s cn78xx;\n+\tstruct cvmx_bgxx_smux_rx_bad_col_lo_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_rx_bad_col_lo_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_rx_bad_col_lo cvmx_bgxx_smux_rx_bad_col_lo_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_rx_ctl\n+ */\n+union cvmx_bgxx_smux_rx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_rx_ctl_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 status : 2;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_rx_ctl_s cn73xx;\n+\tstruct cvmx_bgxx_smux_rx_ctl_s cn78xx;\n+\tstruct cvmx_bgxx_smux_rx_ctl_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_rx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_rx_ctl cvmx_bgxx_smux_rx_ctl_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_rx_decision\n+ *\n+ * This register specifies the byte count used to determine when to accept or to filter a packet.\n+ * As each byte in a packet is received by BGX, the L2 byte count (i.e. the number of bytes from\n+ * the beginning of the L2 header (DMAC)) is compared against CNT. In normal operation, the L2\n+ * header begins after the PREAMBLE + SFD (BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 1) and any\n+ * optional UDD skip data (BGX()_SMU()_RX_UDD_SKP[LEN]).\n+ */\n+union cvmx_bgxx_smux_rx_decision {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_rx_decision_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 cnt : 5;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_rx_decision_s cn73xx;\n+\tstruct cvmx_bgxx_smux_rx_decision_s cn78xx;\n+\tstruct cvmx_bgxx_smux_rx_decision_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_rx_decision_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_rx_decision cvmx_bgxx_smux_rx_decision_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_rx_frm_chk\n+ *\n+ * The CSRs provide the enable bits for a subset of errors passed to CMR encoded.\n+ *\n+ */\n+union cvmx_bgxx_smux_rx_frm_chk {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_rx_frm_chk_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 reserved_6_6 : 1;\n+\t\tu64 fcserr_c : 1;\n+\t\tu64 fcserr_d : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 reserved_0_2 : 3;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_rx_frm_chk_s cn73xx;\n+\tstruct cvmx_bgxx_smux_rx_frm_chk_s cn78xx;\n+\tstruct cvmx_bgxx_smux_rx_frm_chk_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_rx_frm_chk_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_rx_frm_chk cvmx_bgxx_smux_rx_frm_chk_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_rx_frm_ctl\n+ *\n+ * This register controls the handling of the frames.\n+ * The [CTL_BCK] and [CTL_DRP] bits control how the hardware handles incoming PAUSE packets. The\n+ * most\n+ * common modes of operation:\n+ * _ [CTL_BCK] = 1, [CTL_DRP] = 1: hardware handles everything\n+ * _ [CTL_BCK] = 0, [CTL_DRP] = 0: software sees all PAUSE frames\n+ * _ [CTL_BCK] = 0, [CTL_DRP] = 1: all PAUSE frames are completely ignored\n+ *\n+ * These control bits should be set to [CTL_BCK] = 0, [CTL_DRP] = 0 in half-duplex mode. Since\n+ * PAUSE\n+ * packets only apply to full duplex operation, any PAUSE packet would constitute an exception\n+ * which should be handled by the processing cores. PAUSE packets should not be forwarded.\n+ */\n+union cvmx_bgxx_smux_rx_frm_ctl {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_rx_frm_ctl_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 ptp_mode : 1;\n+\t\tu64 reserved_6_11 : 6;\n+\t\tu64 ctl_smac : 1;\n+\t\tu64 ctl_mcst : 1;\n+\t\tu64 ctl_bck : 1;\n+\t\tu64 ctl_drp : 1;\n+\t\tu64 pre_strp : 1;\n+\t\tu64 pre_chk : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_rx_frm_ctl_s cn73xx;\n+\tstruct cvmx_bgxx_smux_rx_frm_ctl_s cn78xx;\n+\tstruct cvmx_bgxx_smux_rx_frm_ctl_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_rx_frm_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_rx_frm_ctl cvmx_bgxx_smux_rx_frm_ctl_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_rx_int\n+ *\n+ * SMU Interrupt Register.\n+ *\n+ */\n+union cvmx_bgxx_smux_rx_int {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_rx_int_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 hg2cc : 1;\n+\t\tu64 hg2fld : 1;\n+\t\tu64 bad_term : 1;\n+\t\tu64 bad_seq : 1;\n+\t\tu64 rem_fault : 1;\n+\t\tu64 loc_fault : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_rx_int_s cn73xx;\n+\tstruct cvmx_bgxx_smux_rx_int_s cn78xx;\n+\tstruct cvmx_bgxx_smux_rx_int_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_rx_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_rx_int cvmx_bgxx_smux_rx_int_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_rx_jabber\n+ *\n+ * This register specifies the maximum size for packets, beyond which the SMU truncates. In\n+ * XAUI/RXAUI mode, port 0 is used for checking.\n+ */\n+union cvmx_bgxx_smux_rx_jabber {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_rx_jabber_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 cnt : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_rx_jabber_s cn73xx;\n+\tstruct cvmx_bgxx_smux_rx_jabber_s cn78xx;\n+\tstruct cvmx_bgxx_smux_rx_jabber_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_rx_jabber_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_rx_jabber cvmx_bgxx_smux_rx_jabber_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_rx_udd_skp\n+ *\n+ * This register specifies the amount of user-defined data (UDD) added before the start of the\n+ * L2C data.\n+ */\n+union cvmx_bgxx_smux_rx_udd_skp {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_rx_udd_skp_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 fcssel : 1;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 len : 7;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_rx_udd_skp_s cn73xx;\n+\tstruct cvmx_bgxx_smux_rx_udd_skp_s cn78xx;\n+\tstruct cvmx_bgxx_smux_rx_udd_skp_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_rx_udd_skp_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_rx_udd_skp cvmx_bgxx_smux_rx_udd_skp_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_smac\n+ */\n+union cvmx_bgxx_smux_smac {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_smac_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 smac : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_smac_s cn73xx;\n+\tstruct cvmx_bgxx_smux_smac_s cn78xx;\n+\tstruct cvmx_bgxx_smux_smac_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_smac_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_smac cvmx_bgxx_smux_smac_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_append\n+ *\n+ * For more details on the interactions between FCS and PAD, see also the description of\n+ * BGX()_SMU()_TX_MIN_PKT[MIN_SIZE].\n+ */\n+union cvmx_bgxx_smux_tx_append {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_append_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 fcs_c : 1;\n+\t\tu64 fcs_d : 1;\n+\t\tu64 pad : 1;\n+\t\tu64 preamble : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_append_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_append_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_append_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_append_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_append cvmx_bgxx_smux_tx_append_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_ctl\n+ */\n+union cvmx_bgxx_smux_tx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_ctl_s {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 spu_mrk_cnt : 20;\n+\t\tu64 hg_pause_hgi : 2;\n+\t\tu64 hg_en : 1;\n+\t\tu64 l2p_bp_conv : 1;\n+\t\tu64 ls_byp : 1;\n+\t\tu64 ls : 2;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 x4a_dis : 1;\n+\t\tu64 uni_en : 1;\n+\t\tu64 dic_en : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_ctl_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_ctl_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_ctl_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_ctl cvmx_bgxx_smux_tx_ctl_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_ifg\n+ *\n+ * Programming IFG1 and IFG2:\n+ * * For XAUI/RXAUI/10Gbs/40Gbs systems that require IEEE 802.3 compatibility, the IFG1+IFG2 sum\n+ * must be 12.\n+ * * In loopback mode, the IFG1+IFG2 of local and remote parties must match exactly; otherwise\n+ * one of the two sides' loopback FIFO will overrun: BGX()_SMU()_TX_INT[LB_OVRFLW].\n+ */\n+union cvmx_bgxx_smux_tx_ifg {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_ifg_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 ifg2 : 4;\n+\t\tu64 ifg1 : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_ifg_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_ifg_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_ifg_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_ifg_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_ifg cvmx_bgxx_smux_tx_ifg_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_int\n+ */\n+union cvmx_bgxx_smux_tx_int {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_int_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 lb_ovrflw : 1;\n+\t\tu64 lb_undflw : 1;\n+\t\tu64 fake_commit : 1;\n+\t\tu64 xchange : 1;\n+\t\tu64 undflw : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_int_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_int_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_int_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_int cvmx_bgxx_smux_tx_int_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_min_pkt\n+ */\n+union cvmx_bgxx_smux_tx_min_pkt {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_min_pkt_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 min_size : 8;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_min_pkt_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_min_pkt_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_min_pkt_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_min_pkt_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_min_pkt cvmx_bgxx_smux_tx_min_pkt_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_pause_pkt_dmac\n+ *\n+ * This register provides the DMAC value that is placed in outbound PAUSE packets.\n+ *\n+ */\n+union cvmx_bgxx_smux_tx_pause_pkt_dmac {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_dmac_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 dmac : 48;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_dmac_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_dmac_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_dmac_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_dmac_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_pause_pkt_dmac cvmx_bgxx_smux_tx_pause_pkt_dmac_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_pause_pkt_interval\n+ *\n+ * This register specifies how often PAUSE packets are sent.\n+ *\n+ */\n+union cvmx_bgxx_smux_tx_pause_pkt_interval {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_interval_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 hg2_intra_en : 1;\n+\t\tu64 hg2_intra_interval : 16;\n+\t\tu64 interval : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_interval_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_interval_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_interval_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_interval_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_pause_pkt_interval cvmx_bgxx_smux_tx_pause_pkt_interval_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_pause_pkt_time\n+ */\n+union cvmx_bgxx_smux_tx_pause_pkt_time {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_time_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 p_time : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_time_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_time_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_time_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_time_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_pause_pkt_time cvmx_bgxx_smux_tx_pause_pkt_time_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_pause_pkt_type\n+ *\n+ * This register provides the P_TYPE field that is placed in outbound PAUSE packets.\n+ *\n+ */\n+union cvmx_bgxx_smux_tx_pause_pkt_type {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_type_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 p_type : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_type_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_type_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_type_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_pause_pkt_type_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_pause_pkt_type cvmx_bgxx_smux_tx_pause_pkt_type_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_pause_togo\n+ */\n+union cvmx_bgxx_smux_tx_pause_togo {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_pause_togo_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 msg_time : 16;\n+\t\tu64 p_time : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_pause_togo_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_pause_togo_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_pause_togo_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_pause_togo_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_pause_togo cvmx_bgxx_smux_tx_pause_togo_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_pause_zero\n+ */\n+union cvmx_bgxx_smux_tx_pause_zero {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_pause_zero_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 send : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_pause_zero_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_pause_zero_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_pause_zero_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_pause_zero_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_pause_zero cvmx_bgxx_smux_tx_pause_zero_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_soft_pause\n+ */\n+union cvmx_bgxx_smux_tx_soft_pause {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_soft_pause_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 p_time : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_soft_pause_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_soft_pause_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_soft_pause_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_soft_pause_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_soft_pause cvmx_bgxx_smux_tx_soft_pause_t;\n+\n+/**\n+ * cvmx_bgx#_smu#_tx_thresh\n+ */\n+union cvmx_bgxx_smux_tx_thresh {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_smux_tx_thresh_s {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 cnt : 11;\n+\t} s;\n+\tstruct cvmx_bgxx_smux_tx_thresh_s cn73xx;\n+\tstruct cvmx_bgxx_smux_tx_thresh_s cn78xx;\n+\tstruct cvmx_bgxx_smux_tx_thresh_s cn78xxp1;\n+\tstruct cvmx_bgxx_smux_tx_thresh_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_smux_tx_thresh cvmx_bgxx_smux_tx_thresh_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_an_adv\n+ *\n+ * Software programs this register with the contents of the AN-link code word base page to be\n+ * transmitted during autonegotiation. (See IEEE 802.3 section 73.6 for details.) Any write\n+ * operations to this register prior to completion of autonegotiation, as indicated by\n+ * BGX()_SPU()_AN_STATUS[AN_COMPLETE], should be followed by a renegotiation in order for\n+ * the new values to take effect. Renegotiation is initiated by setting\n+ * BGX()_SPU()_AN_CONTROL[AN_RESTART]. Once autonegotiation has completed, software can\n+ * examine this register along with BGX()_SPU()_AN_LP_BASE to determine the highest\n+ * common denominator technology.\n+ */\n+union cvmx_bgxx_spux_an_adv {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_an_adv_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 fec_req : 1;\n+\t\tu64 fec_able : 1;\n+\t\tu64 arsv : 19;\n+\t\tu64 a100g_cr10 : 1;\n+\t\tu64 a40g_cr4 : 1;\n+\t\tu64 a40g_kr4 : 1;\n+\t\tu64 a10g_kr : 1;\n+\t\tu64 a10g_kx4 : 1;\n+\t\tu64 a1g_kx : 1;\n+\t\tu64 t : 5;\n+\t\tu64 np : 1;\n+\t\tu64 ack : 1;\n+\t\tu64 rf : 1;\n+\t\tu64 xnp_able : 1;\n+\t\tu64 asm_dir : 1;\n+\t\tu64 pause : 1;\n+\t\tu64 e : 5;\n+\t\tu64 s : 5;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_an_adv_s cn73xx;\n+\tstruct cvmx_bgxx_spux_an_adv_s cn78xx;\n+\tstruct cvmx_bgxx_spux_an_adv_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_an_adv_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_an_adv cvmx_bgxx_spux_an_adv_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_an_bp_status\n+ *\n+ * The contents of this register are updated\n+ * during autonegotiation and are valid when BGX()_SPU()_AN_STATUS[AN_COMPLETE] is set.\n+ * At that time, one of the port type bits ([N100G_CR10], [N40G_CR4], [N40G_KR4], [N10G_KR],\n+ * [N10G_KX4],\n+ * [N1G_KX]) will be set depending on the AN priority resolution. If a BASE-R type is negotiated,\n+ * then [FEC] will be set to indicate that FEC operation has been negotiated, and will be\n+ * clear otherwise.\n+ */\n+union cvmx_bgxx_spux_an_bp_status {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_an_bp_status_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 n100g_cr10 : 1;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 n40g_cr4 : 1;\n+\t\tu64 n40g_kr4 : 1;\n+\t\tu64 fec : 1;\n+\t\tu64 n10g_kr : 1;\n+\t\tu64 n10g_kx4 : 1;\n+\t\tu64 n1g_kx : 1;\n+\t\tu64 bp_an_able : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_an_bp_status_s cn73xx;\n+\tstruct cvmx_bgxx_spux_an_bp_status_s cn78xx;\n+\tstruct cvmx_bgxx_spux_an_bp_status_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_an_bp_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_an_bp_status cvmx_bgxx_spux_an_bp_status_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_an_control\n+ */\n+union cvmx_bgxx_spux_an_control {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_an_control_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 an_reset : 1;\n+\t\tu64 reserved_14_14 : 1;\n+\t\tu64 xnp_en : 1;\n+\t\tu64 an_en : 1;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tu64 an_restart : 1;\n+\t\tu64 reserved_0_8 : 9;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_an_control_s cn73xx;\n+\tstruct cvmx_bgxx_spux_an_control_s cn78xx;\n+\tstruct cvmx_bgxx_spux_an_control_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_an_control_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_an_control cvmx_bgxx_spux_an_control_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_an_lp_base\n+ *\n+ * This register captures the contents of the latest AN link code word base page received from\n+ * the link partner during autonegotiation. (See IEEE 802.3 section 73.6 for details.)\n+ * BGX()_SPU()_AN_STATUS[PAGE_RX] is set when this register is updated by hardware.\n+ */\n+union cvmx_bgxx_spux_an_lp_base {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_an_lp_base_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 fec_req : 1;\n+\t\tu64 fec_able : 1;\n+\t\tu64 arsv : 19;\n+\t\tu64 a100g_cr10 : 1;\n+\t\tu64 a40g_cr4 : 1;\n+\t\tu64 a40g_kr4 : 1;\n+\t\tu64 a10g_kr : 1;\n+\t\tu64 a10g_kx4 : 1;\n+\t\tu64 a1g_kx : 1;\n+\t\tu64 t : 5;\n+\t\tu64 np : 1;\n+\t\tu64 ack : 1;\n+\t\tu64 rf : 1;\n+\t\tu64 xnp_able : 1;\n+\t\tu64 asm_dir : 1;\n+\t\tu64 pause : 1;\n+\t\tu64 e : 5;\n+\t\tu64 s : 5;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_an_lp_base_s cn73xx;\n+\tstruct cvmx_bgxx_spux_an_lp_base_s cn78xx;\n+\tstruct cvmx_bgxx_spux_an_lp_base_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_an_lp_base_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_an_lp_base cvmx_bgxx_spux_an_lp_base_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_an_lp_xnp\n+ *\n+ * This register captures the contents of the latest next page code word received from the link\n+ * partner during autonegotiation, if any. See section 802.3 section 73.7.7 for details.\n+ */\n+union cvmx_bgxx_spux_an_lp_xnp {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_an_lp_xnp_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 u : 32;\n+\t\tu64 np : 1;\n+\t\tu64 ack : 1;\n+\t\tu64 mp : 1;\n+\t\tu64 ack2 : 1;\n+\t\tu64 toggle : 1;\n+\t\tu64 m_u : 11;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_an_lp_xnp_s cn73xx;\n+\tstruct cvmx_bgxx_spux_an_lp_xnp_s cn78xx;\n+\tstruct cvmx_bgxx_spux_an_lp_xnp_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_an_lp_xnp_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_an_lp_xnp cvmx_bgxx_spux_an_lp_xnp_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_an_status\n+ */\n+union cvmx_bgxx_spux_an_status {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_an_status_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 prl_flt : 1;\n+\t\tu64 reserved_8_8 : 1;\n+\t\tu64 xnp_stat : 1;\n+\t\tu64 page_rx : 1;\n+\t\tu64 an_complete : 1;\n+\t\tu64 rmt_flt : 1;\n+\t\tu64 an_able : 1;\n+\t\tu64 link_status : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 lp_an_able : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_an_status_s cn73xx;\n+\tstruct cvmx_bgxx_spux_an_status_s cn78xx;\n+\tstruct cvmx_bgxx_spux_an_status_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_an_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_an_status cvmx_bgxx_spux_an_status_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_an_xnp_tx\n+ *\n+ * Software programs this register with the contents of the AN message next page or unformatted\n+ * next page link code word to be transmitted during autonegotiation. Next page exchange occurs\n+ * after the base link code words have been exchanged if either end of the link segment sets the\n+ * NP bit to 1, indicating that it has at least one next page to send. Once initiated, next page\n+ * exchange continues until both ends of the link segment set their NP bits to 0. See section\n+ * 802.3 section 73.7.7 for details.\n+ */\n+union cvmx_bgxx_spux_an_xnp_tx {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_an_xnp_tx_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 u : 32;\n+\t\tu64 np : 1;\n+\t\tu64 ack : 1;\n+\t\tu64 mp : 1;\n+\t\tu64 ack2 : 1;\n+\t\tu64 toggle : 1;\n+\t\tu64 m_u : 11;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_an_xnp_tx_s cn73xx;\n+\tstruct cvmx_bgxx_spux_an_xnp_tx_s cn78xx;\n+\tstruct cvmx_bgxx_spux_an_xnp_tx_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_an_xnp_tx_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_an_xnp_tx cvmx_bgxx_spux_an_xnp_tx_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_algn_status\n+ *\n+ * This register implements the IEEE 802.3 multilane BASE-R PCS alignment status 1-4 registers\n+ * (3.50-3.53). It is valid only when the LPCS type is 40GBASE-R\n+ * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4), and always returns 0x0 for all other LPCS\n+ * types. IEEE 802.3 bits that are not applicable to 40GBASE-R (e.g. status bits for PCS lanes\n+ * 19-4) are not implemented and marked as reserved. PCS lanes 3-0 are valid and are mapped to\n+ * physical SerDes lanes based on the programming of BGX()_CMR()_CONFIG[LANE_TO_SDS].\n+ */\n+union cvmx_bgxx_spux_br_algn_status {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_algn_status_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 marker_lock : 4;\n+\t\tu64 reserved_13_31 : 19;\n+\t\tu64 alignd : 1;\n+\t\tu64 reserved_4_11 : 8;\n+\t\tu64 block_lock : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_algn_status_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_algn_status_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_algn_status_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_algn_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_algn_status cvmx_bgxx_spux_br_algn_status_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_bip_err_cnt\n+ *\n+ * This register implements the IEEE 802.3 BIP error-counter registers for PCS lanes 0-3\n+ * (3.200-3.203). It is valid only when the LPCS type is 40GBASE-R\n+ * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4), and always returns 0x0 for all other LPCS\n+ * types. The counters are indexed by the RX PCS lane number based on the Alignment Marker\n+ * detected on each lane and captured in BGX()_SPU()_BR_LANE_MAP. Each counter counts the\n+ * BIP errors for its PCS lane, and is held at all ones in case of overflow. The counters are\n+ * reset to all 0s when this register is read by software.\n+ *\n+ * The reset operation takes precedence over the increment operation; if the register is read on\n+ * the same clock cycle as an increment operation, the counter is reset to all 0s and the\n+ * increment operation is lost. The counters are writable for test purposes, rather than read-\n+ * only as specified in IEEE 802.3.\n+ */\n+union cvmx_bgxx_spux_br_bip_err_cnt {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_bip_err_cnt_s {\n+\t\tu64 bip_err_cnt_ln3 : 16;\n+\t\tu64 bip_err_cnt_ln2 : 16;\n+\t\tu64 bip_err_cnt_ln1 : 16;\n+\t\tu64 bip_err_cnt_ln0 : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_bip_err_cnt_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_bip_err_cnt_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_bip_err_cnt_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_bip_err_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_bip_err_cnt cvmx_bgxx_spux_br_bip_err_cnt_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_lane_map\n+ *\n+ * This register implements the IEEE 802.3 lane 0-3 mapping registers (3.400-3.403). It is valid\n+ * only when the LPCS type is 40GBASE-R (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4), and always\n+ * returns 0x0 for all other LPCS types. The LNx_MAPPING field for each programmed PCS lane\n+ * (called service interface in 802.3ba-2010) is valid when that lane has achieved alignment\n+ * marker lock on the receive side (i.e. the associated\n+ * BGX()_SPU()_BR_ALGN_STATUS[MARKER_LOCK] = 1), and is invalid otherwise. When valid, it\n+ * returns the actual detected receive PCS lane number based on the received alignment marker\n+ * contents received on that service interface.\n+ *\n+ * The mapping is flexible because IEEE 802.3 allows multilane BASE-R receive lanes to be re-\n+ * ordered. Note that for the transmit side, each PCS lane is mapped to a physical SerDes lane\n+ * based on the programming of BGX()_CMR()_CONFIG[LANE_TO_SDS]. For the receive side,\n+ * BGX()_CMR()_CONFIG[LANE_TO_SDS] specifies the service interface to physical SerDes\n+ * lane mapping, and this register specifies the service interface to PCS lane mapping.\n+ */\n+union cvmx_bgxx_spux_br_lane_map {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_lane_map_s {\n+\t\tu64 reserved_54_63 : 10;\n+\t\tu64 ln3_mapping : 6;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 ln2_mapping : 6;\n+\t\tu64 reserved_22_31 : 10;\n+\t\tu64 ln1_mapping : 6;\n+\t\tu64 reserved_6_15 : 10;\n+\t\tu64 ln0_mapping : 6;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_lane_map_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_lane_map_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_lane_map_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_lane_map_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_lane_map cvmx_bgxx_spux_br_lane_map_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_pmd_control\n+ */\n+union cvmx_bgxx_spux_br_pmd_control {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_pmd_control_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 train_en : 1;\n+\t\tu64 train_restart : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_pmd_control_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_pmd_control_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_pmd_control_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_pmd_control_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_pmd_control cvmx_bgxx_spux_br_pmd_control_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_pmd_ld_cup\n+ *\n+ * This register implements 802.3 MDIO register 1.153 for 10GBASE-R (when\n+ * BGX()_CMR()_CONFIG[LMAC_TYPE] = 10G_R)\n+ * and MDIO registers 1.1300-1.1303 for 40GBASE-R (when\n+ * BGX()_CMR()_CONFIG[LMAC_TYPE] = 40G_R). It is automatically cleared at the start of training.\n+ * When link training\n+ * is in progress, each field reflects the contents of the coefficient update field in the\n+ * associated lane's outgoing training frame. The fields in this register are read/write even\n+ * though they are specified as read-only in 802.3.\n+ *\n+ * If BGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is set, then this register must be updated\n+ * by software during link training and hardware updates are disabled. If\n+ * BGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is clear, this register is automatically\n+ * updated by hardware, and it should not be written by software. The lane fields in this\n+ * register are indexed by logical PCS lane ID.\n+ *\n+ * The lane 0 field (LN0_*) is valid for both\n+ * 10GBASE-R and 40GBASE-R. The remaining fields (LN1_*, LN2_*, LN3_*) are only valid for\n+ * 40GBASE-R.\n+ */\n+union cvmx_bgxx_spux_br_pmd_ld_cup {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_pmd_ld_cup_s {\n+\t\tu64 ln3_cup : 16;\n+\t\tu64 ln2_cup : 16;\n+\t\tu64 ln1_cup : 16;\n+\t\tu64 ln0_cup : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_pmd_ld_cup_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_pmd_ld_cup_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_pmd_ld_cup_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_pmd_ld_cup_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_pmd_ld_cup cvmx_bgxx_spux_br_pmd_ld_cup_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_pmd_ld_rep\n+ *\n+ * This register implements 802.3 MDIO register 1.154 for 10GBASE-R (when\n+ * BGX()_CMR()_CONFIG[LMAC_TYPE] = 10G_R) and MDIO registers 1.1400-1.1403 for 40GBASE-R\n+ * (when BGX()_CMR()_CONFIG[LMAC_TYPE] = 40G_R). It is automatically cleared at the start of\n+ * training. Each field\n+ * reflects the contents of the status report field in the associated lane's outgoing training\n+ * frame. The fields in this register are read/write even though they are specified as read-only\n+ * in 802.3. If BGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is set, then this register must\n+ * be updated by software during link training and hardware updates are disabled. If\n+ * BGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is clear, this register is automatically\n+ * updated by hardware, and it should not be written by software. The lane fields in this\n+ * register are indexed by logical PCS lane ID.\n+ *\n+ * The lane 0 field (LN0_*) is valid for both\n+ * 10GBASE-R and 40GBASE-R. The remaining fields (LN1_*, LN2_*, LN3_*) are only valid for\n+ * 40GBASE-R.\n+ */\n+union cvmx_bgxx_spux_br_pmd_ld_rep {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_pmd_ld_rep_s {\n+\t\tu64 ln3_rep : 16;\n+\t\tu64 ln2_rep : 16;\n+\t\tu64 ln1_rep : 16;\n+\t\tu64 ln0_rep : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_pmd_ld_rep_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_pmd_ld_rep_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_pmd_ld_rep_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_pmd_ld_rep_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_pmd_ld_rep cvmx_bgxx_spux_br_pmd_ld_rep_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_pmd_lp_cup\n+ *\n+ * This register implements 802.3 MDIO register 1.152 for 10GBASE-R (when\n+ * BGX()_CMR()_CONFIG[LMAC_TYPE] = 10G_R)\n+ * and MDIO registers 1.1100-1.1103 for 40GBASE-R (when\n+ * BGX()_CMR()_CONFIG[LMAC_TYPE] = 40G_R). It is automatically cleared at the start of training.\n+ * Each field reflects\n+ * the contents of the coefficient update field in the lane's most recently received training\n+ * frame. This register should not be written when link training is enabled, i.e. when\n+ * BGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] is set. The lane fields in this register are indexed by\n+ * logical PCS lane ID.\n+ *\n+ * The lane 0 field (LN0_*) is valid for both 10GBASE-R and 40GBASE-R. The remaining fields\n+ * (LN1_*, LN2_*, LN3_*) are only valid for 40GBASE-R.\n+ */\n+union cvmx_bgxx_spux_br_pmd_lp_cup {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_pmd_lp_cup_s {\n+\t\tu64 ln3_cup : 16;\n+\t\tu64 ln2_cup : 16;\n+\t\tu64 ln1_cup : 16;\n+\t\tu64 ln0_cup : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_pmd_lp_cup_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_pmd_lp_cup_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_pmd_lp_cup_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_pmd_lp_cup_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_pmd_lp_cup cvmx_bgxx_spux_br_pmd_lp_cup_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_pmd_lp_rep\n+ *\n+ * This register implements 802.3 MDIO register 1.153 for 10GBASE-R (when\n+ * BGX()_CMR()_CONFIG[LMAC_TYPE] = 10G_R)\n+ * and MDIO registers 1.1200-1.1203 for 40GBASE-R (when\n+ * BGX()_CMR()_CONFIG[LMAC_TYPE] = 40G_R). It is automatically cleared at the start of training.\n+ * Each field reflects\n+ * the contents of the status report field in the associated lane's most recently received\n+ * training frame. The lane fields in this register are indexed by logical PCS lane ID.\n+ *\n+ * The lane\n+ * 0 field (LN0_*) is valid for both 10GBASE-R and 40GBASE-R. The remaining fields (LN1_*, LN2_*,\n+ * LN3_*) are only valid for 40GBASE-R.\n+ */\n+union cvmx_bgxx_spux_br_pmd_lp_rep {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_pmd_lp_rep_s {\n+\t\tu64 ln3_rep : 16;\n+\t\tu64 ln2_rep : 16;\n+\t\tu64 ln1_rep : 16;\n+\t\tu64 ln0_rep : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_pmd_lp_rep_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_pmd_lp_rep_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_pmd_lp_rep_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_pmd_lp_rep_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_pmd_lp_rep cvmx_bgxx_spux_br_pmd_lp_rep_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_pmd_status\n+ *\n+ * The lane fields in this register are indexed by logical PCS lane ID. The lane 0 field (LN0_*)\n+ * is valid for both 10GBASE-R and 40GBASE-R. The remaining fields (LN1_*, LN2_*, LN3_*) are only\n+ * valid for 40GBASE-R.\n+ */\n+union cvmx_bgxx_spux_br_pmd_status {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_pmd_status_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 ln3_train_status : 4;\n+\t\tu64 ln2_train_status : 4;\n+\t\tu64 ln1_train_status : 4;\n+\t\tu64 ln0_train_status : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_pmd_status_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_pmd_status_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_pmd_status_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_pmd_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_pmd_status cvmx_bgxx_spux_br_pmd_status_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_status1\n+ */\n+union cvmx_bgxx_spux_br_status1 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_status1_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 rcv_lnk : 1;\n+\t\tu64 reserved_4_11 : 8;\n+\t\tu64 prbs9 : 1;\n+\t\tu64 prbs31 : 1;\n+\t\tu64 hi_ber : 1;\n+\t\tu64 blk_lock : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_status1_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_status1_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_status1_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_status1_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_status1 cvmx_bgxx_spux_br_status1_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_status2\n+ *\n+ * This register implements a combination of the following IEEE 802.3 registers:\n+ * * BASE-R PCS status 2 (MDIO address 3.33).\n+ * * BASE-R BER high-order counter (MDIO address 3.44).\n+ * * Errored-blocks high-order counter (MDIO address 3.45).\n+ *\n+ * Note that the relative locations of some fields have been moved from IEEE 802.3 in order to\n+ * make the register layout more software friendly: the BER counter high-order and low-order bits\n+ * from sections 3.44 and 3.33 have been combined into the contiguous, 22-bit [BER_CNT] field;\n+ * likewise, the errored-blocks counter high-order and low-order bits from section 3.45 have been\n+ * combined into the contiguous, 22-bit [ERR_BLKS] field.\n+ */\n+union cvmx_bgxx_spux_br_status2 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_status2_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 err_blks : 22;\n+\t\tu64 reserved_38_39 : 2;\n+\t\tu64 ber_cnt : 22;\n+\t\tu64 latched_lock : 1;\n+\t\tu64 latched_ber : 1;\n+\t\tu64 reserved_0_13 : 14;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_status2_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_status2_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_status2_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_status2_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_status2 cvmx_bgxx_spux_br_status2_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_tp_control\n+ *\n+ * Refer to the test pattern methodology described in 802.3 sections 49.2.8 and 82.2.10.\n+ *\n+ */\n+union cvmx_bgxx_spux_br_tp_control {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_tp_control_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 scramble_tp : 1;\n+\t\tu64 prbs9_tx : 1;\n+\t\tu64 prbs31_rx : 1;\n+\t\tu64 prbs31_tx : 1;\n+\t\tu64 tx_tp_en : 1;\n+\t\tu64 rx_tp_en : 1;\n+\t\tu64 tp_sel : 1;\n+\t\tu64 dp_sel : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_tp_control_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_tp_control_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_tp_control_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_tp_control_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_tp_control cvmx_bgxx_spux_br_tp_control_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_br_tp_err_cnt\n+ *\n+ * This register provides the BASE-R PCS test-pattern error counter.\n+ *\n+ */\n+union cvmx_bgxx_spux_br_tp_err_cnt {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_br_tp_err_cnt_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 err_cnt : 16;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_br_tp_err_cnt_s cn73xx;\n+\tstruct cvmx_bgxx_spux_br_tp_err_cnt_s cn78xx;\n+\tstruct cvmx_bgxx_spux_br_tp_err_cnt_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_br_tp_err_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_br_tp_err_cnt cvmx_bgxx_spux_br_tp_err_cnt_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_bx_status\n+ */\n+union cvmx_bgxx_spux_bx_status {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_bx_status_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 alignd : 1;\n+\t\tu64 pattst : 1;\n+\t\tu64 reserved_4_10 : 7;\n+\t\tu64 lsync : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_bx_status_s cn73xx;\n+\tstruct cvmx_bgxx_spux_bx_status_s cn78xx;\n+\tstruct cvmx_bgxx_spux_bx_status_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_bx_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_bx_status cvmx_bgxx_spux_bx_status_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_control1\n+ */\n+union cvmx_bgxx_spux_control1 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_control1_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 reset : 1;\n+\t\tu64 loopbck : 1;\n+\t\tu64 spdsel1 : 1;\n+\t\tu64 reserved_12_12 : 1;\n+\t\tu64 lo_pwr : 1;\n+\t\tu64 reserved_7_10 : 4;\n+\t\tu64 spdsel0 : 1;\n+\t\tu64 spd : 4;\n+\t\tu64 reserved_0_1 : 2;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_control1_s cn73xx;\n+\tstruct cvmx_bgxx_spux_control1_s cn78xx;\n+\tstruct cvmx_bgxx_spux_control1_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_control1_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_control1 cvmx_bgxx_spux_control1_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_control2\n+ */\n+union cvmx_bgxx_spux_control2 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_control2_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 pcs_type : 3;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_control2_s cn73xx;\n+\tstruct cvmx_bgxx_spux_control2_s cn78xx;\n+\tstruct cvmx_bgxx_spux_control2_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_control2_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_control2 cvmx_bgxx_spux_control2_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_fec_abil\n+ */\n+union cvmx_bgxx_spux_fec_abil {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_fec_abil_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 err_abil : 1;\n+\t\tu64 fec_abil : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_fec_abil_s cn73xx;\n+\tstruct cvmx_bgxx_spux_fec_abil_s cn78xx;\n+\tstruct cvmx_bgxx_spux_fec_abil_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_fec_abil_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_fec_abil cvmx_bgxx_spux_fec_abil_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_fec_control\n+ */\n+union cvmx_bgxx_spux_fec_control {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_fec_control_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 err_en : 1;\n+\t\tu64 fec_en : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_fec_control_s cn73xx;\n+\tstruct cvmx_bgxx_spux_fec_control_s cn78xx;\n+\tstruct cvmx_bgxx_spux_fec_control_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_fec_control_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_fec_control cvmx_bgxx_spux_fec_control_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_fec_corr_blks01\n+ *\n+ * This register is valid only when the LPCS type is BASE-R\n+ * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x3 or 0x4). The FEC corrected-block counters are\n+ * defined in IEEE 802.3 section 74.8.4.1. Each corrected-blocks counter increments by 1 for a\n+ * corrected FEC block, i.e. an FEC block that has been received with invalid parity on the\n+ * associated PCS lane and has been corrected by the FEC decoder. The counter is reset to all 0s\n+ * when the register is read, and held at all 1s in case of overflow.\n+ *\n+ * The reset operation takes precedence over the increment operation; if the register is read on\n+ * the same clock cycle as an increment operation, the counter is reset to all 0s and the\n+ * increment operation is lost. The counters are writable for test purposes, rather than read-\n+ * only as specified in IEEE 802.3.\n+ */\n+union cvmx_bgxx_spux_fec_corr_blks01 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_fec_corr_blks01_s {\n+\t\tu64 ln1_corr_blks : 32;\n+\t\tu64 ln0_corr_blks : 32;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_fec_corr_blks01_s cn73xx;\n+\tstruct cvmx_bgxx_spux_fec_corr_blks01_s cn78xx;\n+\tstruct cvmx_bgxx_spux_fec_corr_blks01_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_fec_corr_blks01_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_fec_corr_blks01 cvmx_bgxx_spux_fec_corr_blks01_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_fec_corr_blks23\n+ *\n+ * This register is valid only when the LPCS type is 40GBASE-R\n+ * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4). The FEC corrected-block counters are defined in\n+ * IEEE 802.3 section 74.8.4.1. Each corrected-blocks counter increments by 1 for a corrected FEC\n+ * block, i.e. an FEC block that has been received with invalid parity on the associated PCS lane\n+ * and has been corrected by the FEC decoder. The counter is reset to all 0s when the register is\n+ * read, and held at all 1s in case of overflow.\n+ *\n+ * The reset operation takes precedence over the increment operation; if the register is read on\n+ * the same clock cycle as an increment operation, the counter is reset to all 0s and the\n+ * increment operation is lost. The counters are writable for test purposes, rather than read-\n+ * only as specified in IEEE 802.3.\n+ */\n+union cvmx_bgxx_spux_fec_corr_blks23 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_fec_corr_blks23_s {\n+\t\tu64 ln3_corr_blks : 32;\n+\t\tu64 ln2_corr_blks : 32;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_fec_corr_blks23_s cn73xx;\n+\tstruct cvmx_bgxx_spux_fec_corr_blks23_s cn78xx;\n+\tstruct cvmx_bgxx_spux_fec_corr_blks23_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_fec_corr_blks23_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_fec_corr_blks23 cvmx_bgxx_spux_fec_corr_blks23_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_fec_uncorr_blks01\n+ *\n+ * This register is valid only when the LPCS type is BASE-R\n+ * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x3 or 0x4). The FEC corrected-block counters are\n+ * defined in IEEE 802.3 section 74.8.4.2. Each uncorrected-blocks counter increments by 1 for an\n+ * uncorrected FEC block, i.e. an FEC block that has been received with invalid parity on the\n+ * associated PCS lane and has not been corrected by the FEC decoder. The counter is reset to all\n+ * 0s when the register is read, and held at all 1s in case of overflow.\n+ *\n+ * The reset operation takes precedence over the increment operation; if the register is read on\n+ * the same clock cycle as an increment operation, the counter is reset to all 0s and the\n+ * increment operation is lost. The counters are writable for test purposes, rather than read-\n+ * only as specified in IEEE 802.3.\n+ */\n+union cvmx_bgxx_spux_fec_uncorr_blks01 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_fec_uncorr_blks01_s {\n+\t\tu64 ln1_uncorr_blks : 32;\n+\t\tu64 ln0_uncorr_blks : 32;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_fec_uncorr_blks01_s cn73xx;\n+\tstruct cvmx_bgxx_spux_fec_uncorr_blks01_s cn78xx;\n+\tstruct cvmx_bgxx_spux_fec_uncorr_blks01_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_fec_uncorr_blks01_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_fec_uncorr_blks01 cvmx_bgxx_spux_fec_uncorr_blks01_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_fec_uncorr_blks23\n+ *\n+ * This register is valid only when the LPCS type is 40GBASE-R\n+ * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4). The FEC uncorrected-block counters are defined\n+ * in IEEE 802.3 section 74.8.4.2. Each corrected-blocks counter increments by 1 for an\n+ * uncorrected FEC block, i.e. an FEC block that has been received with invalid parity on the\n+ * associated PCS lane and has not been corrected by the FEC decoder. The counter is reset to all\n+ * 0s when the register is read, and held at all 1s in case of overflow.\n+ *\n+ * The reset operation takes precedence over the increment operation; if the register is read on\n+ * the same clock cycle as an increment operation, the counter is reset to all 0s and the\n+ * increment operation is lost. The counters are writable for test purposes, rather than read-\n+ * only as specified in IEEE 802.3.\n+ */\n+union cvmx_bgxx_spux_fec_uncorr_blks23 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_fec_uncorr_blks23_s {\n+\t\tu64 ln3_uncorr_blks : 32;\n+\t\tu64 ln2_uncorr_blks : 32;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_fec_uncorr_blks23_s cn73xx;\n+\tstruct cvmx_bgxx_spux_fec_uncorr_blks23_s cn78xx;\n+\tstruct cvmx_bgxx_spux_fec_uncorr_blks23_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_fec_uncorr_blks23_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_fec_uncorr_blks23 cvmx_bgxx_spux_fec_uncorr_blks23_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_int\n+ */\n+union cvmx_bgxx_spux_int {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_int_s {\n+\t\tu64 reserved_15_63 : 49;\n+\t\tu64 training_failure : 1;\n+\t\tu64 training_done : 1;\n+\t\tu64 an_complete : 1;\n+\t\tu64 an_link_good : 1;\n+\t\tu64 an_page_rx : 1;\n+\t\tu64 fec_uncorr : 1;\n+\t\tu64 fec_corr : 1;\n+\t\tu64 bip_err : 1;\n+\t\tu64 dbg_sync : 1;\n+\t\tu64 algnlos : 1;\n+\t\tu64 synlos : 1;\n+\t\tu64 bitlckls : 1;\n+\t\tu64 err_blk : 1;\n+\t\tu64 rx_link_down : 1;\n+\t\tu64 rx_link_up : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_int_s cn73xx;\n+\tstruct cvmx_bgxx_spux_int_s cn78xx;\n+\tstruct cvmx_bgxx_spux_int_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_int cvmx_bgxx_spux_int_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_lpcs_states\n+ */\n+union cvmx_bgxx_spux_lpcs_states {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_lpcs_states_s {\n+\t\tu64 reserved_15_63 : 49;\n+\t\tu64 br_rx_sm : 3;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tu64 bx_rx_sm : 2;\n+\t\tu64 deskew_am_found : 4;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 deskew_sm : 3;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_lpcs_states_s cn73xx;\n+\tstruct cvmx_bgxx_spux_lpcs_states_s cn78xx;\n+\tstruct cvmx_bgxx_spux_lpcs_states_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_lpcs_states_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_lpcs_states cvmx_bgxx_spux_lpcs_states_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_misc_control\n+ *\n+ * \"* RX logical PCS lane polarity vector <3:0> = [XOR_RXPLRT]<3:0> ^ [4[[RXPLRT]]].\n+ *  * TX logical PCS lane polarity vector <3:0> = [XOR_TXPLRT]<3:0> ^ [4[[TXPLRT]]].\n+ *\n+ *  In short, keep [RXPLRT] and [TXPLRT] cleared, and use [XOR_RXPLRT] and [XOR_TXPLRT] fields to\n+ *  define\n+ *  the polarity per logical PCS lane. Only bit 0 of vector is used for 10GBASE-R, and only bits\n+ * - 1:0 of vector are used for RXAUI.\"\n+ */\n+union cvmx_bgxx_spux_misc_control {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_misc_control_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 rx_packet_dis : 1;\n+\t\tu64 skip_after_term : 1;\n+\t\tu64 intlv_rdisp : 1;\n+\t\tu64 xor_rxplrt : 4;\n+\t\tu64 xor_txplrt : 4;\n+\t\tu64 rxplrt : 1;\n+\t\tu64 txplrt : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_misc_control_s cn73xx;\n+\tstruct cvmx_bgxx_spux_misc_control_s cn78xx;\n+\tstruct cvmx_bgxx_spux_misc_control_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_misc_control_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_misc_control cvmx_bgxx_spux_misc_control_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_spd_abil\n+ */\n+union cvmx_bgxx_spux_spd_abil {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_spd_abil_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 hundredgb : 1;\n+\t\tu64 fortygb : 1;\n+\t\tu64 tenpasst : 1;\n+\t\tu64 tengb : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_spd_abil_s cn73xx;\n+\tstruct cvmx_bgxx_spux_spd_abil_s cn78xx;\n+\tstruct cvmx_bgxx_spux_spd_abil_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_spd_abil_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_spd_abil cvmx_bgxx_spux_spd_abil_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_status1\n+ */\n+union cvmx_bgxx_spux_status1 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_status1_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 flt : 1;\n+\t\tu64 reserved_3_6 : 4;\n+\t\tu64 rcv_lnk : 1;\n+\t\tu64 lpable : 1;\n+\t\tu64 reserved_0_0 : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_status1_s cn73xx;\n+\tstruct cvmx_bgxx_spux_status1_s cn78xx;\n+\tstruct cvmx_bgxx_spux_status1_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_status1_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_status1 cvmx_bgxx_spux_status1_t;\n+\n+/**\n+ * cvmx_bgx#_spu#_status2\n+ */\n+union cvmx_bgxx_spux_status2 {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spux_status2_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 dev : 2;\n+\t\tu64 reserved_12_13 : 2;\n+\t\tu64 xmtflt : 1;\n+\t\tu64 rcvflt : 1;\n+\t\tu64 reserved_6_9 : 4;\n+\t\tu64 hundredgb_r : 1;\n+\t\tu64 fortygb_r : 1;\n+\t\tu64 tengb_t : 1;\n+\t\tu64 tengb_w : 1;\n+\t\tu64 tengb_x : 1;\n+\t\tu64 tengb_r : 1;\n+\t} s;\n+\tstruct cvmx_bgxx_spux_status2_s cn73xx;\n+\tstruct cvmx_bgxx_spux_status2_s cn78xx;\n+\tstruct cvmx_bgxx_spux_status2_s cn78xxp1;\n+\tstruct cvmx_bgxx_spux_status2_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spux_status2 cvmx_bgxx_spux_status2_t;\n+\n+/**\n+ * cvmx_bgx#_spu_bist_status\n+ *\n+ * This register provides memory BIST status from the SPU receive buffer lane FIFOs.\n+ *\n+ */\n+union cvmx_bgxx_spu_bist_status {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spu_bist_status_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 rx_buf_bist_status : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_spu_bist_status_s cn73xx;\n+\tstruct cvmx_bgxx_spu_bist_status_s cn78xx;\n+\tstruct cvmx_bgxx_spu_bist_status_s cn78xxp1;\n+\tstruct cvmx_bgxx_spu_bist_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spu_bist_status cvmx_bgxx_spu_bist_status_t;\n+\n+/**\n+ * cvmx_bgx#_spu_dbg_control\n+ */\n+union cvmx_bgxx_spu_dbg_control {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spu_dbg_control_s {\n+\t\tu64 reserved_56_63 : 8;\n+\t\tu64 ms_clk_period : 12;\n+\t\tu64 us_clk_period : 12;\n+\t\tu64 reserved_31_31 : 1;\n+\t\tu64 br_ber_mon_dis : 1;\n+\t\tu64 an_nonce_match_dis : 1;\n+\t\tu64 timestamp_norm_dis : 1;\n+\t\tu64 rx_buf_flip_synd : 8;\n+\t\tu64 br_pmd_train_soft_en : 1;\n+\t\tu64 an_arb_link_chk_en : 1;\n+\t\tu64 rx_buf_cor_dis : 1;\n+\t\tu64 scramble_dis : 1;\n+\t\tu64 reserved_15_15 : 1;\n+\t\tu64 marker_rxp : 15;\n+\t} s;\n+\tstruct cvmx_bgxx_spu_dbg_control_s cn73xx;\n+\tstruct cvmx_bgxx_spu_dbg_control_s cn78xx;\n+\tstruct cvmx_bgxx_spu_dbg_control_s cn78xxp1;\n+\tstruct cvmx_bgxx_spu_dbg_control_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spu_dbg_control cvmx_bgxx_spu_dbg_control_t;\n+\n+/**\n+ * cvmx_bgx#_spu_mem_int\n+ */\n+union cvmx_bgxx_spu_mem_int {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spu_mem_int_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 rx_buf_sbe : 4;\n+\t\tu64 rx_buf_dbe : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_spu_mem_int_s cn73xx;\n+\tstruct cvmx_bgxx_spu_mem_int_s cn78xx;\n+\tstruct cvmx_bgxx_spu_mem_int_s cn78xxp1;\n+\tstruct cvmx_bgxx_spu_mem_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spu_mem_int cvmx_bgxx_spu_mem_int_t;\n+\n+/**\n+ * cvmx_bgx#_spu_mem_status\n+ *\n+ * This register provides memory ECC status from the SPU receive buffer lane FIFOs.\n+ *\n+ */\n+union cvmx_bgxx_spu_mem_status {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spu_mem_status_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 rx_buf_ecc_synd : 32;\n+\t} s;\n+\tstruct cvmx_bgxx_spu_mem_status_s cn73xx;\n+\tstruct cvmx_bgxx_spu_mem_status_s cn78xx;\n+\tstruct cvmx_bgxx_spu_mem_status_s cn78xxp1;\n+\tstruct cvmx_bgxx_spu_mem_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spu_mem_status cvmx_bgxx_spu_mem_status_t;\n+\n+/**\n+ * cvmx_bgx#_spu_sds#_skew_status\n+ *\n+ * This register provides SerDes lane skew status. One register per physical SerDes lane.\n+ *\n+ */\n+union cvmx_bgxx_spu_sdsx_skew_status {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spu_sdsx_skew_status_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 skew_status : 32;\n+\t} s;\n+\tstruct cvmx_bgxx_spu_sdsx_skew_status_s cn73xx;\n+\tstruct cvmx_bgxx_spu_sdsx_skew_status_s cn78xx;\n+\tstruct cvmx_bgxx_spu_sdsx_skew_status_s cn78xxp1;\n+\tstruct cvmx_bgxx_spu_sdsx_skew_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spu_sdsx_skew_status cvmx_bgxx_spu_sdsx_skew_status_t;\n+\n+/**\n+ * cvmx_bgx#_spu_sds#_states\n+ *\n+ * This register provides SerDes lane states. One register per physical SerDes lane.\n+ *\n+ */\n+union cvmx_bgxx_spu_sdsx_states {\n+\tu64 u64;\n+\tstruct cvmx_bgxx_spu_sdsx_states_s {\n+\t\tu64 reserved_52_63 : 12;\n+\t\tu64 am_lock_invld_cnt : 2;\n+\t\tu64 am_lock_sm : 2;\n+\t\tu64 reserved_45_47 : 3;\n+\t\tu64 train_sm : 3;\n+\t\tu64 train_code_viol : 1;\n+\t\tu64 train_frame_lock : 1;\n+\t\tu64 train_lock_found_1st_marker : 1;\n+\t\tu64 train_lock_bad_markers : 3;\n+\t\tu64 reserved_35_35 : 1;\n+\t\tu64 an_arb_sm : 3;\n+\t\tu64 an_rx_sm : 2;\n+\t\tu64 reserved_29_29 : 1;\n+\t\tu64 fec_block_sync : 1;\n+\t\tu64 fec_sync_cnt : 4;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 br_sh_invld_cnt : 7;\n+\t\tu64 br_block_lock : 1;\n+\t\tu64 br_sh_cnt : 11;\n+\t\tu64 bx_sync_sm : 4;\n+\t} s;\n+\tstruct cvmx_bgxx_spu_sdsx_states_s cn73xx;\n+\tstruct cvmx_bgxx_spu_sdsx_states_s cn78xx;\n+\tstruct cvmx_bgxx_spu_sdsx_states_s cn78xxp1;\n+\tstruct cvmx_bgxx_spu_sdsx_states_s cnf75xx;\n+};\n+\n+typedef union cvmx_bgxx_spu_sdsx_states cvmx_bgxx_spu_sdsx_states_t;\n+\n+#endif\n",
    "prefixes": [
        "v1",
        "05/50"
    ]
}