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GET /api/patches/1415037/?format=api
{ "id": 1415037, "url": "http://patchwork.ozlabs.org/api/patches/1415037/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-4-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-4-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:25", "name": "[v1,03/50] mips: octeon: Add cvmx-agl-defs.h header file", "commit_ref": "3a21874c8ec76549b603d60e3e75e8dcb6eabe21", "pull_url": null, "state": "accepted", "archived": false, "hash": "1551018b437dbc337ed09a7e5463f2c313c6b2cf", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-4-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1415037/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1415037/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=S2d+6rQf;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4CsxL9690kz9sSn\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:38:25 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 13B378263C;\n\tFri, 11 Dec 2020 17:38:15 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 5188782772; Fri, 11 Dec 2020 17:06:48 +0100 (CET)", "from mx2.mailbox.org (mx2a.mailbox.org\n [IPv6:2001:67c:2050:104:0:2:25:2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id CD9C08240E\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:20 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id 78846A0B8E;\n Fri, 11 Dec 2020 17:06:20 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter05.heinlein-hosting.de (spamfilter05.heinlein-hosting.de\n [80.241.56.123]) (amavisd-new, port 10030)\n with ESMTP id zzyC8s_rakLx; Fri, 11 Dec 2020 17:06:14 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607704695;\n\tbh=n56Uop/7uh1WeiWpJ7xdM+pDGqgYOgV0yBciGgEyWE8=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=S2d+6rQfQxBS2MyVRFF7eqfAzyZsXGo/pOB2dSURyTFBhbNXULZy8nVRaYYsJdoOj\n\t sF6VFws6Ytmphq3+7xAOM/epodsiw/heL1dn1ou598kCzVGmjlsmzKexfnLUINi53L\n\t 54ML2sxiacWqgSnGRJ0fX/e6oei1OT0o7mbDxM2dyjLAPTV8QCO8i2srGgNy+mFap8\n\t 1j6Si2ecbsueVf6f1kayi+6oOHHxuJ8Yml+RFEkOzcrjxNdValB+jsvKd5qYqWTG/y\n\t +Suj0+hjPW5tcJWJLzmWF9hxalpWs0OYNcr0xi/zIQbrinwuchEgju5bCT2mi3Rsb2\n\t sEa8nWj0+mFtA==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 03/50] mips: octeon: Add cvmx-agl-defs.h header file", "Date": "Fri, 11 Dec 2020 17:05:25 +0100", "Message-Id": "<20201211160612.1498780-4-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.76 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "469231882", "X-Rspamd-UID": "c08c7b", "X-Mailman-Approved-At": "Fri, 11 Dec 2020 17:38:11 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-agl-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-agl-defs.h | 3135 +++++++++++++++++\n 1 file changed, 3135 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-agl-defs.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-agl-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-agl-defs.h\nnew file mode 100644\nindex 0000000000..bbf1f5936b\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-agl-defs.h\n@@ -0,0 +1,3135 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon agl.\n+ *\n+ */\n+\n+#ifndef __CVMX_AGL_DEFS_H__\n+#define __CVMX_AGL_DEFS_H__\n+\n+#define CVMX_AGL_GMX_BAD_REG\t\t\t (0x00011800E0000518ull)\n+#define CVMX_AGL_GMX_BIST\t\t\t (0x00011800E0000400ull)\n+#define CVMX_AGL_GMX_DRV_CTL\t\t\t (0x00011800E00007F0ull)\n+#define CVMX_AGL_GMX_INF_MODE\t\t\t (0x00011800E00007F8ull)\n+#define CVMX_AGL_GMX_PRTX_CFG(offset)\t\t (0x00011800E0000010ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset)\t (0x00011800E0000180ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset)\t (0x00011800E0000188ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset)\t (0x00011800E0000190ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset)\t (0x00011800E0000198ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset)\t (0x00011800E00001A0ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset)\t (0x00011800E00001A8ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset)\t (0x00011800E0000108ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_ADR_CTL(offset)\t (0x00011800E0000100ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_DECISION(offset)\t (0x00011800E0000040ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_FRM_CHK(offset)\t (0x00011800E0000020ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_FRM_CTL(offset)\t (0x00011800E0000018ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_FRM_MAX(offset)\t (0x00011800E0000030ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_FRM_MIN(offset)\t (0x00011800E0000028ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_IFG(offset)\t\t (0x00011800E0000058ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_INT_EN(offset)\t\t (0x00011800E0000008ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_INT_REG(offset)\t (0x00011800E0000000ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_JABBER(offset)\t\t (0x00011800E0000038ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (0x00011800E0000068ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_RX_INBND(offset)\t (0x00011800E0000060ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_STATS_CTL(offset)\t (0x00011800E0000050ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset)\t (0x00011800E0000088ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset)\t (0x00011800E0000098ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (0x00011800E00000A8ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset)\t (0x00011800E00000B8ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset)\t (0x00011800E0000080ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset)\t (0x00011800E00000C0ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset)\t (0x00011800E0000090ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (0x00011800E00000A0ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset)\t (0x00011800E00000B0ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RXX_UDD_SKP(offset)\t (0x00011800E0000048ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_RX_BP_DROPX(offset)\t (0x00011800E0000420ull + ((offset) & 1) * 8)\n+#define CVMX_AGL_GMX_RX_BP_OFFX(offset)\t\t (0x00011800E0000460ull + ((offset) & 1) * 8)\n+#define CVMX_AGL_GMX_RX_BP_ONX(offset)\t\t (0x00011800E0000440ull + ((offset) & 1) * 8)\n+#define CVMX_AGL_GMX_RX_PRT_INFO\t\t (0x00011800E00004E8ull)\n+#define CVMX_AGL_GMX_RX_TX_STATUS\t\t (0x00011800E00007E8ull)\n+#define CVMX_AGL_GMX_SMACX(offset)\t\t (0x00011800E0000230ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_STAT_BP\t\t\t (0x00011800E0000520ull)\n+#define CVMX_AGL_GMX_TXX_APPEND(offset)\t\t (0x00011800E0000218ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_CLK(offset)\t\t (0x00011800E0000208ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_CTL(offset)\t\t (0x00011800E0000270ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_MIN_PKT(offset)\t (0x00011800E0000240ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (0x00011800E0000248ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset)\t (0x00011800E0000238ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset)\t (0x00011800E0000258ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset)\t (0x00011800E0000260ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset)\t (0x00011800E0000250ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_STAT0(offset)\t\t (0x00011800E0000280ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_STAT1(offset)\t\t (0x00011800E0000288ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_STAT2(offset)\t\t (0x00011800E0000290ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_STAT3(offset)\t\t (0x00011800E0000298ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_STAT4(offset)\t\t (0x00011800E00002A0ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_STAT5(offset)\t\t (0x00011800E00002A8ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_STAT6(offset)\t\t (0x00011800E00002B0ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_STAT7(offset)\t\t (0x00011800E00002B8ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_STAT8(offset)\t\t (0x00011800E00002C0ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_STAT9(offset)\t\t (0x00011800E00002C8ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_STATS_CTL(offset)\t (0x00011800E0000268ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TXX_THRESH(offset)\t\t (0x00011800E0000210ull + ((offset) & 1) * 2048)\n+#define CVMX_AGL_GMX_TX_BP\t\t\t (0x00011800E00004D0ull)\n+#define CVMX_AGL_GMX_TX_COL_ATTEMPT\t\t (0x00011800E0000498ull)\n+#define CVMX_AGL_GMX_TX_IFG\t\t\t (0x00011800E0000488ull)\n+#define CVMX_AGL_GMX_TX_INT_EN\t\t\t (0x00011800E0000508ull)\n+#define CVMX_AGL_GMX_TX_INT_REG\t\t\t (0x00011800E0000500ull)\n+#define CVMX_AGL_GMX_TX_JAM\t\t\t (0x00011800E0000490ull)\n+#define CVMX_AGL_GMX_TX_LFSR\t\t\t (0x00011800E00004F8ull)\n+#define CVMX_AGL_GMX_TX_OVR_BP\t\t\t (0x00011800E00004C8ull)\n+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC\t\t (0x00011800E00004A0ull)\n+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE\t\t (0x00011800E00004A8ull)\n+#define CVMX_AGL_GMX_WOL_CTL\t\t\t (0x00011800E0000780ull)\n+#define CVMX_AGL_PRTX_CTL(offset)\t\t (0x00011800E0002000ull + ((offset) & 1) * 8)\n+\n+/**\n+ * cvmx_agl_gmx_bad_reg\n+ *\n+ * AGL_GMX_BAD_REG = A collection of things that have gone very, very wrong\n+ *\n+ *\n+ * Notes:\n+ * OUT_OVR[0], LOSTSTAT[0], OVRFLW, TXPOP, TXPSH will be reset when MIX0_CTL[RESET] is set to 1.\n+ * OUT_OVR[1], LOSTSTAT[1], OVRFLW1, TXPOP1, TXPSH1 will be reset when MIX1_CTL[RESET] is set to 1.\n+ * STATOVR will be reset when both MIX0/1_CTL[RESET] are set to 1.\n+ */\n+union cvmx_agl_gmx_bad_reg {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_bad_reg_s {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 txpsh1 : 1;\n+\t\tu64 txpop1 : 1;\n+\t\tu64 ovrflw1 : 1;\n+\t\tu64 txpsh : 1;\n+\t\tu64 txpop : 1;\n+\t\tu64 ovrflw : 1;\n+\t\tu64 reserved_27_31 : 5;\n+\t\tu64 statovr : 1;\n+\t\tu64 reserved_24_25 : 2;\n+\t\tu64 loststat : 2;\n+\t\tu64 reserved_4_21 : 18;\n+\t\tu64 out_ovr : 2;\n+\t\tu64 reserved_0_1 : 2;\n+\t} s;\n+\tstruct cvmx_agl_gmx_bad_reg_cn52xx {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 txpsh1 : 1;\n+\t\tu64 txpop1 : 1;\n+\t\tu64 ovrflw1 : 1;\n+\t\tu64 txpsh : 1;\n+\t\tu64 txpop : 1;\n+\t\tu64 ovrflw : 1;\n+\t\tu64 reserved_27_31 : 5;\n+\t\tu64 statovr : 1;\n+\t\tu64 reserved_23_25 : 3;\n+\t\tu64 loststat : 1;\n+\t\tu64 reserved_4_21 : 18;\n+\t\tu64 out_ovr : 2;\n+\t\tu64 reserved_0_1 : 2;\n+\t} cn52xx;\n+\tstruct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1;\n+\tstruct cvmx_agl_gmx_bad_reg_cn56xx {\n+\t\tu64 reserved_35_63 : 29;\n+\t\tu64 txpsh : 1;\n+\t\tu64 txpop : 1;\n+\t\tu64 ovrflw : 1;\n+\t\tu64 reserved_27_31 : 5;\n+\t\tu64 statovr : 1;\n+\t\tu64 reserved_23_25 : 3;\n+\t\tu64 loststat : 1;\n+\t\tu64 reserved_3_21 : 19;\n+\t\tu64 out_ovr : 1;\n+\t\tu64 reserved_0_1 : 2;\n+\t} cn56xx;\n+\tstruct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_bad_reg_s cn61xx;\n+\tstruct cvmx_agl_gmx_bad_reg_s cn63xx;\n+\tstruct cvmx_agl_gmx_bad_reg_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_bad_reg_s cn66xx;\n+\tstruct cvmx_agl_gmx_bad_reg_s cn68xx;\n+\tstruct cvmx_agl_gmx_bad_reg_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_bad_reg_cn56xx cn70xx;\n+\tstruct cvmx_agl_gmx_bad_reg_cn56xx cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_bad_reg cvmx_agl_gmx_bad_reg_t;\n+\n+/**\n+ * cvmx_agl_gmx_bist\n+ *\n+ * AGL_GMX_BIST = GMX BIST Results\n+ *\n+ *\n+ * Notes:\n+ * Not reset when MIX*_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_bist {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_bist_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 status : 25;\n+\t} s;\n+\tstruct cvmx_agl_gmx_bist_cn52xx {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 status : 10;\n+\t} cn52xx;\n+\tstruct cvmx_agl_gmx_bist_cn52xx cn52xxp1;\n+\tstruct cvmx_agl_gmx_bist_cn52xx cn56xx;\n+\tstruct cvmx_agl_gmx_bist_cn52xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_bist_s cn61xx;\n+\tstruct cvmx_agl_gmx_bist_s cn63xx;\n+\tstruct cvmx_agl_gmx_bist_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_bist_s cn66xx;\n+\tstruct cvmx_agl_gmx_bist_s cn68xx;\n+\tstruct cvmx_agl_gmx_bist_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_bist_s cn70xx;\n+\tstruct cvmx_agl_gmx_bist_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_bist cvmx_agl_gmx_bist_t;\n+\n+/**\n+ * cvmx_agl_gmx_drv_ctl\n+ *\n+ * AGL_GMX_DRV_CTL = GMX Drive Control\n+ *\n+ *\n+ * Notes:\n+ * NCTL, PCTL, BYP_EN will be reset when MIX0_CTL[RESET] is set to 1.\n+ * NCTL1, PCTL1, BYP_EN1 will be reset when MIX1_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_drv_ctl {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_drv_ctl_s {\n+\t\tu64 reserved_49_63 : 15;\n+\t\tu64 byp_en1 : 1;\n+\t\tu64 reserved_45_47 : 3;\n+\t\tu64 pctl1 : 5;\n+\t\tu64 reserved_37_39 : 3;\n+\t\tu64 nctl1 : 5;\n+\t\tu64 reserved_17_31 : 15;\n+\t\tu64 byp_en : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 pctl : 5;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 nctl : 5;\n+\t} s;\n+\tstruct cvmx_agl_gmx_drv_ctl_s cn52xx;\n+\tstruct cvmx_agl_gmx_drv_ctl_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_drv_ctl_cn56xx {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 byp_en : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 pctl : 5;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 nctl : 5;\n+\t} cn56xx;\n+\tstruct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_drv_ctl cvmx_agl_gmx_drv_ctl_t;\n+\n+/**\n+ * cvmx_agl_gmx_inf_mode\n+ *\n+ * AGL_GMX_INF_MODE = Interface Mode\n+ *\n+ *\n+ * Notes:\n+ * Not reset when MIX*_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_inf_mode {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_inf_mode_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 en : 1;\n+\t\tu64 reserved_0_0 : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_inf_mode_s cn52xx;\n+\tstruct cvmx_agl_gmx_inf_mode_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_inf_mode_s cn56xx;\n+\tstruct cvmx_agl_gmx_inf_mode_s cn56xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_inf_mode cvmx_agl_gmx_inf_mode_t;\n+\n+/**\n+ * cvmx_agl_gmx_prt#_cfg\n+ *\n+ * AGL_GMX_PRT_CFG = Port description\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_prtx_cfg {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_prtx_cfg_s {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 tx_idle : 1;\n+\t\tu64 rx_idle : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 speed_msb : 1;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 burst : 1;\n+\t\tu64 tx_en : 1;\n+\t\tu64 rx_en : 1;\n+\t\tu64 slottime : 1;\n+\t\tu64 duplex : 1;\n+\t\tu64 speed : 1;\n+\t\tu64 en : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_prtx_cfg_cn52xx {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 tx_en : 1;\n+\t\tu64 rx_en : 1;\n+\t\tu64 slottime : 1;\n+\t\tu64 duplex : 1;\n+\t\tu64 speed : 1;\n+\t\tu64 en : 1;\n+\t} cn52xx;\n+\tstruct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1;\n+\tstruct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx;\n+\tstruct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_prtx_cfg_s cn61xx;\n+\tstruct cvmx_agl_gmx_prtx_cfg_s cn63xx;\n+\tstruct cvmx_agl_gmx_prtx_cfg_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_prtx_cfg_s cn66xx;\n+\tstruct cvmx_agl_gmx_prtx_cfg_s cn68xx;\n+\tstruct cvmx_agl_gmx_prtx_cfg_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_prtx_cfg_s cn70xx;\n+\tstruct cvmx_agl_gmx_prtx_cfg_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_prtx_cfg cvmx_agl_gmx_prtx_cfg_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_adr_cam0\n+ *\n+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_adr_cam0 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s {\n+\t\tu64 adr : 64;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam0_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_adr_cam0 cvmx_agl_gmx_rxx_adr_cam0_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_adr_cam1\n+ *\n+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_adr_cam1 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s {\n+\t\tu64 adr : 64;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam1_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_adr_cam1 cvmx_agl_gmx_rxx_adr_cam1_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_adr_cam2\n+ *\n+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_adr_cam2 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s {\n+\t\tu64 adr : 64;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam2_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_adr_cam2 cvmx_agl_gmx_rxx_adr_cam2_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_adr_cam3\n+ *\n+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_adr_cam3 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s {\n+\t\tu64 adr : 64;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam3_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_adr_cam3 cvmx_agl_gmx_rxx_adr_cam3_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_adr_cam4\n+ *\n+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_adr_cam4 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s {\n+\t\tu64 adr : 64;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam4_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_adr_cam4 cvmx_agl_gmx_rxx_adr_cam4_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_adr_cam5\n+ *\n+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_adr_cam5 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s {\n+\t\tu64 adr : 64;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam5_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_adr_cam5 cvmx_agl_gmx_rxx_adr_cam5_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_adr_cam_en\n+ *\n+ * AGL_GMX_RX_ADR_CAM_EN = Address Filtering Control Enable\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_adr_cam_en {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 en : 8;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_cam_en_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_adr_cam_en cvmx_agl_gmx_rxx_adr_cam_en_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_adr_ctl\n+ *\n+ * AGL_GMX_RX_ADR_CTL = Address Filtering Control\n+ *\n+ *\n+ * Notes:\n+ * * ALGORITHM\n+ * Here is some pseudo code that represents the address filter behavior.\n+ *\n+ * @verbatim\n+ * bool dmac_addr_filter(uint8 prt, uint48 dmac) [\n+ * ASSERT(prt >= 0 && prt <= 3);\n+ * if (is_bcst(dmac)) // broadcast accept\n+ * return (AGL_GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);\n+ * if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 1) // multicast reject\n+ * return REJECT;\n+ * if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 2) // multicast accept\n+ * return ACCEPT;\n+ *\n+ * cam_hit = 0;\n+ *\n+ * for (i=0; i<8; i++) [\n+ * if (AGL_GMX_RX[prt]_ADR_CAM_EN[EN<i>] == 0)\n+ * continue;\n+ * uint48 unswizzled_mac_adr = 0x0;\n+ * for (j=5; j>=0; j--) [\n+ * unswizzled_mac_adr = (unswizzled_mac_adr << 8) | AGL_GMX_RX[prt]_ADR_CAM[j][ADR<i*8+7:i*8>];\n+ * ]\n+ * if (unswizzled_mac_adr == dmac) [\n+ * cam_hit = 1;\n+ * break;\n+ * ]\n+ * ]\n+ *\n+ * if (cam_hit)\n+ * return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);\n+ * else\n+ * return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);\n+ * ]\n+ * @endverbatim\n+ *\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rxx_adr_ctl {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 cam_mode : 1;\n+\t\tu64 mcst : 2;\n+\t\tu64 bcst : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_adr_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_adr_ctl cvmx_agl_gmx_rxx_adr_ctl_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_decision\n+ *\n+ * AGL_GMX_RX_DECISION = The byte count to decide when to accept or filter a packet\n+ *\n+ *\n+ * Notes:\n+ * As each byte in a packet is received by GMX, the L2 byte count is compared\n+ * against the AGL_GMX_RX_DECISION[CNT]. The L2 byte count is the number of bytes\n+ * from the beginning of the L2 header (DMAC). In normal operation, the L2\n+ * header begins after the PREAMBLE+SFD (AGL_GMX_RX_FRM_CTL[PRE_CHK]=1) and any\n+ * optional UDD skip data (AGL_GMX_RX_UDD_SKP[LEN]).\n+ *\n+ * When AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the\n+ * packet and would require UDD skip length to account for them.\n+ *\n+ * L2 Size\n+ * Port Mode <=AGL_GMX_RX_DECISION bytes (default=24) >AGL_GMX_RX_DECISION bytes (default=24)\n+ *\n+ * MII/Full Duplex accept packet apply filters\n+ * no filtering is applied accept packet based on DMAC and PAUSE packet filters\n+ *\n+ * MII/Half Duplex drop packet apply filters\n+ * packet is unconditionally dropped accept packet based on DMAC\n+ *\n+ * where l2_size = MAX(0, total_packet_size - AGL_GMX_RX_UDD_SKP[LEN] - ((AGL_GMX_RX_FRM_CTL[PRE_CHK]==1)*8)\n+ *\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rxx_decision {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_decision_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 cnt : 5;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_decision_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_decision_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_decision_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_decision_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_decision_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_decision_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_decision_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_decision_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_decision_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_decision_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_decision_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_decision_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_decision cvmx_agl_gmx_rxx_decision_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_frm_chk\n+ *\n+ * AGL_GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame\n+ *\n+ *\n+ * Notes:\n+ * If AGL_GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW.\n+ *\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rxx_frm_chk {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_cn52xx {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 minerr : 1;\n+\t} cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_chk_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_frm_chk cvmx_agl_gmx_rxx_frm_chk_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_frm_ctl\n+ *\n+ * AGL_GMX_RX_FRM_CTL = Frame Control\n+ *\n+ *\n+ * Notes:\n+ * * PRE_STRP\n+ * When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP\n+ * determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane\n+ * core as part of the packet.\n+ *\n+ * In either mode, the PREAMBLE+SFD bytes are not counted toward the packet\n+ * size when checking against the MIN and MAX bounds. Furthermore, the bytes\n+ * are skipped when locating the start of the L2 header for DMAC and Control\n+ * frame recognition.\n+ *\n+ * * CTL_BCK/CTL_DRP\n+ * These bits control how the HW handles incoming PAUSE packets. Here are\n+ * the most common modes of operation:\n+ * CTL_BCK=1,CTL_DRP=1 - HW does it all\n+ * CTL_BCK=0,CTL_DRP=0 - SW sees all pause frames\n+ * CTL_BCK=0,CTL_DRP=1 - all pause frames are completely ignored\n+ *\n+ * These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode.\n+ * Since PAUSE packets only apply to fulldup operation, any PAUSE packet\n+ * would constitute an exception which should be handled by the processing\n+ * cores. PAUSE packets should not be forwarded.\n+ *\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rxx_frm_ctl {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 ptp_mode : 1;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 null_dis : 1;\n+\t\tu64 pre_align : 1;\n+\t\tu64 pad_len : 1;\n+\t\tu64 vlan_len : 1;\n+\t\tu64 pre_free : 1;\n+\t\tu64 ctl_smac : 1;\n+\t\tu64 ctl_mcst : 1;\n+\t\tu64 ctl_bck : 1;\n+\t\tu64 ctl_drp : 1;\n+\t\tu64 pre_strp : 1;\n+\t\tu64 pre_chk : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 pre_align : 1;\n+\t\tu64 pad_len : 1;\n+\t\tu64 vlan_len : 1;\n+\t\tu64 pre_free : 1;\n+\t\tu64 ctl_smac : 1;\n+\t\tu64 ctl_mcst : 1;\n+\t\tu64 ctl_bck : 1;\n+\t\tu64 ctl_drp : 1;\n+\t\tu64 pre_strp : 1;\n+\t\tu64 pre_chk : 1;\n+\t} cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_frm_ctl cvmx_agl_gmx_rxx_frm_ctl_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_frm_max\n+ *\n+ * AGL_GMX_RX_FRM_MAX = Frame Max length\n+ *\n+ *\n+ * Notes:\n+ * When changing the LEN field, be sure that LEN does not exceed\n+ * AGL_GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that\n+ * are within the maximum length parameter to be rejected because they exceed\n+ * the AGL_GMX_RX_JABBER[CNT] limit.\n+ *\n+ * Notes:\n+ *\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rxx_frm_max {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 len : 16;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_max_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_frm_max cvmx_agl_gmx_rxx_frm_max_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_frm_min\n+ *\n+ * AGL_GMX_RX_FRM_MIN = Frame Min length\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_frm_min {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 len : 16;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_frm_min_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_frm_min cvmx_agl_gmx_rxx_frm_min_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_ifg\n+ *\n+ * AGL_GMX_RX_IFG = RX Min IFG\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_ifg {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 ifg : 4;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_ifg_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_ifg cvmx_agl_gmx_rxx_ifg_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_int_en\n+ *\n+ * AGL_GMX_RX_INT_EN = Interrupt Enable\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_int_en {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_int_en_s {\n+\t\tu64 reserved_30_63 : 34;\n+\t\tu64 wol : 1;\n+\t\tu64 reserved_20_28 : 9;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 phy_dupx : 1;\n+\t\tu64 phy_spd : 1;\n+\t\tu64 phy_link : 1;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_int_en_cn52xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 reserved_16_18 : 3;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 reserved_9_9 : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 minerr : 1;\n+\t} cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_int_en_cn61xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 phy_dupx : 1;\n+\t\tu64 phy_spd : 1;\n+\t\tu64 phy_link : 1;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_int_en_cn61xx cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_int_en_cn61xx cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_int_en_cn61xx cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_int_en_cn61xx cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_int_en_cn61xx cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_int_en_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_int_en_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_int_en cvmx_agl_gmx_rxx_int_en_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_int_reg\n+ *\n+ * AGL_GMX_RX_INT_REG = Interrupt Register\n+ *\n+ *\n+ * Notes:\n+ * (1) exceptions will only be raised to the control processor if the\n+ * corresponding bit in the AGL_GMX_RX_INT_EN register is set.\n+ *\n+ * (2) exception conditions 10:0 can also set the rcv/opcode in the received\n+ * packet's workQ entry. The AGL_GMX_RX_FRM_CHK register provides a bit mask\n+ * for configuring which conditions set the error.\n+ *\n+ * (3) in half duplex operation, the expectation is that collisions will appear\n+ * as MINERRs.\n+ *\n+ * (4) JABBER - An RX Jabber error indicates that a packet was received which\n+ * is longer than the maximum allowed packet as defined by the\n+ * system. GMX will truncate the packet at the JABBER count.\n+ * Failure to do so could lead to system instabilty.\n+ *\n+ * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS >\n+ * AGL_GMX_RX_FRM_MAX. For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS\n+ * > AGL_GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED.\n+ *\n+ * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < AGL_GMX_RX_FRM_MIN.\n+ *\n+ * (8) ALNERR - Indicates that the packet received was not an integer number of\n+ * bytes. If FCS checking is enabled, ALNERR will only assert if\n+ * the FCS is bad. If FCS checking is disabled, ALNERR will\n+ * assert in all non-integer frame cases.\n+ *\n+ * (9) Collisions - Collisions can only occur in half-duplex mode. A collision\n+ * is assumed by the receiver when the received\n+ * frame < AGL_GMX_RX_FRM_MIN - this is normally a MINERR\n+ *\n+ * (A) LENERR - Length errors occur when the received packet does not match the\n+ * length field. LENERR is only checked for packets between 64\n+ * and 1500 bytes. For untagged frames, the length must exact\n+ * match. For tagged frames the length or length+4 must match.\n+ *\n+ * (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence.\n+ * Does not check the number of PREAMBLE cycles.\n+ *\n+ * (C) OVRERR -\n+ *\n+ * OVRERR is an architectural assertion check internal to GMX to\n+ * make sure no assumption was violated. In a correctly operating\n+ * system, this interrupt can never fire.\n+ *\n+ * GMX has an internal arbiter which selects which of 4 ports to\n+ * buffer in the main RX FIFO. If we normally buffer 8 bytes,\n+ * then each port will typically push a tick every 8 cycles - if\n+ * the packet interface is going as fast as possible. If there\n+ * are four ports, they push every two cycles. So that's the\n+ * assumption. That the inbound module will always be able to\n+ * consume the tick before another is produced. If that doesn't\n+ * happen - that's when OVRERR will assert.\n+ *\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rxx_int_reg {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_s {\n+\t\tu64 reserved_30_63 : 34;\n+\t\tu64 wol : 1;\n+\t\tu64 reserved_20_28 : 9;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 phy_dupx : 1;\n+\t\tu64 phy_spd : 1;\n+\t\tu64 phy_link : 1;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_cn52xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 reserved_16_18 : 3;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 reserved_9_9 : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 minerr : 1;\n+\t} cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_cn61xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 pause_drp : 1;\n+\t\tu64 phy_dupx : 1;\n+\t\tu64 phy_spd : 1;\n+\t\tu64 phy_link : 1;\n+\t\tu64 ifgerr : 1;\n+\t\tu64 coldet : 1;\n+\t\tu64 falerr : 1;\n+\t\tu64 rsverr : 1;\n+\t\tu64 pcterr : 1;\n+\t\tu64 ovrerr : 1;\n+\t\tu64 niberr : 1;\n+\t\tu64 skperr : 1;\n+\t\tu64 rcverr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 alnerr : 1;\n+\t\tu64 fcserr : 1;\n+\t\tu64 jabber : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 carext : 1;\n+\t\tu64 minerr : 1;\n+\t} cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_cn61xx cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_cn61xx cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_cn61xx cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_cn61xx cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_cn61xx cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_int_reg_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_int_reg cvmx_agl_gmx_rxx_int_reg_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_jabber\n+ *\n+ * AGL_GMX_RX_JABBER = The max size packet after which GMX will truncate\n+ *\n+ *\n+ * Notes:\n+ * CNT must be 8-byte aligned such that CNT[2:0] == 0\n+ *\n+ * The packet that will be sent to the packet input logic will have an\n+ * additionl 8 bytes if AGL_GMX_RX_FRM_CTL[PRE_CHK] is set and\n+ * AGL_GMX_RX_FRM_CTL[PRE_STRP] is clear. The max packet that will be sent is\n+ * defined as...\n+ *\n+ * max_sized_packet = AGL_GMX_RX_JABBER[CNT]+((AGL_GMX_RX_FRM_CTL[PRE_CHK] & !AGL_GMX_RX_FRM_CTL[PRE_STRP])*8)\n+ *\n+ * Be sure the CNT field value is at least as large as the\n+ * AGL_GMX_RX_FRM_MAX[LEN] value. Failure to meet this constraint will cause\n+ * packets that are within the AGL_GMX_RX_FRM_MAX[LEN] length to be rejected\n+ * because they exceed the CNT limit.\n+ *\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rxx_jabber {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 cnt : 16;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_jabber_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_jabber cvmx_agl_gmx_rxx_jabber_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_pause_drop_time\n+ *\n+ * AGL_GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_pause_drop_time {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 status : 16;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_pause_drop_time_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_pause_drop_time cvmx_agl_gmx_rxx_pause_drop_time_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_rx_inbnd\n+ *\n+ * AGL_GMX_RX_INBND = RGMII InBand Link Status\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_rx_inbnd {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_rx_inbnd_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 duplex : 1;\n+\t\tu64 speed : 2;\n+\t\tu64 status : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_rx_inbnd_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_rx_inbnd_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_rx_inbnd_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_rx_inbnd_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_rx_inbnd cvmx_agl_gmx_rxx_rx_inbnd_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_stats_ctl\n+ *\n+ * AGL_GMX_RX_STATS_CTL = RX Stats Control register\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_rxx_stats_ctl {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 rd_clr : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_stats_ctl cvmx_agl_gmx_rxx_stats_ctl_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_stats_octs\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rxx_stats_octs {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_stats_octs cvmx_agl_gmx_rxx_stats_octs_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_stats_octs_ctl\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rxx_stats_octs_ctl {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_stats_octs_ctl cvmx_agl_gmx_rxx_stats_octs_ctl_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_stats_octs_dmac\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rxx_stats_octs_dmac {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_stats_octs_dmac cvmx_agl_gmx_rxx_stats_octs_dmac_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_stats_octs_drp\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rxx_stats_octs_drp {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 cnt : 48;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_octs_drp_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_stats_octs_drp cvmx_agl_gmx_rxx_stats_octs_drp_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_stats_pkts\n+ *\n+ * Count of good received packets - packets that are not recognized as PAUSE\n+ * packets, dropped due the DMAC filter, dropped due FIFO full status, or\n+ * have any other OPCODE (FCS, Length, etc).\n+ */\n+union cvmx_agl_gmx_rxx_stats_pkts {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_stats_pkts cvmx_agl_gmx_rxx_stats_pkts_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_stats_pkts_bad\n+ *\n+ * Count of all packets received with some error that were not dropped\n+ * either due to the dmac filter or lack of room in the receive FIFO.\n+ */\n+union cvmx_agl_gmx_rxx_stats_pkts_bad {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_stats_pkts_bad cvmx_agl_gmx_rxx_stats_pkts_bad_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_stats_pkts_ctl\n+ *\n+ * Count of all packets received that were recognized as Flow Control or\n+ * PAUSE packets. PAUSE packets with any kind of error are counted in\n+ * AGL_GMX_RX_STATS_PKTS_BAD. Pause packets can be optionally dropped or\n+ * forwarded based on the AGL_GMX_RX_FRM_CTL[CTL_DRP] bit. This count\n+ * increments regardless of whether the packet is dropped. Pause packets\n+ * will never be counted in AGL_GMX_RX_STATS_PKTS. Packets dropped due the dmac\n+ * filter will be counted in AGL_GMX_RX_STATS_PKTS_DMAC and not here.\n+ */\n+union cvmx_agl_gmx_rxx_stats_pkts_ctl {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_stats_pkts_ctl cvmx_agl_gmx_rxx_stats_pkts_ctl_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_stats_pkts_dmac\n+ *\n+ * Count of all packets received that were dropped by the dmac filter.\n+ * Packets that match the DMAC will be dropped and counted here regardless\n+ * of if they were bad packets. These packets will never be counted in\n+ * AGL_GMX_RX_STATS_PKTS.\n+ * Some packets that were not able to satisify the DECISION_CNT may not\n+ * actually be dropped by Octeon, but they will be counted here as if they\n+ * were dropped.\n+ */\n+union cvmx_agl_gmx_rxx_stats_pkts_dmac {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_stats_pkts_dmac cvmx_agl_gmx_rxx_stats_pkts_dmac_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_stats_pkts_drp\n+ *\n+ * Count of all packets received that were dropped due to a full receive\n+ * FIFO. This counts good and bad packets received - all packets dropped by\n+ * the FIFO. It does not count packets dropped by the dmac or pause packet\n+ * filters.\n+ */\n+union cvmx_agl_gmx_rxx_stats_pkts_drp {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_stats_pkts_drp cvmx_agl_gmx_rxx_stats_pkts_drp_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx#_udd_skp\n+ *\n+ * AGL_GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data\n+ *\n+ *\n+ * Notes:\n+ * (1) The skip bytes are part of the packet and will be sent down the NCB\n+ * packet interface and will be handled by PKI.\n+ *\n+ * (2) The system can determine if the UDD bytes are included in the FCS check\n+ * by using the FCSSEL field - if the FCS check is enabled.\n+ *\n+ * (3) Assume that the preamble/sfd is always at the start of the frame - even\n+ * before UDD bytes. In most cases, there will be no preamble in these\n+ * cases since it will be MII to MII communication without a PHY\n+ * involved.\n+ *\n+ * (4) We can still do address filtering and control packet filtering is the\n+ * user desires.\n+ *\n+ * (5) UDD_SKP must be 0 in half-duplex operation unless\n+ * AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear. If AGL_GMX_RX_FRM_CTL[PRE_CHK] is set,\n+ * then UDD_SKP will normally be 8.\n+ *\n+ * (6) In all cases, the UDD bytes will be sent down the packet interface as\n+ * part of the packet. The UDD bytes are never stripped from the actual\n+ * packet.\n+ *\n+ * (7) If LEN != 0, then AGL_GMX_RX_FRM_CHK[LENERR] will be disabled and AGL_GMX_RX_INT_REG[LENERR] will be zero\n+ *\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rxx_udd_skp {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 fcssel : 1;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 len : 7;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s cn61xx;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s cn63xx;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s cn66xx;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s cn68xx;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s cn70xx;\n+\tstruct cvmx_agl_gmx_rxx_udd_skp_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rxx_udd_skp cvmx_agl_gmx_rxx_udd_skp_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx_bp_drop#\n+ *\n+ * AGL_GMX_RX_BP_DROP = FIFO mark for packet drop\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_rx_bp_dropx {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 mark : 6;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s cn61xx;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s cn63xx;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s cn66xx;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s cn68xx;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s cn70xx;\n+\tstruct cvmx_agl_gmx_rx_bp_dropx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rx_bp_dropx cvmx_agl_gmx_rx_bp_dropx_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx_bp_off#\n+ *\n+ * AGL_GMX_RX_BP_OFF = Lowater mark for packet drop\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_rx_bp_offx {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 mark : 6;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s cn52xx;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s cn56xx;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s cn61xx;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s cn63xx;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s cn66xx;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s cn68xx;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s cn70xx;\n+\tstruct cvmx_agl_gmx_rx_bp_offx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rx_bp_offx cvmx_agl_gmx_rx_bp_offx_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx_bp_on#\n+ *\n+ * AGL_GMX_RX_BP_ON = Hiwater mark for port/interface backpressure\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_rx_bp_onx {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 mark : 9;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s cn52xx;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s cn56xx;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s cn61xx;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s cn63xx;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s cn66xx;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s cn68xx;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s cn70xx;\n+\tstruct cvmx_agl_gmx_rx_bp_onx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rx_bp_onx cvmx_agl_gmx_rx_bp_onx_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx_prt_info\n+ *\n+ * AGL_GMX_RX_PRT_INFO = state information for the ports\n+ *\n+ *\n+ * Notes:\n+ * COMMIT[0], DROP[0] will be reset when MIX0_CTL[RESET] is set to 1.\n+ * COMMIT[1], DROP[1] will be reset when MIX1_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rx_prt_info {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rx_prt_info_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 drop : 2;\n+\t\tu64 reserved_2_15 : 14;\n+\t\tu64 commit : 2;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rx_prt_info_s cn52xx;\n+\tstruct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rx_prt_info_cn56xx {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 drop : 1;\n+\t\tu64 reserved_1_15 : 15;\n+\t\tu64 commit : 1;\n+\t} cn56xx;\n+\tstruct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_rx_prt_info_s cn61xx;\n+\tstruct cvmx_agl_gmx_rx_prt_info_s cn63xx;\n+\tstruct cvmx_agl_gmx_rx_prt_info_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rx_prt_info_s cn66xx;\n+\tstruct cvmx_agl_gmx_rx_prt_info_s cn68xx;\n+\tstruct cvmx_agl_gmx_rx_prt_info_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rx_prt_info_cn56xx cn70xx;\n+\tstruct cvmx_agl_gmx_rx_prt_info_cn56xx cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rx_prt_info cvmx_agl_gmx_rx_prt_info_t;\n+\n+/**\n+ * cvmx_agl_gmx_rx_tx_status\n+ *\n+ * AGL_GMX_RX_TX_STATUS = GMX RX/TX Status\n+ *\n+ *\n+ * Notes:\n+ * RX[0], TX[0] will be reset when MIX0_CTL[RESET] is set to 1.\n+ * RX[1], TX[1] will be reset when MIX1_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_rx_tx_status {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_rx_tx_status_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 tx : 2;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 rx : 2;\n+\t} s;\n+\tstruct cvmx_agl_gmx_rx_tx_status_s cn52xx;\n+\tstruct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_rx_tx_status_cn56xx {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 tx : 1;\n+\t\tu64 reserved_1_3 : 3;\n+\t\tu64 rx : 1;\n+\t} cn56xx;\n+\tstruct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_rx_tx_status_s cn61xx;\n+\tstruct cvmx_agl_gmx_rx_tx_status_s cn63xx;\n+\tstruct cvmx_agl_gmx_rx_tx_status_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_rx_tx_status_s cn66xx;\n+\tstruct cvmx_agl_gmx_rx_tx_status_s cn68xx;\n+\tstruct cvmx_agl_gmx_rx_tx_status_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_rx_tx_status_cn56xx cn70xx;\n+\tstruct cvmx_agl_gmx_rx_tx_status_cn56xx cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_rx_tx_status cvmx_agl_gmx_rx_tx_status_t;\n+\n+/**\n+ * cvmx_agl_gmx_smac#\n+ *\n+ * AGL_GMX_SMAC = Packet SMAC\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_smacx {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_smacx_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 smac : 48;\n+\t} s;\n+\tstruct cvmx_agl_gmx_smacx_s cn52xx;\n+\tstruct cvmx_agl_gmx_smacx_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_smacx_s cn56xx;\n+\tstruct cvmx_agl_gmx_smacx_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_smacx_s cn61xx;\n+\tstruct cvmx_agl_gmx_smacx_s cn63xx;\n+\tstruct cvmx_agl_gmx_smacx_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_smacx_s cn66xx;\n+\tstruct cvmx_agl_gmx_smacx_s cn68xx;\n+\tstruct cvmx_agl_gmx_smacx_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_smacx_s cn70xx;\n+\tstruct cvmx_agl_gmx_smacx_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_smacx cvmx_agl_gmx_smacx_t;\n+\n+/**\n+ * cvmx_agl_gmx_stat_bp\n+ *\n+ * AGL_GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.\n+ *\n+ *\n+ *\n+ * It has no relationship with the TX FIFO per se. The TX engine sends packets\n+ * from PKO and upon completion, sends a command to the TX stats block for an\n+ * update based on the packet size. The stats operation can take a few cycles -\n+ * normally not enough to be visible considering the 64B min packet size that is\n+ * ethernet convention.\n+ *\n+ * In the rare case in which SW attempted to schedule really, really, small packets\n+ * or the sclk (6xxx) is running ass-slow, then the stats updates may not happen in\n+ * real time and can back up the TX engine.\n+ *\n+ * This counter is the number of cycles in which the TX engine was stalled. In\n+ * normal operation, it should always be zeros.\n+ */\n+union cvmx_agl_gmx_stat_bp {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_stat_bp_s {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 bp : 1;\n+\t\tu64 cnt : 16;\n+\t} s;\n+\tstruct cvmx_agl_gmx_stat_bp_s cn52xx;\n+\tstruct cvmx_agl_gmx_stat_bp_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_stat_bp_s cn56xx;\n+\tstruct cvmx_agl_gmx_stat_bp_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_stat_bp_s cn61xx;\n+\tstruct cvmx_agl_gmx_stat_bp_s cn63xx;\n+\tstruct cvmx_agl_gmx_stat_bp_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_stat_bp_s cn66xx;\n+\tstruct cvmx_agl_gmx_stat_bp_s cn68xx;\n+\tstruct cvmx_agl_gmx_stat_bp_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_stat_bp_s cn70xx;\n+\tstruct cvmx_agl_gmx_stat_bp_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_stat_bp cvmx_agl_gmx_stat_bp_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_append\n+ *\n+ * AGL_GMX_TX_APPEND = Packet TX Append Control\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_txx_append {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_append_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 force_fcs : 1;\n+\t\tu64 fcs : 1;\n+\t\tu64 pad : 1;\n+\t\tu64 preamble : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_append_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_append_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_append_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_append_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_append_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_append_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_append_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_append_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_append_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_append_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_append_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_append_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_append cvmx_agl_gmx_txx_append_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_clk\n+ *\n+ * AGL_GMX_TX_CLK = RGMII TX Clock Generation Register\n+ *\n+ *\n+ * Notes:\n+ * Normal Programming Values:\n+ * (1) RGMII, 1000Mbs (AGL_GMX_PRT_CFG[SPEED]==1), CLK_CNT == 1\n+ * (2) RGMII, 10/100Mbs (AGL_GMX_PRT_CFG[SPEED]==0), CLK_CNT == 50/5\n+ * (3) MII, 10/100Mbs (AGL_GMX_PRT_CFG[SPEED]==0), CLK_CNT == 1\n+ *\n+ * RGMII Example:\n+ * Given a 125MHz PLL reference clock...\n+ * CLK_CNT == 1 ==> 125.0MHz TXC clock period (8ns* 1)\n+ * CLK_CNT == 5 ==> 25.0MHz TXC clock period (8ns* 5)\n+ * CLK_CNT == 50 ==> 2.5MHz TXC clock period (8ns*50)\n+ *\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_clk {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_clk_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 clk_cnt : 6;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_clk_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_clk_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_clk_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_clk_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_clk_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_clk_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_clk_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_clk_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_clk cvmx_agl_gmx_txx_clk_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_ctl\n+ *\n+ * AGL_GMX_TX_CTL = TX Control register\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_txx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_ctl_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 xsdef_en : 1;\n+\t\tu64 xscol_en : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_ctl_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_ctl_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_ctl_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_ctl_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_ctl_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_ctl_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_ctl_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_ctl_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_ctl_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_ctl_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_ctl_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_ctl cvmx_agl_gmx_txx_ctl_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_min_pkt\n+ *\n+ * AGL_GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size)\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_txx_min_pkt {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 min_size : 8;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_min_pkt_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_min_pkt cvmx_agl_gmx_txx_min_pkt_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_pause_pkt_interval\n+ *\n+ * AGL_GMX_TX_PAUSE_PKT_INTERVAL = Packet TX Pause Packet transmission interval - how often PAUSE packets will be sent\n+ *\n+ *\n+ * Notes:\n+ * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and\n+ * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system\n+ * designer. It is suggested that TIME be much greater than INTERVAL and\n+ * AGL_GMX_TX_PAUSE_ZERO[SEND] be set. This allows a periodic refresh of the PAUSE\n+ * count and then when the backpressure condition is lifted, a PAUSE packet\n+ * with TIME==0 will be sent indicating that Octane is ready for additional\n+ * data.\n+ *\n+ * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is\n+ * suggested that TIME and INTERVAL are programmed such that they satisify the\n+ * following rule...\n+ *\n+ * INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)\n+ *\n+ * where largest_pkt_size is that largest packet that the system can send\n+ * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size\n+ * of the PAUSE packet (normally 64B).\n+ *\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_pause_pkt_interval {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 interval : 16;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_interval_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_pause_pkt_interval cvmx_agl_gmx_txx_pause_pkt_interval_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_pause_pkt_time\n+ *\n+ * AGL_GMX_TX_PAUSE_PKT_TIME = Packet TX Pause Packet pause_time field\n+ *\n+ *\n+ * Notes:\n+ * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and\n+ * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system\n+ * designer. It is suggested that TIME be much greater than INTERVAL and\n+ * AGL_GMX_TX_PAUSE_ZERO[SEND] be set. This allows a periodic refresh of the PAUSE\n+ * count and then when the backpressure condition is lifted, a PAUSE packet\n+ * with TIME==0 will be sent indicating that Octane is ready for additional\n+ * data.\n+ *\n+ * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is\n+ * suggested that TIME and INTERVAL are programmed such that they satisify the\n+ * following rule...\n+ *\n+ * INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)\n+ *\n+ * where largest_pkt_size is that largest packet that the system can send\n+ * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size\n+ * of the PAUSE packet (normally 64B).\n+ *\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_pause_pkt_time {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 time : 16;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_pause_pkt_time_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_pause_pkt_time cvmx_agl_gmx_txx_pause_pkt_time_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_pause_togo\n+ *\n+ * AGL_GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_txx_pause_togo {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 time : 16;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_pause_togo_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_pause_togo cvmx_agl_gmx_txx_pause_togo_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_pause_zero\n+ *\n+ * AGL_GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_txx_pause_zero {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 send : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_pause_zero_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_pause_zero cvmx_agl_gmx_txx_pause_zero_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_soft_pause\n+ *\n+ * AGL_GMX_TX_SOFT_PAUSE = Packet TX Software Pause\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_txx_soft_pause {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 time : 16;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_soft_pause_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_soft_pause cvmx_agl_gmx_txx_soft_pause_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_stat0\n+ *\n+ * AGL_GMX_TX_STAT0 = AGL_GMX_TX_STATS_XSDEF / AGL_GMX_TX_STATS_XSCOL\n+ *\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_stat0 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_stat0_s {\n+\t\tu64 xsdef : 32;\n+\t\tu64 xscol : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_stat0_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_stat0_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat0_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_stat0_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat0_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_stat0_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_stat0_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat0_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_stat0_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_stat0_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat0_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_stat0_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_stat0 cvmx_agl_gmx_txx_stat0_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_stat1\n+ *\n+ * AGL_GMX_TX_STAT1 = AGL_GMX_TX_STATS_SCOL / AGL_GMX_TX_STATS_MCOL\n+ *\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_stat1 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_stat1_s {\n+\t\tu64 scol : 32;\n+\t\tu64 mcol : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_stat1_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_stat1_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat1_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_stat1_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat1_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_stat1_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_stat1_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat1_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_stat1_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_stat1_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat1_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_stat1_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_stat1 cvmx_agl_gmx_txx_stat1_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_stat2\n+ *\n+ * AGL_GMX_TX_STAT2 = AGL_GMX_TX_STATS_OCTS\n+ *\n+ *\n+ * Notes:\n+ * - Octect counts are the sum of all data transmitted on the wire including\n+ * packet data, pad bytes, fcs bytes, pause bytes, and jam bytes. The octect\n+ * counts do not include PREAMBLE byte or EXTEND cycles.\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_stat2 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_stat2_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 octs : 48;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_stat2_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_stat2_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat2_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_stat2_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat2_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_stat2_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_stat2_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat2_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_stat2_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_stat2_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat2_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_stat2_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_stat2 cvmx_agl_gmx_txx_stat2_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_stat3\n+ *\n+ * AGL_GMX_TX_STAT3 = AGL_GMX_TX_STATS_PKTS\n+ *\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_stat3 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_stat3_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 pkts : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_stat3_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_stat3_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat3_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_stat3_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat3_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_stat3_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_stat3_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat3_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_stat3_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_stat3_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat3_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_stat3_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_stat3 cvmx_agl_gmx_txx_stat3_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_stat4\n+ *\n+ * AGL_GMX_TX_STAT4 = AGL_GMX_TX_STATS_HIST1 (64) / AGL_GMX_TX_STATS_HIST0 (<64)\n+ *\n+ *\n+ * Notes:\n+ * - Packet length is the sum of all data transmitted on the wire for the given\n+ * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam\n+ * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles.\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_stat4 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_stat4_s {\n+\t\tu64 hist1 : 32;\n+\t\tu64 hist0 : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_stat4_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_stat4_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat4_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_stat4_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat4_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_stat4_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_stat4_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat4_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_stat4_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_stat4_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat4_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_stat4_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_stat4 cvmx_agl_gmx_txx_stat4_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_stat5\n+ *\n+ * AGL_GMX_TX_STAT5 = AGL_GMX_TX_STATS_HIST3 (128- 255) / AGL_GMX_TX_STATS_HIST2 (65- 127)\n+ *\n+ *\n+ * Notes:\n+ * - Packet length is the sum of all data transmitted on the wire for the given\n+ * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam\n+ * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles.\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_stat5 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_stat5_s {\n+\t\tu64 hist3 : 32;\n+\t\tu64 hist2 : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_stat5_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_stat5_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat5_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_stat5_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat5_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_stat5_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_stat5_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat5_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_stat5_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_stat5_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat5_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_stat5_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_stat5 cvmx_agl_gmx_txx_stat5_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_stat6\n+ *\n+ * AGL_GMX_TX_STAT6 = AGL_GMX_TX_STATS_HIST5 (512-1023) / AGL_GMX_TX_STATS_HIST4 (256-511)\n+ *\n+ *\n+ * Notes:\n+ * - Packet length is the sum of all data transmitted on the wire for the given\n+ * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam\n+ * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles.\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_stat6 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_stat6_s {\n+\t\tu64 hist5 : 32;\n+\t\tu64 hist4 : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_stat6_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_stat6_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat6_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_stat6_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat6_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_stat6_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_stat6_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat6_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_stat6_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_stat6_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat6_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_stat6_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_stat6 cvmx_agl_gmx_txx_stat6_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_stat7\n+ *\n+ * AGL_GMX_TX_STAT7 = AGL_GMX_TX_STATS_HIST7 (1024-1518) / AGL_GMX_TX_STATS_HIST6 (>1518)\n+ *\n+ *\n+ * Notes:\n+ * - Packet length is the sum of all data transmitted on the wire for the given\n+ * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam\n+ * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles.\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_stat7 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_stat7_s {\n+\t\tu64 hist7 : 32;\n+\t\tu64 hist6 : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_stat7_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_stat7_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat7_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_stat7_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat7_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_stat7_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_stat7_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat7_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_stat7_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_stat7_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat7_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_stat7_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_stat7 cvmx_agl_gmx_txx_stat7_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_stat8\n+ *\n+ * AGL_GMX_TX_STAT8 = AGL_GMX_TX_STATS_MCST / AGL_GMX_TX_STATS_BCST\n+ *\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the\n+ * packet. GMX assumes that the DMAC lies in the first 6 bytes of the packet\n+ * as per the 802.3 frame definition. If the system requires additional data\n+ * before the L2 header, then the MCST and BCST counters may not reflect\n+ * reality and should be ignored by software.\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_stat8 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_stat8_s {\n+\t\tu64 mcst : 32;\n+\t\tu64 bcst : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_stat8_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_stat8_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat8_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_stat8_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat8_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_stat8_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_stat8_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat8_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_stat8_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_stat8_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat8_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_stat8_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_stat8 cvmx_agl_gmx_txx_stat8_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_stat9\n+ *\n+ * AGL_GMX_TX_STAT9 = AGL_GMX_TX_STATS_UNDFLW / AGL_GMX_TX_STATS_CTL\n+ *\n+ *\n+ * Notes:\n+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set\n+ * - Counters will wrap\n+ * - Not reset when MIX*_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_txx_stat9 {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_stat9_s {\n+\t\tu64 undflw : 32;\n+\t\tu64 ctl : 32;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_stat9_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_stat9_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat9_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_stat9_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat9_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_stat9_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_stat9_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat9_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_stat9_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_stat9_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_stat9_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_stat9_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_stat9 cvmx_agl_gmx_txx_stat9_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_stats_ctl\n+ *\n+ * AGL_GMX_TX_STATS_CTL = TX Stats Control register\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_txx_stats_ctl {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 rd_clr : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_stats_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_stats_ctl cvmx_agl_gmx_txx_stats_ctl_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx#_thresh\n+ *\n+ * AGL_GMX_TX_THRESH = Packet TX Threshold\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_txx_thresh {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_txx_thresh_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 cnt : 6;\n+\t} s;\n+\tstruct cvmx_agl_gmx_txx_thresh_s cn52xx;\n+\tstruct cvmx_agl_gmx_txx_thresh_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_txx_thresh_s cn56xx;\n+\tstruct cvmx_agl_gmx_txx_thresh_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_txx_thresh_s cn61xx;\n+\tstruct cvmx_agl_gmx_txx_thresh_s cn63xx;\n+\tstruct cvmx_agl_gmx_txx_thresh_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_txx_thresh_s cn66xx;\n+\tstruct cvmx_agl_gmx_txx_thresh_s cn68xx;\n+\tstruct cvmx_agl_gmx_txx_thresh_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_txx_thresh_s cn70xx;\n+\tstruct cvmx_agl_gmx_txx_thresh_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_txx_thresh cvmx_agl_gmx_txx_thresh_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx_bp\n+ *\n+ * AGL_GMX_TX_BP = Packet TX BackPressure Register\n+ *\n+ *\n+ * Notes:\n+ * BP[0] will be reset when MIX0_CTL[RESET] is set to 1.\n+ * BP[1] will be reset when MIX1_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_tx_bp {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_tx_bp_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 bp : 2;\n+\t} s;\n+\tstruct cvmx_agl_gmx_tx_bp_s cn52xx;\n+\tstruct cvmx_agl_gmx_tx_bp_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_tx_bp_cn56xx {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 bp : 1;\n+\t} cn56xx;\n+\tstruct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_tx_bp_s cn61xx;\n+\tstruct cvmx_agl_gmx_tx_bp_s cn63xx;\n+\tstruct cvmx_agl_gmx_tx_bp_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_tx_bp_s cn66xx;\n+\tstruct cvmx_agl_gmx_tx_bp_s cn68xx;\n+\tstruct cvmx_agl_gmx_tx_bp_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_tx_bp_cn56xx cn70xx;\n+\tstruct cvmx_agl_gmx_tx_bp_cn56xx cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_tx_bp cvmx_agl_gmx_tx_bp_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx_col_attempt\n+ *\n+ * AGL_GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_tx_col_attempt {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 limit : 5;\n+\t} s;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s cn52xx;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s cn56xx;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s cn61xx;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s cn63xx;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s cn66xx;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s cn68xx;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s cn70xx;\n+\tstruct cvmx_agl_gmx_tx_col_attempt_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_tx_col_attempt cvmx_agl_gmx_tx_col_attempt_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx_ifg\n+ *\n+ * Common\n+ * AGL_GMX_TX_IFG = Packet TX Interframe Gap\n+ */\n+union cvmx_agl_gmx_tx_ifg {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_tx_ifg_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 ifg2 : 4;\n+\t\tu64 ifg1 : 4;\n+\t} s;\n+\tstruct cvmx_agl_gmx_tx_ifg_s cn52xx;\n+\tstruct cvmx_agl_gmx_tx_ifg_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_tx_ifg_s cn56xx;\n+\tstruct cvmx_agl_gmx_tx_ifg_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_tx_ifg_s cn61xx;\n+\tstruct cvmx_agl_gmx_tx_ifg_s cn63xx;\n+\tstruct cvmx_agl_gmx_tx_ifg_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_tx_ifg_s cn66xx;\n+\tstruct cvmx_agl_gmx_tx_ifg_s cn68xx;\n+\tstruct cvmx_agl_gmx_tx_ifg_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_tx_ifg_s cn70xx;\n+\tstruct cvmx_agl_gmx_tx_ifg_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_tx_ifg cvmx_agl_gmx_tx_ifg_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx_int_en\n+ *\n+ * AGL_GMX_TX_INT_EN = Interrupt Enable\n+ *\n+ *\n+ * Notes:\n+ * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0], PTP_LOST[0] will be reset when MIX0_CTL[RESET] is set to 1.\n+ * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1.\n+ * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1.\n+ */\n+union cvmx_agl_gmx_tx_int_en {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_tx_int_en_s {\n+\t\tu64 reserved_22_63 : 42;\n+\t\tu64 ptp_lost : 2;\n+\t\tu64 reserved_18_19 : 2;\n+\t\tu64 late_col : 2;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 xsdef : 2;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tu64 xscol : 2;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 undflw : 2;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_tx_int_en_cn52xx {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 late_col : 2;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 xsdef : 2;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tu64 xscol : 2;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 undflw : 2;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn52xx;\n+\tstruct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1;\n+\tstruct cvmx_agl_gmx_tx_int_en_cn56xx {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 late_col : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 xsdef : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 xscol : 1;\n+\t\tu64 reserved_3_7 : 5;\n+\t\tu64 undflw : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn56xx;\n+\tstruct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_tx_int_en_s cn61xx;\n+\tstruct cvmx_agl_gmx_tx_int_en_s cn63xx;\n+\tstruct cvmx_agl_gmx_tx_int_en_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_tx_int_en_s cn66xx;\n+\tstruct cvmx_agl_gmx_tx_int_en_s cn68xx;\n+\tstruct cvmx_agl_gmx_tx_int_en_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_tx_int_en_cn70xx {\n+\t\tu64 reserved_21_63 : 43;\n+\t\tu64 ptp_lost : 1;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 late_col : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 xsdef : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 xscol : 1;\n+\t\tu64 reserved_3_7 : 5;\n+\t\tu64 undflw : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn70xx;\n+\tstruct cvmx_agl_gmx_tx_int_en_cn70xx cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_tx_int_en cvmx_agl_gmx_tx_int_en_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx_int_reg\n+ *\n+ * AGL_GMX_TX_INT_REG = Interrupt Register\n+ *\n+ *\n+ * Notes:\n+ * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0], PTP_LOST[0] will be reset when MIX0_CTL[RESET] is set to 1.\n+ * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1.\n+ * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1.\n+ */\n+union cvmx_agl_gmx_tx_int_reg {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_tx_int_reg_s {\n+\t\tu64 reserved_22_63 : 42;\n+\t\tu64 ptp_lost : 2;\n+\t\tu64 reserved_18_19 : 2;\n+\t\tu64 late_col : 2;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 xsdef : 2;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tu64 xscol : 2;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 undflw : 2;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_tx_int_reg_cn52xx {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 late_col : 2;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 xsdef : 2;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tu64 xscol : 2;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 undflw : 2;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn52xx;\n+\tstruct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;\n+\tstruct cvmx_agl_gmx_tx_int_reg_cn56xx {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 late_col : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 xsdef : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 xscol : 1;\n+\t\tu64 reserved_3_7 : 5;\n+\t\tu64 undflw : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn56xx;\n+\tstruct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_tx_int_reg_s cn61xx;\n+\tstruct cvmx_agl_gmx_tx_int_reg_s cn63xx;\n+\tstruct cvmx_agl_gmx_tx_int_reg_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_tx_int_reg_s cn66xx;\n+\tstruct cvmx_agl_gmx_tx_int_reg_s cn68xx;\n+\tstruct cvmx_agl_gmx_tx_int_reg_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_tx_int_reg_cn70xx {\n+\t\tu64 reserved_21_63 : 43;\n+\t\tu64 ptp_lost : 1;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 late_col : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 xsdef : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 xscol : 1;\n+\t\tu64 reserved_3_7 : 5;\n+\t\tu64 undflw : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pko_nxa : 1;\n+\t} cn70xx;\n+\tstruct cvmx_agl_gmx_tx_int_reg_cn70xx cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_tx_int_reg cvmx_agl_gmx_tx_int_reg_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx_jam\n+ *\n+ * AGL_GMX_TX_JAM = Packet TX Jam Pattern\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_tx_jam {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_tx_jam_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 jam : 8;\n+\t} s;\n+\tstruct cvmx_agl_gmx_tx_jam_s cn52xx;\n+\tstruct cvmx_agl_gmx_tx_jam_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_tx_jam_s cn56xx;\n+\tstruct cvmx_agl_gmx_tx_jam_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_tx_jam_s cn61xx;\n+\tstruct cvmx_agl_gmx_tx_jam_s cn63xx;\n+\tstruct cvmx_agl_gmx_tx_jam_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_tx_jam_s cn66xx;\n+\tstruct cvmx_agl_gmx_tx_jam_s cn68xx;\n+\tstruct cvmx_agl_gmx_tx_jam_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_tx_jam_s cn70xx;\n+\tstruct cvmx_agl_gmx_tx_jam_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_tx_jam cvmx_agl_gmx_tx_jam_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx_lfsr\n+ *\n+ * AGL_GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_tx_lfsr {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 lfsr : 16;\n+\t} s;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s cn52xx;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s cn56xx;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s cn61xx;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s cn63xx;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s cn66xx;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s cn68xx;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s cn70xx;\n+\tstruct cvmx_agl_gmx_tx_lfsr_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_tx_lfsr cvmx_agl_gmx_tx_lfsr_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx_ovr_bp\n+ *\n+ * AGL_GMX_TX_OVR_BP = Packet TX Override BackPressure\n+ *\n+ *\n+ * Notes:\n+ * IGN_FULL[0], BP[0], EN[0] will be reset when MIX0_CTL[RESET] is set to 1.\n+ * IGN_FULL[1], BP[1], EN[1] will be reset when MIX1_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_gmx_tx_ovr_bp {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 en : 2;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 bp : 2;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 ign_full : 2;\n+\t} s;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_cn56xx {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 en : 1;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 bp : 1;\n+\t\tu64 reserved_1_3 : 3;\n+\t\tu64 ign_full : 1;\n+\t} cn56xx;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_s cn61xx;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_s cn63xx;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_s cn66xx;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_s cn68xx;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn70xx;\n+\tstruct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_tx_ovr_bp cvmx_agl_gmx_tx_ovr_bp_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx_pause_pkt_dmac\n+ *\n+ * AGL_GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_tx_pause_pkt_dmac {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 dmac : 48;\n+\t} s;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn61xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn66xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn70xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_tx_pause_pkt_dmac cvmx_agl_gmx_tx_pause_pkt_dmac_t;\n+\n+/**\n+ * cvmx_agl_gmx_tx_pause_pkt_type\n+ *\n+ * AGL_GMX_TX_PAUSE_PKT_TYPE = Packet TX Pause Packet TYPE field\n+ *\n+ *\n+ * Notes:\n+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.\n+ *\n+ */\n+union cvmx_agl_gmx_tx_pause_pkt_type {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 type : 16;\n+\t} s;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s cn61xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s cn66xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xxp1;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s cn70xx;\n+\tstruct cvmx_agl_gmx_tx_pause_pkt_type_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_tx_pause_pkt_type cvmx_agl_gmx_tx_pause_pkt_type_t;\n+\n+/**\n+ * cvmx_agl_gmx_wol_ctl\n+ */\n+union cvmx_agl_gmx_wol_ctl {\n+\tu64 u64;\n+\tstruct cvmx_agl_gmx_wol_ctl_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 magic_en : 1;\n+\t\tu64 reserved_17_31 : 15;\n+\t\tu64 direct_en : 1;\n+\t\tu64 reserved_1_15 : 15;\n+\t\tu64 en : 1;\n+\t} s;\n+\tstruct cvmx_agl_gmx_wol_ctl_s cn70xx;\n+\tstruct cvmx_agl_gmx_wol_ctl_s cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_gmx_wol_ctl cvmx_agl_gmx_wol_ctl_t;\n+\n+/**\n+ * cvmx_agl_prt#_ctl\n+ *\n+ * AGL_PRT_CTL = AGL Port Control\n+ *\n+ *\n+ * Notes:\n+ * The RGMII timing specification requires that devices transmit clock and\n+ * data synchronously. The specification requires external sources (namely\n+ * the PC board trace routes) to introduce the appropriate 1.5 to 2.0 ns of\n+ * delay.\n+ *\n+ * To eliminate the need for the PC board delays, the MIX RGMII interface\n+ * has optional onboard DLL's for both transmit and receive. For correct\n+ * operation, at most one of the transmitter, board, or receiver involved\n+ * in an RGMII link should introduce delay. By default/reset,\n+ * the MIX RGMII receivers delay the received clock, and the MIX\n+ * RGMII transmitters do not delay the transmitted clock. Whether this\n+ * default works as-is with a given link partner depends on the behavior\n+ * of the link partner and the PC board.\n+ *\n+ * These are the possible modes of MIX RGMII receive operation:\n+ * o AGL_PRTx_CTL[CLKRX_BYP] = 0 (reset value) - The OCTEON MIX RGMII\n+ * receive interface introduces clock delay using its internal DLL.\n+ * This mode is appropriate if neither the remote\n+ * transmitter nor the PC board delays the clock.\n+ * o AGL_PRTx_CTL[CLKRX_BYP] = 1, [CLKRX_SET] = 0x0 - The OCTEON MIX\n+ * RGMII receive interface introduces no clock delay. This mode\n+ * is appropriate if either the remote transmitter or the PC board\n+ * delays the clock.\n+ *\n+ * These are the possible modes of MIX RGMII transmit operation:\n+ * o AGL_PRTx_CTL[CLKTX_BYP] = 1, [CLKTX_SET] = 0x0 (reset value) -\n+ * The OCTEON MIX RGMII transmit interface introduces no clock\n+ * delay. This mode is appropriate is either the remote receiver\n+ * or the PC board delays the clock.\n+ * o AGL_PRTx_CTL[CLKTX_BYP] = 0 - The OCTEON MIX RGMII transmit\n+ * interface introduces clock delay using its internal DLL.\n+ * This mode is appropriate if neither the remote receiver\n+ * nor the PC board delays the clock.\n+ *\n+ * AGL_PRT0_CTL will be reset when MIX0_CTL[RESET] is set to 1.\n+ * AGL_PRT1_CTL will be reset when MIX1_CTL[RESET] is set to 1.\n+ */\n+union cvmx_agl_prtx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_agl_prtx_ctl_s {\n+\t\tu64 drv_byp : 1;\n+\t\tu64 reserved_62_62 : 1;\n+\t\tu64 cmp_pctl : 6;\n+\t\tu64 reserved_54_55 : 2;\n+\t\tu64 cmp_nctl : 6;\n+\t\tu64 reserved_46_47 : 2;\n+\t\tu64 drv_pctl : 6;\n+\t\tu64 reserved_38_39 : 2;\n+\t\tu64 drv_nctl : 6;\n+\t\tu64 reserved_31_31 : 1;\n+\t\tu64 clk_set : 7;\n+\t\tu64 clkrx_byp : 1;\n+\t\tu64 clkrx_set : 7;\n+\t\tu64 clktx_byp : 1;\n+\t\tu64 clktx_set : 7;\n+\t\tu64 refclk_sel : 2;\n+\t\tu64 reserved_5_5 : 1;\n+\t\tu64 dllrst : 1;\n+\t\tu64 comp : 1;\n+\t\tu64 enable : 1;\n+\t\tu64 clkrst : 1;\n+\t\tu64 mode : 1;\n+\t} s;\n+\tstruct cvmx_agl_prtx_ctl_cn61xx {\n+\t\tu64 drv_byp : 1;\n+\t\tu64 reserved_62_62 : 1;\n+\t\tu64 cmp_pctl : 6;\n+\t\tu64 reserved_54_55 : 2;\n+\t\tu64 cmp_nctl : 6;\n+\t\tu64 reserved_46_47 : 2;\n+\t\tu64 drv_pctl : 6;\n+\t\tu64 reserved_38_39 : 2;\n+\t\tu64 drv_nctl : 6;\n+\t\tu64 reserved_29_31 : 3;\n+\t\tu64 clk_set : 5;\n+\t\tu64 clkrx_byp : 1;\n+\t\tu64 reserved_21_22 : 2;\n+\t\tu64 clkrx_set : 5;\n+\t\tu64 clktx_byp : 1;\n+\t\tu64 reserved_13_14 : 2;\n+\t\tu64 clktx_set : 5;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 dllrst : 1;\n+\t\tu64 comp : 1;\n+\t\tu64 enable : 1;\n+\t\tu64 clkrst : 1;\n+\t\tu64 mode : 1;\n+\t} cn61xx;\n+\tstruct cvmx_agl_prtx_ctl_cn61xx cn63xx;\n+\tstruct cvmx_agl_prtx_ctl_cn61xx cn63xxp1;\n+\tstruct cvmx_agl_prtx_ctl_cn61xx cn66xx;\n+\tstruct cvmx_agl_prtx_ctl_cn61xx cn68xx;\n+\tstruct cvmx_agl_prtx_ctl_cn61xx cn68xxp1;\n+\tstruct cvmx_agl_prtx_ctl_cn70xx {\n+\t\tu64 drv_byp : 1;\n+\t\tu64 reserved_61_62 : 2;\n+\t\tu64 cmp_pctl : 5;\n+\t\tu64 reserved_53_55 : 3;\n+\t\tu64 cmp_nctl : 5;\n+\t\tu64 reserved_45_47 : 3;\n+\t\tu64 drv_pctl : 5;\n+\t\tu64 reserved_37_39 : 3;\n+\t\tu64 drv_nctl : 5;\n+\t\tu64 reserved_31_31 : 1;\n+\t\tu64 clk_set : 7;\n+\t\tu64 clkrx_byp : 1;\n+\t\tu64 clkrx_set : 7;\n+\t\tu64 clktx_byp : 1;\n+\t\tu64 clktx_set : 7;\n+\t\tu64 refclk_sel : 2;\n+\t\tu64 reserved_5_5 : 1;\n+\t\tu64 dllrst : 1;\n+\t\tu64 comp : 1;\n+\t\tu64 enable : 1;\n+\t\tu64 clkrst : 1;\n+\t\tu64 mode : 1;\n+\t} cn70xx;\n+\tstruct cvmx_agl_prtx_ctl_cn70xx cn70xxp1;\n+};\n+\n+typedef union cvmx_agl_prtx_ctl cvmx_agl_prtx_ctl_t;\n+\n+#endif\n", "prefixes": [ "v1", "03/50" ] }